1/*-
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 50842 1999-09-03 10:57:17Z phk $
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_FEATURE 0x01 /* (W) feature register */
35#define ATA_F_DMA 0x01 /* enable DMA */
36#define ATA_F_OVL 0x02 /* enable overlap */
37
38#define ATA_COUNT 0x02 /* (W) sector count */
39#define ATA_IREASON 0x02 /* (R) interrupt reason */
40#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
41#define ATA_I_IN 0x02 /* read (1) | write (0) */
42#define ATA_I_RELEASE 0x04 /* released bus (1) */
43#define ATA_I_TAGMASK 0xf8 /* tag mask */
44
45#define ATA_SECTOR 0x03 /* sector # */
46#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
47#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
48#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
49#define ATA_D_LBA 0x40 /* use LBA adressing */
50#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
51
52#define ATA_CMD 0x07 /* command register */
53#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
54#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
55#define ATA_C_READ 0x20 /* read command */
56#define ATA_C_WRITE 0x30 /* write command */
57#define ATA_C_READ_MULTI 0xc4 /* read multi command */
58#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
59#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
60#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
61#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
62#define ATA_C_PACKET_CMD 0xa0 /* packet command */
63#define ATA_C_SETFEATURES 0xef /* features command */
64#define ATA_C_FEA_SETXFER 0x03 /* set transfer mode */
65
66#define ATA_STATUS 0x07 /* status register */
67#define ATA_S_ERROR 0x01 /* error */
68#define ATA_S_INDEX 0x02 /* index */
69#define ATA_S_CORR 0x04 /* data corrected */
70#define ATA_S_DRQ 0x08 /* data request */
71#define ATA_S_DSC 0x10 /* drive seek completed */
72#define ATA_S_SERV 0x10 /* drive needs service */
73#define ATA_S_DWF 0x20 /* drive write fault */
74#define ATA_S_DMRD 0x20 /* DMA ready */
75#define ATA_S_DRDY 0x40 /* drive ready */
76#define ATA_S_BSY 0x80 /* busy */
77
78#define ATA_ALTPORT 0x206 /* alternate Status register */
79#define ATA_A_IDS 0x02 /* disable interrupts */
80#define ATA_A_RESET 0x04 /* RESET controller */
81#define ATA_A_4BIT 0x08 /* 4 head bits */
82
83/* misc defines */
84#define ATA_MASTER 0x00
85#define ATA_SLAVE 0x10
86#define ATA_IOSIZE 0x08
87#define ATA_OP_FINISHED 0x00
88#define ATA_OP_CONTINUES 0x01
89
90/* busmaster DMA related defines */
91#define ATA_BM_OFFSET1 0x08
92#define ATA_DMA_ENTRIES 256
93#define ATA_DMA_EOT 0x80000000
94
95#define ATA_BMCMD_PORT 0x00
96#define ATA_BMCMD_START_STOP 0x01
97#define ATA_BMCMD_WRITE_READ 0x08
98
99#define ATA_BMSTAT_PORT 0x02
100#define ATA_BMSTAT_MASK 0x07
101#define ATA_BMSTAT_ACTIVE 0x01
102#define ATA_BMSTAT_ERROR 0x02
103#define ATA_BMSTAT_INTERRUPT 0x04
104#define ATA_BMSTAT_DMA_MASTER 0x20
105#define ATA_BMSTAT_DMA_SLAVE 0x40
106
107#define ATA_BMDTP_PORT 0x04
108
109#define ATA_WDMA2 0x22
110#define ATA_UDMA2 0x42
111
112/* structure for holding DMA address data */
113struct ata_dmaentry {
114 u_int32_t base;
115 u_int32_t count;
116};
117
118/* structure describing an ATA device */
119struct ata_softc {
120 int32_t unit; /* unit on this controller */
121 int32_t lun; /* logical unit # */
122 struct device *dev; /* device handle */
123 int32_t ioaddr; /* port addr */
124 int32_t altioaddr; /* alternate port addr */
125 int32_t bmaddr; /* bus master DMA port */
126 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
127 int32_t flags; /* controller flags */
128 int32_t devices; /* what is present */
129#define ATA_ATA_MASTER 0x01
130#define ATA_ATA_SLAVE 0x02
131#define ATA_ATAPI_MASTER 0x04
132#define ATA_ATAPI_SLAVE 0x08
133
134 u_int8_t status; /* last controller status */
135 u_int8_t error; /* last controller error */
136 int32_t active; /* active processing request */
137#define ATA_IDLE 0x0
138#define ATA_IMMEDIATE 0x0
139#define ATA_WAIT_INTR 0x1
140#define ATA_IGNORE_INTR 0x2
141#define ATA_ACTIVE_ATA 0x3
142#define ATA_ACTIVE_ATAPI 0x4
143
144 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
145 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
146};
147
148#define MAXATA 8
149
150extern struct ata_softc *atadevices[];
151
152/* public prototypes */
153void ata_start(struct ata_softc *);
154int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
155int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
156int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
157int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
158void ata_dmastart(struct ata_softc *, int32_t);
159int32_t ata_dmastatus(struct ata_softc *, int32_t);
160int32_t ata_dmadone(struct ata_softc *, int32_t);
161void bswap(int8_t *, int32_t);
162void btrim(int8_t *, int32_t);
163void bpack(int8_t *, int8_t *, int32_t);
164
165void ad_transfer(struct ad_request *);
166int32_t ad_interrupt(struct ad_request *);
167
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 50842 1999-09-03 10:57:17Z phk $
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_FEATURE 0x01 /* (W) feature register */
35#define ATA_F_DMA 0x01 /* enable DMA */
36#define ATA_F_OVL 0x02 /* enable overlap */
37
38#define ATA_COUNT 0x02 /* (W) sector count */
39#define ATA_IREASON 0x02 /* (R) interrupt reason */
40#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
41#define ATA_I_IN 0x02 /* read (1) | write (0) */
42#define ATA_I_RELEASE 0x04 /* released bus (1) */
43#define ATA_I_TAGMASK 0xf8 /* tag mask */
44
45#define ATA_SECTOR 0x03 /* sector # */
46#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
47#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
48#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
49#define ATA_D_LBA 0x40 /* use LBA adressing */
50#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
51
52#define ATA_CMD 0x07 /* command register */
53#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
54#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
55#define ATA_C_READ 0x20 /* read command */
56#define ATA_C_WRITE 0x30 /* write command */
57#define ATA_C_READ_MULTI 0xc4 /* read multi command */
58#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
59#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
60#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
61#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
62#define ATA_C_PACKET_CMD 0xa0 /* packet command */
63#define ATA_C_SETFEATURES 0xef /* features command */
64#define ATA_C_FEA_SETXFER 0x03 /* set transfer mode */
65
66#define ATA_STATUS 0x07 /* status register */
67#define ATA_S_ERROR 0x01 /* error */
68#define ATA_S_INDEX 0x02 /* index */
69#define ATA_S_CORR 0x04 /* data corrected */
70#define ATA_S_DRQ 0x08 /* data request */
71#define ATA_S_DSC 0x10 /* drive seek completed */
72#define ATA_S_SERV 0x10 /* drive needs service */
73#define ATA_S_DWF 0x20 /* drive write fault */
74#define ATA_S_DMRD 0x20 /* DMA ready */
75#define ATA_S_DRDY 0x40 /* drive ready */
76#define ATA_S_BSY 0x80 /* busy */
77
78#define ATA_ALTPORT 0x206 /* alternate Status register */
79#define ATA_A_IDS 0x02 /* disable interrupts */
80#define ATA_A_RESET 0x04 /* RESET controller */
81#define ATA_A_4BIT 0x08 /* 4 head bits */
82
83/* misc defines */
84#define ATA_MASTER 0x00
85#define ATA_SLAVE 0x10
86#define ATA_IOSIZE 0x08
87#define ATA_OP_FINISHED 0x00
88#define ATA_OP_CONTINUES 0x01
89
90/* busmaster DMA related defines */
91#define ATA_BM_OFFSET1 0x08
92#define ATA_DMA_ENTRIES 256
93#define ATA_DMA_EOT 0x80000000
94
95#define ATA_BMCMD_PORT 0x00
96#define ATA_BMCMD_START_STOP 0x01
97#define ATA_BMCMD_WRITE_READ 0x08
98
99#define ATA_BMSTAT_PORT 0x02
100#define ATA_BMSTAT_MASK 0x07
101#define ATA_BMSTAT_ACTIVE 0x01
102#define ATA_BMSTAT_ERROR 0x02
103#define ATA_BMSTAT_INTERRUPT 0x04
104#define ATA_BMSTAT_DMA_MASTER 0x20
105#define ATA_BMSTAT_DMA_SLAVE 0x40
106
107#define ATA_BMDTP_PORT 0x04
108
109#define ATA_WDMA2 0x22
110#define ATA_UDMA2 0x42
111
112/* structure for holding DMA address data */
113struct ata_dmaentry {
114 u_int32_t base;
115 u_int32_t count;
116};
117
118/* structure describing an ATA device */
119struct ata_softc {
120 int32_t unit; /* unit on this controller */
121 int32_t lun; /* logical unit # */
122 struct device *dev; /* device handle */
123 int32_t ioaddr; /* port addr */
124 int32_t altioaddr; /* alternate port addr */
125 int32_t bmaddr; /* bus master DMA port */
126 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
127 int32_t flags; /* controller flags */
128 int32_t devices; /* what is present */
129#define ATA_ATA_MASTER 0x01
130#define ATA_ATA_SLAVE 0x02
131#define ATA_ATAPI_MASTER 0x04
132#define ATA_ATAPI_SLAVE 0x08
133
134 u_int8_t status; /* last controller status */
135 u_int8_t error; /* last controller error */
136 int32_t active; /* active processing request */
137#define ATA_IDLE 0x0
138#define ATA_IMMEDIATE 0x0
139#define ATA_WAIT_INTR 0x1
140#define ATA_IGNORE_INTR 0x2
141#define ATA_ACTIVE_ATA 0x3
142#define ATA_ACTIVE_ATAPI 0x4
143
144 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
145 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
146};
147
148#define MAXATA 8
149
150extern struct ata_softc *atadevices[];
151
152/* public prototypes */
153void ata_start(struct ata_softc *);
154int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
155int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
156int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
157int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
158void ata_dmastart(struct ata_softc *, int32_t);
159int32_t ata_dmastatus(struct ata_softc *, int32_t);
160int32_t ata_dmadone(struct ata_softc *, int32_t);
161void bswap(int8_t *, int32_t);
162void btrim(int8_t *, int32_t);
163void bpack(int8_t *, int8_t *, int32_t);
164
165void ad_transfer(struct ad_request *);
166int32_t ad_interrupt(struct ad_request *);
167