1/*-
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
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20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $Id: ata-all.h,v 1.5 1999/03/28 18:57:18 sos Exp $
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_FEATURE 0x01 /* (W) feature register */
35#define ATA_F_DMA 0x01 /* enable DMA */
36#define ATA_F_OVL 0x02 /* enable overlap */
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120 u_int32_t base;
121 u_int32_t count;
122};
123
124/* structure describing an ATA device */
125struct ata_softc {
126 int32_t unit; /* unit on this controller */
127 int32_t lun; /* logical unit # */
128 struct device *dev; /* device handle */
129 int32_t ioaddr; /* port addr */
130 int32_t altioaddr; /* alternate port addr */
131 int32_t bmaddr; /* bus master DMA port */
132 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
133 int32_t flags; /* controller flags */
134 int32_t devices; /* what is present */
135 u_int8_t status; /* last controller status */
136 u_int8_t error; /* last controller error */
--- 29 unchanged lines hidden ---
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $Id: ata-all.h,v 1.5 1999/03/28 18:57:18 sos Exp $
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_FEATURE 0x01 /* (W) feature register */
35#define ATA_F_DMA 0x01 /* enable DMA */
36#define ATA_F_OVL 0x02 /* enable overlap */
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120 u_int32_t base;
121 u_int32_t count;
122};
123
124/* structure describing an ATA device */
125struct ata_softc {
126 int32_t unit; /* unit on this controller */
127 int32_t lun; /* logical unit # */
128 struct device *dev; /* device handle */
129 int32_t ioaddr; /* port addr */
130 int32_t altioaddr; /* alternate port addr */
131 int32_t bmaddr; /* bus master DMA port */
132 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
133 int32_t flags; /* controller flags */
134 int32_t devices; /* what is present */
135 u_int8_t status; /* last controller status */
136 u_int8_t error; /* last controller error */
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