| am335x.dtsi (254559) | am335x.dtsi (254598) |
|---|---|
| 1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/boot/fdt/dts/am335x.dtsi 254559 2013-08-20 12:33:35Z ian $ | 26 * $FreeBSD: head/sys/boot/fdt/dts/am335x.dtsi 254598 2013-08-21 14:33:02Z ian $ |
| 27 */ 28 29/ { 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 interrupt-parent = <&AINTC>; 34 --- 48 unchanged lines hidden (view full) --- 83 0x4804C000 0x1000 84 0x481AC000 0x1000 85 0x481AE000 0x1000 >; 86 interrupts = < 96 97 98 99 32 33 62 63 >; 87 interrupt-parent = <&AINTC>; 88 }; 89 90 uart0: serial@44E09000 { | 27 */ 28 29/ { 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 interrupt-parent = <&AINTC>; 34 --- 48 unchanged lines hidden (view full) --- 83 0x4804C000 0x1000 84 0x481AC000 0x1000 85 0x481AE000 0x1000 >; 86 interrupts = < 96 97 98 99 32 33 62 63 >; 87 interrupt-parent = <&AINTC>; 88 }; 89 90 uart0: serial@44E09000 { |
| 91 compatible = "ns16550"; | 91 compatible = "ti,ns16550"; |
| 92 reg = <0x44E09000 0x1000>; 93 reg-shift = <2>; 94 interrupts = < 72 >; 95 interrupt-parent = <&AINTC>; | 92 reg = <0x44E09000 0x1000>; 93 reg-shift = <2>; 94 interrupts = < 72 >; 95 interrupt-parent = <&AINTC>; |
| 96 clock-frequency = < 48000000 >; /* FIXME */ 97 }; | 96 clock-frequency = < 48000000 >; 97 uart-device-id = < 0 >; 98 }; 99 100 uart1: serial@48022000 { 101 compatible = "ti,ns16550"; 102 reg = <0x48022000 0x1000>; 103 reg-shift = <2>; 104 interrupts = < 73 >; 105 interrupt-parent = <&AINTC>; 106 clock-frequency = < 48000000 >; 107 uart-device-id = < 1 >; 108 status = "disabled"; 109 }; 110 111 uart2: serial@48024000 { 112 compatible = "ti,ns16550"; 113 reg = <0x48024000 0x1000>; 114 reg-shift = <2>; 115 interrupts = < 74 >; 116 interrupt-parent = <&AINTC>; 117 clock-frequency = < 48000000 >; 118 uart-device-id = < 2 >; 119 status = "disabled"; 120 }; 121 122 uart3: serial@481a6000 { 123 compatible = "ti,ns16550"; 124 reg = <0x481A6000 0x1000>; 125 reg-shift = <2>; 126 interrupts = < 44 >; 127 interrupt-parent = <&AINTC>; 128 clock-frequency = < 48000000 >; 129 uart-device-id = < 3 >; 130 status = "disabled"; 131 }; 132 133 uart4: serial@481a8000 { 134 compatible = "ti,ns16550"; 135 reg = <0x481A8000 0x1000>; 136 reg-shift = <2>; 137 interrupts = < 45 >; 138 interrupt-parent = <&AINTC>; 139 clock-frequency = < 48000000 >; 140 uart-device-id = < 4 >; 141 status = "disabled"; 142 }; 143 144 uart5: serial@481aa000 { 145 compatible = "ti,ns16550"; 146 reg = <0x481AA000 0x1000>; 147 reg-shift = <2>; 148 interrupts = < 46 >; 149 interrupt-parent = <&AINTC>; 150 clock-frequency = < 48000000 >; 151 uart-device-id = < 5 >; 152 status = "disabled"; 153 }; |
| 98 99 edma3@49000000 { 100 compatible = "ti,edma3"; 101 reg =< 0x49000000 0x100000 /* Channel Controller Regs */ 102 0x49800000 0x100000 /* Transfer Controller 0 Regs */ 103 0x49900000 0x100000 /* Transfer Controller 1 Regs */ 104 0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */ 105 interrupts = <12 13 14>; --- 139 unchanged lines hidden --- | 154 155 edma3@49000000 { 156 compatible = "ti,edma3"; 157 reg =< 0x49000000 0x100000 /* Channel Controller Regs */ 158 0x49800000 0x100000 /* Transfer Controller 0 Regs */ 159 0x49900000 0x100000 /* Transfer Controller 1 Regs */ 160 0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */ 161 interrupts = <12 13 14>; --- 139 unchanged lines hidden --- |