| uart_dev_z8530.c (155973) | uart_dev_z8530.c (157300) |
|---|---|
| 1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 155973 2006-02-24 05:40:17Z marcel $"); | 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 157300 2006-03-30 18:37:03Z marcel $"); |
| 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> --- 306 unchanged lines hidden (view full) --- 343z8530_bus_getsig(struct uart_softc *sc) 344{ 345 uint32_t new, old, sig; 346 uint8_t bes; 347 348 do { 349 old = sc->sc_hwsig; 350 sig = old; | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> --- 306 unchanged lines hidden (view full) --- 343z8530_bus_getsig(struct uart_softc *sc) 344{ 345 uint32_t new, old, sig; 346 uint8_t bes; 347 348 do { 349 old = sc->sc_hwsig; 350 sig = old; |
| 351 mtx_lock_spin(&sc->sc_hwmtx); | 351 uart_lock(sc->sc_hwmtx); |
| 352 bes = uart_getmreg(&sc->sc_bas, RR_BES); | 352 bes = uart_getmreg(&sc->sc_bas, RR_BES); |
| 353 mtx_unlock_spin(&sc->sc_hwmtx); | 353 uart_unlock(sc->sc_hwmtx); |
| 354 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 355 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 356 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 357 new = sig & ~SER_MASK_DELTA; 358 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 359 return (sig); 360} 361 362static int 363z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 364{ 365 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 366 struct uart_bas *bas; 367 int error; 368 369 bas = &sc->sc_bas; 370 error = 0; | 354 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 355 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 356 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 357 new = sig & ~SER_MASK_DELTA; 358 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 359 return (sig); 360} 361 362static int 363z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 364{ 365 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 366 struct uart_bas *bas; 367 int error; 368 369 bas = &sc->sc_bas; 370 error = 0; |
| 371 mtx_lock_spin(&sc->sc_hwmtx); | 371 uart_lock(sc->sc_hwmtx); |
| 372 switch (request) { 373 case UART_IOCTL_BREAK: 374 if (data) 375 z8530->tpc |= TPC_BRK; 376 else 377 z8530->tpc &= ~TPC_BRK; 378 uart_setmreg(bas, WR_TPC, z8530->tpc); 379 uart_barrier(bas); 380 break; 381 default: 382 error = EINVAL; 383 break; 384 } | 372 switch (request) { 373 case UART_IOCTL_BREAK: 374 if (data) 375 z8530->tpc |= TPC_BRK; 376 else 377 z8530->tpc &= ~TPC_BRK; 378 uart_setmreg(bas, WR_TPC, z8530->tpc); 379 uart_barrier(bas); 380 break; 381 default: 382 error = EINVAL; 383 break; 384 } |
| 385 mtx_unlock_spin(&sc->sc_hwmtx); | 385 uart_unlock(sc->sc_hwmtx); |
| 386 return (error); 387} 388 389static int 390z8530_bus_ipend(struct uart_softc *sc) 391{ 392 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 393 struct uart_bas *bas; 394 int ipend; 395 uint32_t sig; 396 uint8_t bes, ip, iv, src; 397 398 bas = &sc->sc_bas; 399 ipend = 0; 400 | 386 return (error); 387} 388 389static int 390z8530_bus_ipend(struct uart_softc *sc) 391{ 392 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 393 struct uart_bas *bas; 394 int ipend; 395 uint32_t sig; 396 uint8_t bes, ip, iv, src; 397 398 bas = &sc->sc_bas; 399 ipend = 0; 400 |
| 401 mtx_lock_spin(&sc->sc_hwmtx); | 401 uart_lock(sc->sc_hwmtx); |
| 402 switch (bas->chan) { 403 case 1: 404 ip = uart_getmreg(bas, RR_IP); 405 break; 406 case 2: /* XXX hack!!! */ 407 iv = uart_getmreg(bas, RR_IV) & 0x0E; 408 switch (iv) { 409 case IV_TEB: ip = IP_TIA; break; --- 39 unchanged lines hidden (view full) --- 449 } 450 } 451 452 if (ipend) { 453 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 454 uart_barrier(bas); 455 } 456 | 402 switch (bas->chan) { 403 case 1: 404 ip = uart_getmreg(bas, RR_IP); 405 break; 406 case 2: /* XXX hack!!! */ 407 iv = uart_getmreg(bas, RR_IV) & 0x0E; 408 switch (iv) { 409 case IV_TEB: ip = IP_TIA; break; --- 39 unchanged lines hidden (view full) --- 449 } 450 } 451 452 if (ipend) { 453 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 454 uart_barrier(bas); 455 } 456 |
| 457 mtx_unlock_spin(&sc->sc_hwmtx); | 457 uart_unlock(sc->sc_hwmtx); |
| 458 459 return (ipend); 460} 461 462static int 463z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 464 int stopbits, int parity) 465{ 466 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 467 int error; 468 | 458 459 return (ipend); 460} 461 462static int 463z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 464 int stopbits, int parity) 465{ 466 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 467 int error; 468 |
| 469 mtx_lock_spin(&sc->sc_hwmtx); | 469 uart_lock(sc->sc_hwmtx); |
| 470 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 471 &z8530->tpc); | 470 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 471 &z8530->tpc); |
| 472 mtx_unlock_spin(&sc->sc_hwmtx); | 472 uart_unlock(sc->sc_hwmtx); |
| 473 return (error); 474} 475 476static int 477z8530_bus_probe(struct uart_softc *sc) 478{ 479 char buf[80]; 480 int error; --- 13 unchanged lines hidden (view full) --- 494static int 495z8530_bus_receive(struct uart_softc *sc) 496{ 497 struct uart_bas *bas; 498 int xc; 499 uint8_t bes, src; 500 501 bas = &sc->sc_bas; | 473 return (error); 474} 475 476static int 477z8530_bus_probe(struct uart_softc *sc) 478{ 479 char buf[80]; 480 int error; --- 13 unchanged lines hidden (view full) --- 494static int 495z8530_bus_receive(struct uart_softc *sc) 496{ 497 struct uart_bas *bas; 498 int xc; 499 uint8_t bes, src; 500 501 bas = &sc->sc_bas; |
| 502 mtx_lock_spin(&sc->sc_hwmtx); | 502 uart_lock(sc->sc_hwmtx); |
| 503 bes = uart_getmreg(bas, RR_BES); 504 while (bes & BES_RXA) { 505 if (uart_rx_full(sc)) { 506 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 507 break; 508 } 509 xc = uart_getreg(bas, REG_DATA); 510 uart_barrier(bas); --- 17 unchanged lines hidden (view full) --- 528 uart_barrier(bas); 529 src = uart_getmreg(bas, RR_SRC); 530 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 531 uart_setreg(bas, REG_CTRL, CR_RSTERR); 532 uart_barrier(bas); 533 } 534 bes = uart_getmreg(bas, RR_BES); 535 } | 503 bes = uart_getmreg(bas, RR_BES); 504 while (bes & BES_RXA) { 505 if (uart_rx_full(sc)) { 506 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 507 break; 508 } 509 xc = uart_getreg(bas, REG_DATA); 510 uart_barrier(bas); --- 17 unchanged lines hidden (view full) --- 528 uart_barrier(bas); 529 src = uart_getmreg(bas, RR_SRC); 530 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 531 uart_setreg(bas, REG_CTRL, CR_RSTERR); 532 uart_barrier(bas); 533 } 534 bes = uart_getmreg(bas, RR_BES); 535 } |
| 536 mtx_unlock_spin(&sc->sc_hwmtx); | 536 uart_unlock(sc->sc_hwmtx); |
| 537 return (0); 538} 539 540static int 541z8530_bus_setsig(struct uart_softc *sc, int sig) 542{ 543 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 544 struct uart_bas *bas; --- 8 unchanged lines hidden (view full) --- 553 SER_DDTR); 554 } 555 if (sig & SER_DRTS) { 556 SIGCHG(sig & SER_RTS, new, SER_RTS, 557 SER_DRTS); 558 } 559 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 560 | 537 return (0); 538} 539 540static int 541z8530_bus_setsig(struct uart_softc *sc, int sig) 542{ 543 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 544 struct uart_bas *bas; --- 8 unchanged lines hidden (view full) --- 553 SER_DDTR); 554 } 555 if (sig & SER_DRTS) { 556 SIGCHG(sig & SER_RTS, new, SER_RTS, 557 SER_DRTS); 558 } 559 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 560 |
| 561 mtx_lock_spin(&sc->sc_hwmtx); | 561 uart_lock(sc->sc_hwmtx); |
| 562 if (new & SER_DTR) 563 z8530->tpc |= TPC_DTR; 564 else 565 z8530->tpc &= ~TPC_DTR; 566 if (new & SER_RTS) 567 z8530->tpc |= TPC_RTS; 568 else 569 z8530->tpc &= ~TPC_RTS; 570 uart_setmreg(bas, WR_TPC, z8530->tpc); 571 uart_barrier(bas); | 562 if (new & SER_DTR) 563 z8530->tpc |= TPC_DTR; 564 else 565 z8530->tpc &= ~TPC_DTR; 566 if (new & SER_RTS) 567 z8530->tpc |= TPC_RTS; 568 else 569 z8530->tpc &= ~TPC_RTS; 570 uart_setmreg(bas, WR_TPC, z8530->tpc); 571 uart_barrier(bas); |
| 572 mtx_unlock_spin(&sc->sc_hwmtx); | 572 uart_unlock(sc->sc_hwmtx); |
| 573 return (0); 574} 575 576static int 577z8530_bus_transmit(struct uart_softc *sc) 578{ 579 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 580 struct uart_bas *bas; 581 582 bas = &sc->sc_bas; | 573 return (0); 574} 575 576static int 577z8530_bus_transmit(struct uart_softc *sc) 578{ 579 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 580 struct uart_bas *bas; 581 582 bas = &sc->sc_bas; |
| 583 mtx_lock_spin(&sc->sc_hwmtx); | 583 uart_lock(sc->sc_hwmtx); |
| 584 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 585 ; 586 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 587 uart_barrier(bas); 588 sc->sc_txbusy = 1; 589 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ | 584 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 585 ; 586 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 587 uart_barrier(bas); 588 sc->sc_txbusy = 1; 589 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ |
| 590 mtx_unlock_spin(&sc->sc_hwmtx); | 590 uart_unlock(sc->sc_hwmtx); |
| 591 return (0); 592} | 591 return (0); 592} |