1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_z8530.c 119866 2003-09-07 21:51:03Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39#include <dev/uart/uart_dev_z8530.h>
40
41#include "uart_if.h"
42
43#define DEFAULT_RCLK 307200
44
45#define IS_CHANNEL_A(bas) ((uart_cpu_busaddr(bas) & 7) != 0)
46#define IS_CHANNEL_B(bas) ((uart_cpu_busaddr(bas) & 7) == 0)
47
48/* Multiplexed I/O. */
49static __inline void
50uart_setmreg(struct uart_bas *bas, int reg, int val)
51{
52
53 uart_setreg(bas, REG_CTRL, reg);
54 uart_barrier(bas);
55 uart_setreg(bas, REG_CTRL, val);
56}
57
58static __inline uint8_t
59uart_getmreg(struct uart_bas *bas, int reg)
60{
61
62 uart_setreg(bas, REG_CTRL, reg);
63 uart_barrier(bas);
64 return (uart_getreg(bas, REG_CTRL));
65}
66
67static int
68z8530_divisor(int rclk, int baudrate)
69{
70 int act_baud, divisor, error;
71
72 if (baudrate == 0)
73 return (0);
74
75 divisor = (rclk + baudrate) / (baudrate << 1) - 2;
76 if (divisor >= 65536)
77 return (0);
78 act_baud = rclk / 2 / (divisor + 2);
79
80 /* 10 times error in percent: */
81 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
82
83 /* 3.0% maximum error tolerance: */
84 if (error < -30 || error > 30)
85 return (0);
86
87 return (divisor);
88}
89
90static int
91z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
92 int parity, uint8_t *tpcp)
93{
94 int divisor;
95 uint8_t mpm, rpc, tpc;
96
97 rpc = RPC_RXE;
98 mpm = MPM_CM16;
99 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
100
101 if (databits >= 8) {
102 rpc |= RPC_RB8;
103 tpc |= TPC_TB8;
104 } else if (databits == 7) {
105 rpc |= RPC_RB7;
106 tpc |= TPC_TB7;
107 } else if (databits == 6) {
108 rpc |= RPC_RB6;
109 tpc |= TPC_TB6;
110 } else {
111 rpc |= RPC_RB5;
112 tpc |= TPC_TB5;
113 }
114 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
115 switch (parity) {
116 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
117 case UART_PARITY_NONE: break;
118 case UART_PARITY_ODD: mpm |= MPM_PE; break;
119 default: return (EINVAL);
120 }
121
122 /* Set baudrate. */
123 if (baudrate > 0) {
124 divisor = z8530_divisor(bas->rclk, baudrate);
125 if (divisor == 0)
126 return (EINVAL);
127 uart_setmreg(bas, WR_TCL, divisor & 0xff);
128 uart_barrier(bas);
129 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
130 uart_barrier(bas);
131 }
132
133 uart_setmreg(bas, WR_RPC, rpc);
134 uart_barrier(bas);
135 uart_setmreg(bas, WR_MPM, mpm);
136 uart_barrier(bas);
137 uart_setmreg(bas, WR_TPC, tpc);
138 uart_barrier(bas);
139 *tpcp = tpc;
140 return (0);
141}
142
143static int
144z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
145 int parity)
146{
147 uint8_t tpc;
148
149 if (bas->rclk == 0)
150 bas->rclk = DEFAULT_RCLK;
151
152 /* Assume we don't need to perform a full hardware reset. */
153 uart_setmreg(bas, WR_MIC, ((IS_CHANNEL_A(bas)) ? MIC_CRA : MIC_CRB) |
154 MIC_MIE | MIC_NV);
155 uart_barrier(bas);
156 /* Set clock sources and enable BRG. */
157 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
158 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
159 uart_barrier(bas);
160 /* Set data encoding. */
161 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
162 uart_barrier(bas);
163
164 tpc = TPC_DTR | TPC_RTS;
165 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
166 return (int)tpc;
167}
168
169/*
170 * Low-level UART interface.
171 */
172static int z8530_probe(struct uart_bas *bas);
173static void z8530_init(struct uart_bas *bas, int, int, int, int);
174static void z8530_term(struct uart_bas *bas);
175static void z8530_putc(struct uart_bas *bas, int);
176static int z8530_poll(struct uart_bas *bas);
177static int z8530_getc(struct uart_bas *bas);
178
179struct uart_ops uart_z8530_ops = {
180 .probe = z8530_probe,
181 .init = z8530_init,
182 .term = z8530_term,
183 .putc = z8530_putc,
184 .poll = z8530_poll,
185 .getc = z8530_getc,
186};
187
188static int
189z8530_probe(struct uart_bas *bas)
190{
191
192 return (0);
193}
194
195static void
196z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
197 int parity)
198{
199
200 z8530_setup(bas, baudrate, databits, stopbits, parity);
201}
202
203static void
204z8530_term(struct uart_bas *bas)
205{
206}
207
208static void
209z8530_putc(struct uart_bas *bas, int c)
210{
211
212 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
213 ;
214 uart_setreg(bas, REG_DATA, c);
215 uart_barrier(bas);
216}
217
218static int
219z8530_poll(struct uart_bas *bas)
220{
221
222 if (!(uart_getmreg(bas, RR_BES) & BES_RXA))
223 return (-1);
224 return (uart_getreg(bas, REG_DATA));
225}
226
227static int
228z8530_getc(struct uart_bas *bas)
229{
230
231 while (!(uart_getmreg(bas, RR_BES) & BES_RXA))
232 ;
233 return (uart_getreg(bas, REG_DATA));
234}
235
236/*
237 * High-level UART interface.
238 */
239struct z8530_softc {
240 struct uart_softc base;
241 uint8_t tpc;
242};
243
244static int z8530_bus_attach(struct uart_softc *);
245static int z8530_bus_detach(struct uart_softc *);
246static int z8530_bus_flush(struct uart_softc *, int);
247static int z8530_bus_getsig(struct uart_softc *);
248static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
249static int z8530_bus_ipend(struct uart_softc *);
250static int z8530_bus_param(struct uart_softc *, int, int, int, int);
251static int z8530_bus_probe(struct uart_softc *);
252static int z8530_bus_receive(struct uart_softc *);
253static int z8530_bus_setsig(struct uart_softc *, int);
254static int z8530_bus_transmit(struct uart_softc *);
255
256static kobj_method_t z8530_methods[] = {
257 KOBJMETHOD(uart_attach, z8530_bus_attach),
258 KOBJMETHOD(uart_detach, z8530_bus_detach),
259 KOBJMETHOD(uart_flush, z8530_bus_flush),
260 KOBJMETHOD(uart_getsig, z8530_bus_getsig),
261 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
262 KOBJMETHOD(uart_ipend, z8530_bus_ipend),
263 KOBJMETHOD(uart_param, z8530_bus_param),
264 KOBJMETHOD(uart_probe, z8530_bus_probe),
265 KOBJMETHOD(uart_receive, z8530_bus_receive),
266 KOBJMETHOD(uart_setsig, z8530_bus_setsig),
267 KOBJMETHOD(uart_transmit, z8530_bus_transmit),
268 { 0, 0 }
269};
270
271struct uart_class uart_z8530_class = {
272 "z8530 class",
273 z8530_methods,
274 sizeof(struct z8530_softc),
275 .uc_range = 2,
276 .uc_rclk = DEFAULT_RCLK
277};
278
279#define SIGCHG(c, i, s, d) \
280 if (c) { \
281 i |= (i & s) ? s : s | d; \
282 } else { \
283 i = (i & s) ? (i & ~s) | d : i; \
284 }
285
286static int
287z8530_bus_attach(struct uart_softc *sc)
288{
289 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
290 struct uart_bas *bas;
291 struct uart_devinfo *di;
292
293 bas = &sc->sc_bas;
294 if (sc->sc_sysdev != NULL) {
295 di = sc->sc_sysdev;
296 z8530->tpc = TPC_DTR|TPC_RTS;
297 z8530_param(bas, di->baudrate, di->databits, di->stopbits,
298 di->parity, &z8530->tpc);
299 } else {
300 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
301 z8530->tpc &= ~(TPC_DTR|TPC_RTS);
302 }
303
304 sc->sc_rxfifosz = 3;
305 sc->sc_txfifosz = 1;
306
307 (void)z8530_bus_getsig(sc);
308
309 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
310 uart_barrier(bas);
311 uart_setmreg(bas, WR_IDT, IDT_TIE | IDT_RIA);
312 uart_barrier(bas);
313 uart_setmreg(bas, WR_IV, 0);
314 uart_barrier(bas);
315 uart_setmreg(bas, WR_TPC, z8530->tpc);
316 uart_barrier(bas);
317 return (0);
318}
319
320static int
321z8530_bus_detach(struct uart_softc *sc)
322{
323
324 return (0);
325}
326
327static int
328z8530_bus_flush(struct uart_softc *sc, int what)
329{
330
331 return (0);
332}
333
334static int
335z8530_bus_getsig(struct uart_softc *sc)
336{
337 struct uart_bas *bas;
338 uint32_t new, old, sig;
339 uint8_t bes;
340
341 bas = &sc->sc_bas;
342 do {
343 old = sc->sc_hwsig;
344 sig = old;
345 bes = uart_getmreg(bas, RR_BES);
346 SIGCHG(bes & BES_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
347 SIGCHG(bes & BES_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
348 new = sig & ~UART_SIGMASK_DELTA;
349 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
350 return (sig);
351}
352
353static int
354z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
355{
356 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
357 struct uart_bas *bas;
358
359 bas = &sc->sc_bas;
360 switch (request) {
361 case UART_IOCTL_BREAK:
362 if (data)
363 z8530->tpc |= TPC_BRK;
364 else
365 z8530->tpc &= ~TPC_BRK;
366 uart_setmreg(bas, WR_TPC, z8530->tpc);
367 uart_barrier(bas);
368 break;
369 default:
370 return (EINVAL);
371 }
372 return (0);
373}
374
375static int
376z8530_bus_ipend(struct uart_softc *sc)
377{
378 struct uart_bas *bas;
379 int ipend;
380 uint32_t sig;
381 uint8_t bes, src;
382
383 bas = &sc->sc_bas;
384 ipend = 0;
385 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
386 uart_barrier(bas);
387 bes = uart_getmreg(bas, RR_BES);
388 if (bes & BES_BRK) {
389 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
390 ipend |= UART_IPEND_BREAK;
391 }
392 if (bes & BES_TXE) {
393 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
394 ipend |= UART_IPEND_TXIDLE;
395 }
396 if (bes & BES_RXA)
397 ipend |= UART_IPEND_RXREADY;
398 sig = sc->sc_hwsig;
399 SIGCHG(bes & BES_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
400 SIGCHG(bes & BES_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
401 if (sig & UART_SIGMASK_DELTA)
402 ipend |= UART_IPEND_SIGCHG;
403 src = uart_getmreg(bas, RR_SRC);
404 if (src & SRC_OVR) {
405 uart_setreg(bas, REG_CTRL, CR_RSTERR);
406 ipend |= UART_IPEND_OVERRUN;
407 }
408 return (ipend);
409}
410
411static int
412z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
413 int stopbits, int parity)
414{
415 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
416 int error;
417
418 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
419 &z8530->tpc);
420 return (error);
421}
422
423static int
424z8530_bus_probe(struct uart_softc *sc)
425{
426 char buf[80];
427 const char *ch;
428 int error;
429
430 error = z8530_probe(&sc->sc_bas);
431 if (error)
432 return (error);
433
434 /* Assume the address range is naturally aligned. */
435 ch = IS_CHANNEL_A(&sc->sc_bas) ? "A" : "B";
436
437 snprintf(buf, sizeof(buf), "z8530, channel %s", ch);
438 device_set_desc_copy(sc->sc_dev, buf);
439 return (0);
440}
441
442static int
443z8530_bus_receive(struct uart_softc *sc)
444{
445 struct uart_bas *bas;
446 int xc;
447 uint8_t bes, src;
448
449 bas = &sc->sc_bas;
450 bes = uart_getmreg(bas, RR_BES);
451 while ((bes & BES_RXA) && !uart_rx_full(sc)) {
452 src = uart_getmreg(bas, RR_SRC);
453 xc = uart_getreg(bas, REG_DATA);
454 if (src & SRC_FE)
455 xc |= UART_STAT_FRAMERR;
456 if (src & SRC_PE)
457 xc |= UART_STAT_PARERR;
458 uart_rx_put(sc, xc);
459 if (src & (SRC_FE | SRC_PE))
460 uart_setreg(bas, REG_CTRL, CR_RSTERR);
461 bes = uart_getmreg(bas, RR_BES);
462 }
463 return (0);
464}
465
466static int
467z8530_bus_setsig(struct uart_softc *sc, int sig)
468{
469 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
470 struct uart_bas *bas;
471 uint32_t new, old;
472
473 bas = &sc->sc_bas;
474 do {
475 old = sc->sc_hwsig;
476 new = old;
477 if (sig & UART_SIG_DDTR) {
478 SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
479 UART_SIG_DDTR);
480 }
481 if (sig & UART_SIG_DRTS) {
482 SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
483 UART_SIG_DRTS);
484 }
485 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
486
487 if (new & UART_SIG_DTR)
488 z8530->tpc |= TPC_DTR;
489 else
490 z8530->tpc &= ~TPC_DTR;
491 if (new & UART_SIG_RTS)
492 z8530->tpc |= TPC_RTS;
493 else
494 z8530->tpc &= ~TPC_RTS;
495 uart_setmreg(bas, WR_TPC, z8530->tpc);
496 uart_barrier(bas);
497 return (0);
498}
499
500static int
501z8530_bus_transmit(struct uart_softc *sc)
502{
503 struct uart_bas *bas;
504
505 bas = &sc->sc_bas;
506 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
507 ;
508 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
509 uart_barrier(bas);
510 sc->sc_txbusy = 1;
511 return (0);
512}