1/**************************************************************************
2**
3** $Id$
4**
5** Declarations for pci device drivers.
6**
7** FreeBSD
8**
9**-------------------------------------------------------------------------
10**
11** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
12**
13** Redistribution and use in source and binary forms, with or without
14** modification, are permitted provided that the following conditions
15** are met:
16** 1. Redistributions of source code must retain the above copyright
17** notice, this list of conditions and the following disclaimer.
18** 2. Redistributions in binary form must reproduce the above copyright
19** notice, this list of conditions and the following disclaimer in the
20** documentation and/or other materials provided with the distribution.
21** 3. The name of the author may not be used to endorse or promote products
22** derived from this software without specific prior written permission.
23**
24** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34**
35***************************************************************************
36*/
| 1#ifndef PCI_COMPAT
2#define PCI_COMPAT
3#endif
4/*
5 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $Id$
30 *
31 */
|
37
| 32
|
38#ifndef __PCI_VAR_H__
39#define __PCI_VAR_H__ "pl2 95/03/21"
| 33/* some PCI bus constants */
|
40
| 34
|
41/*-----------------------------------------------------------------
42**
43** main pci initialization function.
44** called at boot time from autoconf.c
45**
46**-----------------------------------------------------------------
47*/
| 35#define PCI_BUSMAX 255 /* highest supported bus number */
36#define PCI_SLOTMAX 31 /* highest supported slot number */
37#define PCI_FUNCMAX 7 /* highest supported function number */
38#define PCI_REGMAX 255 /* highest supported config register addr. */
|
48
| 39
|
49void pci_configure (void);
| 40#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
41#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
42#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
|
50
| 43
|
51/*-----------------------------------------------------------------
52**
53** The pci configuration id describes a pci device on the bus.
54** It is constructed from: bus, device & function numbers.
55**
56**-----------------------------------------------------------------
57*/
| 44/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
|
58
| 45
|
59typedef union {
60 u_long cfg1;
61 struct {
62 u_char enable;
63 u_char forward;
64 u_short port;
65 } cfg2;
66 unsigned tag;
67 } pcici_t;
| 46#ifdef PCI_A64
47typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
48#else
49typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
50#endif
|
68
| 51
|
69#define sametag(x,y) ((x).tag == (y).tag)
| 52/* map register information */
|
70
| 53
|
71/*-----------------------------------------------------------------
72**
73** Each pci device has an unique device id.
74** It is used to find a matching driver.
75**
76**-----------------------------------------------------------------
77*/
| 54typedef struct {
55 u_int32_t base;
56 u_int8_t type;
57#define PCI_MAPMEM 0x01 /* memory map */
58#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
59#define PCI_MAPPORT 0x04 /* port map */
60 u_int8_t ln2size;
61 u_int8_t ln2range;
62/* u_int8_t dummy;*/
63} pcimap;
|
78
| 64
|
79typedef u_long pcidi_t;
| 65/* config header information common to all header types */
|
80
| 66
|
81/*-----------------------------------------------------------------
82**
83** The following functions are provided for the device driver
84** to read/write the configuration space.
85**
86** pci_conf_read():
87** Read a long word from the pci configuration space.
88** Requires a tag (from pcitag) and the register
89** number (should be a long word alligned one).
90**
91** pci_conf_write():
92** Writes a long word to the pci configuration space.
93** Requires a tag (from pcitag), the register number
94** (should be a long word alligned one), and a value.
95**
96**-----------------------------------------------------------------
97*/
| 67typedef struct pcicfg {
68 struct pcicfg *parent;
69 struct pcicfg *next;
70 pcimap *map; /* pointer to array of PCI maps */
71 void *hdrspec; /* pointer to header type specific data */
|
98
| 72
|
99u_long pci_conf_read (pcici_t tag, u_long reg );
| 73 u_int16_t subvendor; /* card vendor ID */
74 u_int16_t subdevice; /* card device ID, assigned by card vendor */
75 u_int16_t vendor; /* chip vendor ID */
76 u_int16_t device; /* chip device ID, assigned by chip vendor */
|
100
| 77
|
101void pci_conf_write (pcici_t tag, u_long reg, u_long data);
| 78 u_int16_t cmdreg; /* disable/enable chip and PCI options */
79 u_int16_t statreg; /* supported PCI features and error state */
|
102
| 80
|
103/*-----------------------------------------------------------------
104**
105** The pci driver structure.
106**
107** name: The short device name.
108**
109** probe: Checks if the driver can support a device
110** with this type. The tag may be used to get
111** more info with pci_read_conf(). See below.
112** It returns a string with the devices name,
113** or a NULL pointer, if the driver cannot
114** support this device.
115**
116** attach: Allocate a control structure and prepare
117** it. This function may use the pci mapping
118** functions. See below.
119** (configuration id) or type.
120**
121** count: A pointer to a unit counter.
122** It's used by the pci configurator to
123** allocate unit numbers.
124**
125**-----------------------------------------------------------------
126*/
| 81 u_int8_t class; /* chip PCI class */
82 u_int8_t subclass; /* chip PCI subclass */
83 u_int8_t progif; /* chip PCI programming interface */
84 u_int8_t revid; /* chip revision ID */
|
127
| 85
|
128struct pci_device {
129 char* pd_name;
130 char* (*pd_probe ) (pcici_t tag, pcidi_t type);
131 void (*pd_attach) (pcici_t tag, int unit);
132 u_long *pd_count;
133 int (*pd_shutdown) (int, int);
134};
| 86 u_int8_t hdrtype; /* chip config header type */
87 u_int8_t cachelnsz; /* cache line size in 4byte units */
88 u_int8_t intpin; /* PCI interrupt pin */
89 u_int8_t intline; /* interrupt line (IRQ for PC arch) */
|
135
| 90
|
136/*-----------------------------------------------------------------
137**
138** This table includes pointers to all pci device drivers.
139** It should be generated by the linker.
140**
141**-----------------------------------------------------------------
142*/
| 91 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
92 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
93 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
|
143
| 94
|
144extern struct linker_set pcidevice_set;
| 95 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
96 u_int8_t nummaps; /* actual number of PCI maps used */
|
145
| 97
|
146extern unsigned pci_max_burst_len; /* log2 of safe burst transfer length */
147extern unsigned pci_mechanism;
148extern unsigned pci_maxdevice;
| 98 u_int8_t bus; /* config space bus address */
99 u_int8_t slot; /* config space slot address */
100 u_int8_t func; /* config space function number */
|
149
| 101
|
150/*-----------------------------------------------------------------
151**
152** Map a pci device to physical and virtual memory.
153**
154** Entry selects the register in the pci configuration
155** space, which supplies the size of the region, and
156** receives the physical address.
157**
158** In case of success the function sets the addresses
159** in *va and *pa, and returns 1.
160** In case of errors a message is written,
161** and the function returns 0.
162**
163**-----------------------------------------------------------------
164*/
| 102 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */
103 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */
104} pcicfgregs;
|
165
| 105
|
166int pci_map_mem (pcici_t tag, u_long entry, vm_offset_t *va, vm_offset_t *pa);
| 106/* additional type 1 device config header information (PCI to PCI bridge) */
|
167
| 107
|
168/*-----------------------------------------------------------------
169**
170** Map a pci device to an io port area.
171**
172** Entry selects the register in the pci configuration
173** space, which supplies the size of the region, and
174** receives the port number.
175**
176** In case of success the function sets the port number in pa,
177** and returns 1.
178** In case of errors a message is written,
179** and the function returns 0.
180**
181**-----------------------------------------------------------------
182*/
| 108#ifdef PCI_A64
109#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
110#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
111#else
112#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
113#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
114#endif /* PCI_A64 */
|
183
| 115
|
184int pci_map_port (pcici_t tag, u_long entry, u_short * pa);
| 116#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
117#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
|
185
| 118
|
186/*-----------------------------------------------------------------
187**
188** Map a pci interrupt to an isa irq line, and enable the interrupt.
189**
190** -----------------
191**
192** func is the interrupt handler, arg is the argument
193** to the handler (usually a pointer to a softc).
194**
195** The maskptr argument should be &bio_imask,
196** &net_imask etc. or NULL.
197**
198** If there is any error, a message is written, and
199** the function returns with zero.
200** Else it returns with a value different to zero.
201**
202** -----------------
203**
204** The irq number is read from the configuration space.
205** (Should have been set by the bios).
206**
207** Supports multiple handlers per irq (shared interrupts).
208**
209**-----------------------------------------------------------------
210*/
| 119typedef struct {
120 pci_addr_t pmembase; /* base address of prefetchable memory */
121 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
122 u_int32_t membase; /* base address of memory window */
123 u_int32_t memlimit; /* topmost address of memory window */
124 u_int32_t iobase; /* base address of port window */
125 u_int32_t iolimit; /* topmost address of port window */
126 u_int16_t secstat; /* secondary bus status register */
127 u_int16_t bridgectl; /* bridge control register */
128 u_int8_t seclat; /* CardBus latency timer */
129} pcih1cfgregs;
|
211
| 130
|
| 131/* additional type 2 device config header information (CardBus bridge) */
132
133typedef struct {
134 u_int32_t membase0; /* base address of memory window */
135 u_int32_t memlimit0; /* topmost address of memory window */
136 u_int32_t membase1; /* base address of memory window */
137 u_int32_t memlimit1; /* topmost address of memory window */
138 u_int32_t iobase0; /* base address of port window */
139 u_int32_t iolimit0; /* topmost address of port window */
140 u_int32_t iobase1; /* base address of port window */
141 u_int32_t iolimit1; /* topmost address of port window */
142 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
143 u_int16_t secstat; /* secondary bus status register */
144 u_int16_t bridgectl; /* bridge control register */
145 u_int8_t seclat; /* CardBus latency timer */
146} pcih2cfgregs;
147
148/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */
149
150typedef struct pciattach {
151 int unit;
152 int pcibushigh;
153 struct pciattach *next;
154} pciattach;
155
156/* externally visible functions */
157
158int pci_probe (pciattach *attach);
159void pci_drvattach(pcicfgregs *cfg);
160
161/* low level PCI config register functions provided by pcibus.c */
162
163int pci_cfgopen (void);
164int pci_cfgread (pcicfgregs *cfg, int reg, int bytes);
165void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
166
167/* for compatibility to FreeBSD-2.2 version of PCI code */
168
169#ifdef PCI_COMPAT
170
171typedef pcicfgregs *pcici_t;
172typedef unsigned pcidi_t;
|
212typedef void pci_inthand_t(void *arg);
213
| 173typedef void pci_inthand_t(void *arg);
174
|
214struct pci_int_desc {
215 struct pci_int_desc * pcid_next;
216 pcici_t pcid_tag;
217 pci_inthand_t *pcid_handler;
218 void* pcid_argument;
219 unsigned * pcid_maskptr;
220 unsigned pcid_tally;
221 unsigned pcid_mask;
| 175#define pci_max_burst_len (3)
176
177/* just copied from old PCI code for now ... */
178
179extern struct linker_set pcidevice_set;
180extern int pci_mechanism;
181
182struct pci_device {
183 char* pd_name;
184 char* (*pd_probe ) (pcici_t tag, pcidi_t type);
185 void (*pd_attach) (pcici_t tag, int unit);
186 u_long *pd_count;
187 int (*pd_shutdown) (int, int);
|
222};
223
| 188};
189
|
224int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg,
225 unsigned *maskptr);
| 190struct pci_lkm {
191 struct pci_device *dvp;
192 struct pci_lkm *next;
193};
|
226
| 194
|
| 195u_long pci_conf_read (pcici_t tag, u_long reg);
196void pci_conf_write (pcici_t tag, u_long reg, u_long data);
197int pci_map_port (pcici_t tag, u_long reg, u_short* pa);
198int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
199int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr);
|
227int pci_unmap_int (pcici_t tag);
| 200int pci_unmap_int (pcici_t tag);
|
| 201int pci_register_lkm (struct pci_device *dvp, int if_revision);
|
228
| 202
|
229#endif
| 203#endif /* PCI_COMPAT */
|
| |