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cxgb_xgmac.c (176472) cxgb_xgmac.c (180583)
1
2/**************************************************************************
3
4Copyright (c) 2007, Chelsio Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:

--- 15 unchanged lines hidden (view full) ---

24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29***************************************************************************/
30
31#include <sys/cdefs.h>
1
2/**************************************************************************
3
4Copyright (c) 2007, Chelsio Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:

--- 15 unchanged lines hidden (view full) ---

24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29***************************************************************************/
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_xgmac.c 176472 2008-02-23 01:06:17Z kmacy $");
32__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_xgmac.c 180583 2008-07-18 06:12:31Z kmacy $");
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
40#undef msleep
41#define msleep t3_os_sleep
42
43/*
44 * # of exact address filters. The first one is used for the station address,
45 * the rest are available for multicast addresses.
46 */
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
40#undef msleep
41#define msleep t3_os_sleep
42
43/*
44 * # of exact address filters. The first one is used for the station address,
45 * the rest are available for multicast addresses.
46 */
47#define EXACT_ADDR_FILTERS 8
48
49static inline int macidx(const struct cmac *mac)
50{
51 return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
52}
53
54static void xaui_serdes_reset(struct cmac *mac)
55{

--- 98 unchanged lines hidden (view full) ---

154 t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE |
155 F_ENNON802_3PREAMBLE);
156 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft,
157 V_TXFIFOTHRESH(M_TXFIFOTHRESH),
158 V_TXFIFOTHRESH(64));
159 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
160 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
161 }
47
48static inline int macidx(const struct cmac *mac)
49{
50 return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
51}
52
53static void xaui_serdes_reset(struct cmac *mac)
54{

--- 98 unchanged lines hidden (view full) ---

153 t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE |
154 F_ENNON802_3PREAMBLE);
155 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft,
156 V_TXFIFOTHRESH(M_TXFIFOTHRESH),
157 V_TXFIFOTHRESH(64));
158 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
159 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
160 }
161
162 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
163 V_RXMAXFRAMERSIZE(M_RXMAXFRAMERSIZE),
164 V_RXMAXFRAMERSIZE(MAX_FRAME_SIZE) | F_RXENFRAMER);
162 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
163 V_RXMAXFRAMERSIZE(M_RXMAXFRAMERSIZE),
164 V_RXMAXFRAMERSIZE(MAX_FRAME_SIZE) | F_RXENFRAMER);
165
165 val = F_MAC_RESET_ | F_XGMAC_STOP_EN;
166 val = F_MAC_RESET_ | F_XGMAC_STOP_EN;
166 if (is_10G(adap) || mac->multiport)
167 if (!mac->multiport)
168 val |= F_XG2G_RESET_;
169 if (uses_xaui(adap))
167 val |= F_PCS_RESET_;
170 val |= F_PCS_RESET_;
168 else if (uses_xaui(adap))
169 val |= F_PCS_RESET_ | F_XG2G_RESET_;
170 else
171 else
171 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
172 val |= F_RGMII_RESET_;
172 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
173 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
174 if ((val & F_PCS_RESET_) && adap->params.rev) {
175 msleep(1);
176 t3b_pcs_reset(mac);
177 }
178
179 memset(&mac->stats, 0, sizeof(mac->stats));
180 return 0;
181}
182
183static int t3b2_mac_reset(struct cmac *mac)
184{
185 u32 val;
186 adapter_t *adap = mac->adapter;
187 unsigned int oft = mac->offset;
188
189
190 /* Stop egress traffic to xgm*/
173 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
174 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
175 if ((val & F_PCS_RESET_) && adap->params.rev) {
176 msleep(1);
177 t3b_pcs_reset(mac);
178 }
179
180 memset(&mac->stats, 0, sizeof(mac->stats));
181 return 0;
182}
183
184static int t3b2_mac_reset(struct cmac *mac)
185{
186 u32 val;
187 adapter_t *adap = mac->adapter;
188 unsigned int oft = mac->offset;
189
190
191 /* Stop egress traffic to xgm*/
191 if (!macidx(mac))
192 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
192 if (!macidx(mac))
193 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
193 else
194 else
194 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
195 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
195
196 /* PCS in reset */
197 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
198 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
199
200 msleep(10);
201
202 /* Check for xgm Rx fifo empty */

--- 15 unchanged lines hidden (view full) ---

218 else
219 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
220 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
221 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
222 if ((val & F_PCS_RESET_) && adap->params.rev) {
223 msleep(1);
224 t3b_pcs_reset(mac);
225 }
196
197 /* PCS in reset */
198 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
199 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
200
201 msleep(10);
202
203 /* Check for xgm Rx fifo empty */

--- 15 unchanged lines hidden (view full) ---

219 else
220 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
221 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
222 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
223 if ((val & F_PCS_RESET_) && adap->params.rev) {
224 msleep(1);
225 t3b_pcs_reset(mac);
226 }
226 t3_write_reg(adap, A_XGM_RX_CFG + oft,
227 t3_write_reg(adap, A_XGM_RX_CFG + oft,
227 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
228 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST );
229
230 /*Resume egress traffic to xgm*/
228 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
229 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST );
230
231 /*Resume egress traffic to xgm*/
231 if (!macidx(mac))
232 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
232 if (!macidx(mac))
233 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
233 else
234 else
234 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
235 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
235
236 return 0;
237}
238
239/*
240 * Set the exact match register 'idx' to recognize the given Ethernet address.
241 */
242static void set_addr_filter(struct cmac *mac, int idx, const u8 *addr)

--- 31 unchanged lines hidden (view full) ---

274/**
275 * t3_mac_set_num_ucast - set the number of unicast addresses needed
276 * @mac: the MAC handle
277 * @n: number of unicast addresses needed
278 *
279 * Specify the number of exact address filters that should be reserved for
280 * unicast addresses. Caller should reload the unicast and multicast
281 * addresses after calling this.
236
237 return 0;
238}
239
240/*
241 * Set the exact match register 'idx' to recognize the given Ethernet address.
242 */
243static void set_addr_filter(struct cmac *mac, int idx, const u8 *addr)

--- 31 unchanged lines hidden (view full) ---

275/**
276 * t3_mac_set_num_ucast - set the number of unicast addresses needed
277 * @mac: the MAC handle
278 * @n: number of unicast addresses needed
279 *
280 * Specify the number of exact address filters that should be reserved for
281 * unicast addresses. Caller should reload the unicast and multicast
282 * addresses after calling this.
283 *
284 * Generally, this is 1 with the first one used for the station address,
285 * and the rest are available for multicast addresses.
282 */
283int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n)
284{
285 if (n > EXACT_ADDR_FILTERS)
286 return -EINVAL;
287 mac->nucast = n;
288 return 0;
289}

--- 90 unchanged lines hidden (view full) ---

380
381/**
382 * t3_mac_set_mtu - set the MAC MTU
383 * @mac: the MAC to configure
384 * @mtu: the MTU
385 *
386 * Sets the MAC MTU and adjusts the FIFO PAUSE watermarks accordingly.
387 */
286 */
287int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n)
288{
289 if (n > EXACT_ADDR_FILTERS)
290 return -EINVAL;
291 mac->nucast = n;
292 return 0;
293}

--- 90 unchanged lines hidden (view full) ---

384
385/**
386 * t3_mac_set_mtu - set the MAC MTU
387 * @mac: the MAC to configure
388 * @mtu: the MTU
389 *
390 * Sets the MAC MTU and adjusts the FIFO PAUSE watermarks accordingly.
391 */
388int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
392int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
389{
390 int hwm, lwm, divisor;
391 int ipg;
392 unsigned int thres, v, reg;
393 adapter_t *adap = mac->adapter;
394
395 /*
396 * MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max

--- 11 unchanged lines hidden (view full) ---

408 (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
409 disable_exact_filters(mac);
410 v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
411 t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
412 F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
413
414 reg = adap->params.rev == T3_REV_B2 ?
415 A_XGM_RX_MAX_PKT_SIZE_ERR_CNT : A_XGM_RXFIFO_CFG;
393{
394 int hwm, lwm, divisor;
395 int ipg;
396 unsigned int thres, v, reg;
397 adapter_t *adap = mac->adapter;
398
399 /*
400 * MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max

--- 11 unchanged lines hidden (view full) ---

412 (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
413 disable_exact_filters(mac);
414 v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
415 t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
416 F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
417
418 reg = adap->params.rev == T3_REV_B2 ?
419 A_XGM_RX_MAX_PKT_SIZE_ERR_CNT : A_XGM_RXFIFO_CFG;
416
420
417 /* drain RX FIFO */
418 if (t3_wait_op_done(adap, reg + mac->offset,
419 F_RXFIFO_EMPTY, 1, 20, 5)) {
420 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
421 enable_exact_filters(mac);
422 return -EIO;
423 }
424 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
425 V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
426 V_RXMAXPKTSIZE(mtu));
427 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
428 enable_exact_filters(mac);
429 } else
430 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
421 /* drain RX FIFO */
422 if (t3_wait_op_done(adap, reg + mac->offset,
423 F_RXFIFO_EMPTY, 1, 20, 5)) {
424 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
425 enable_exact_filters(mac);
426 return -EIO;
427 }
428 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
429 V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
430 V_RXMAXPKTSIZE(mtu));
431 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
432 enable_exact_filters(mac);
433 } else
434 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
431 V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
432 V_RXMAXPKTSIZE(mtu));
433
435 V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
436 V_RXMAXPKTSIZE(mtu));
434 /*
435 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
436 * HWM only if flow-control is enabled.
437 */
438 hwm = rx_fifo_hwm(mtu);
439 lwm = min(3 * (int) mtu, MAC_RXFIFO_SIZE /4);
440 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
441 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);

--- 15 unchanged lines hidden (view full) ---

457 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
458 V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
459 V_TXFIFOTHRESH(thres) | V_TXIPG(ipg));
460
461 /* Assuming a minimum drain rate of 2.5Gbps...
462 */
463 if (adap->params.rev > 0) {
464 divisor = (adap->params.rev == T3_REV_C) ? 64 : 8;
437 /*
438 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
439 * HWM only if flow-control is enabled.
440 */
441 hwm = rx_fifo_hwm(mtu);
442 lwm = min(3 * (int) mtu, MAC_RXFIFO_SIZE /4);
443 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
444 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);

--- 15 unchanged lines hidden (view full) ---

460 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
461 V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
462 V_TXFIFOTHRESH(thres) | V_TXIPG(ipg));
463
464 /* Assuming a minimum drain rate of 2.5Gbps...
465 */
466 if (adap->params.rev > 0) {
467 divisor = (adap->params.rev == T3_REV_C) ? 64 : 8;
465 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
466 (hwm - lwm) * 4 / divisor);
468 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
469 (hwm - lwm) * 4 / divisor);
467 }
470 }
468 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
471 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
469 MAC_RXFIFO_SIZE * 4 * 8 / 512);
470 return 0;
471}
472
473/**
474 * t3_mac_set_speed_duplex_fc - set MAC speed, duplex and flow control
475 * @mac: the MAC to configure
476 * @speed: the desired speed (10/100/1000/10000)

--- 7 unchanged lines hidden (view full) ---

484int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
485{
486 u32 val;
487 adapter_t *adap = mac->adapter;
488 unsigned int oft = mac->offset;
489
490 if (duplex >= 0 && duplex != DUPLEX_FULL)
491 return -EINVAL;
472 MAC_RXFIFO_SIZE * 4 * 8 / 512);
473 return 0;
474}
475
476/**
477 * t3_mac_set_speed_duplex_fc - set MAC speed, duplex and flow control
478 * @mac: the MAC to configure
479 * @speed: the desired speed (10/100/1000/10000)

--- 7 unchanged lines hidden (view full) ---

487int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
488{
489 u32 val;
490 adapter_t *adap = mac->adapter;
491 unsigned int oft = mac->offset;
492
493 if (duplex >= 0 && duplex != DUPLEX_FULL)
494 return -EINVAL;
492 if (mac->multiport) {
495 if (mac->multiport) {
493 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
494 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
495 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
496 A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
497 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
498
499 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
500 F_TXPAUSEEN);

--- 69 unchanged lines hidden (view full) ---

570 mac->rx_pause = s->rx_pause;
571 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
572 A_XGM_RX_SPI4_SOP_EOP_CNT +
573 oft)));
574 mac->rx_ocnt = s->rx_fifo_ovfl;
575 mac->txen = F_TXEN;
576 mac->toggle_cnt = 0;
577 }
496 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
497 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
498 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
499 A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
500 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
501
502 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
503 F_TXPAUSEEN);

--- 69 unchanged lines hidden (view full) ---

573 mac->rx_pause = s->rx_pause;
574 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
575 A_XGM_RX_SPI4_SOP_EOP_CNT +
576 oft)));
577 mac->rx_ocnt = s->rx_fifo_ovfl;
578 mac->txen = F_TXEN;
579 mac->toggle_cnt = 0;
580 }
578 if (which & MAC_DIRECTION_RX)
581 if (which & MAC_DIRECTION_RX)
579 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
580 return 0;
581}
582
583/**
584 * t3_mac_disable - disable the MAC in the given directions
585 * @mac: the MAC to configure
586 * @which: bitmap indicating which directions to disable

--- 81 unchanged lines hidden (view full) ---

668 mac->toggle_cnt = 0;
669 goto rxcheck;
670 }
671
672rxcheck:
673 if (rx_mcnt != mac->rx_mcnt) {
674 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
675 A_XGM_RX_SPI4_SOP_EOP_CNT +
582 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
583 return 0;
584}
585
586/**
587 * t3_mac_disable - disable the MAC in the given directions
588 * @mac: the MAC to configure
589 * @which: bitmap indicating which directions to disable

--- 81 unchanged lines hidden (view full) ---

671 mac->toggle_cnt = 0;
672 goto rxcheck;
673 }
674
675rxcheck:
676 if (rx_mcnt != mac->rx_mcnt) {
677 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
678 A_XGM_RX_SPI4_SOP_EOP_CNT +
676 mac->offset))) +
679 mac->offset))) +
677 (s->rx_fifo_ovfl - mac->rx_ocnt);
678 mac->rx_ocnt = s->rx_fifo_ovfl;
680 (s->rx_fifo_ovfl - mac->rx_ocnt);
681 mac->rx_ocnt = s->rx_fifo_ovfl;
679 } else
682 } else
680 goto out;
681
682 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0) {
683 if (!mac->multiport)
684 status = 2;
685 goto out;
686 }
683 goto out;
684
685 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0) {
686 if (!mac->multiport)
687 status = 2;
688 goto out;
689 }
687
688out:
690
691out:
689 mac->tx_tcnt = tx_tcnt;
690 mac->tx_xcnt = tx_xcnt;
691 mac->tx_mcnt = s->tx_frames;
692 mac->rx_xcnt = rx_xcnt;
693 mac->rx_mcnt = s->rx_frames;
694 mac->rx_pause = s->rx_pause;
695 if (status == 1) {
696 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);

--- 84 unchanged lines hidden --- 		692 mac->tx_tcnt = tx_tcnt;
693 mac->tx_xcnt = tx_xcnt;
694 mac->tx_mcnt = s->tx_frames;
695 mac->rx_xcnt = rx_xcnt;
696 mac->rx_mcnt = s->rx_frames;
697 mac->rx_pause = s->rx_pause;
698 if (status == 1) {
699 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);

--- 84 unchanged lines hidden ---