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cxgb_xgmac.c (170654) cxgb_xgmac.c (171471)
1
2/**************************************************************************
3
4Copyright (c) 2007, Chelsio Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:

--- 15 unchanged lines hidden (view full) ---

24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29***************************************************************************/
30
31#include <sys/cdefs.h>
1
2/**************************************************************************
3
4Copyright (c) 2007, Chelsio Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:

--- 15 unchanged lines hidden (view full) ---

24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29***************************************************************************/
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_xgmac.c 170654 2007-06-13 05:36:00Z kmacy $");
32__FBSDID("$FreeBSD: head/sys/dev/cxgb/common/cxgb_xgmac.c 171471 2007-07-17 06:50:35Z kmacy $");
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
33
34#ifdef CONFIG_DEFINED
35#include <cxgb_include.h>
36#else
37#include <dev/cxgb/cxgb_include.h>
38#endif
39
40#undef msleep
41#define msleep t3_os_sleep
42
40/*
41 * # of exact address filters. The first one is used for the station address,
42 * the rest are available for multicast addresses.
43 */
44#define EXACT_ADDR_FILTERS 8
45
46static inline int macidx(const struct cmac *mac)
47{

--- 101 unchanged lines hidden (view full) ---

149 val |= F_PCS_RESET_;
150 else if (uses_xaui(adap))
151 val |= F_PCS_RESET_ | F_XG2G_RESET_;
152 else
153 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
154 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
155 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
156 if ((val & F_PCS_RESET_) && adap->params.rev) {
43/*
44 * # of exact address filters. The first one is used for the station address,
45 * the rest are available for multicast addresses.
46 */
47#define EXACT_ADDR_FILTERS 8
48
49static inline int macidx(const struct cmac *mac)
50{

--- 101 unchanged lines hidden (view full) ---

152 val |= F_PCS_RESET_;
153 else if (uses_xaui(adap))
154 val |= F_PCS_RESET_ | F_XG2G_RESET_;
155 else
156 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
157 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
158 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
159 if ((val & F_PCS_RESET_) && adap->params.rev) {
157 t3_os_sleep(1);
160 msleep(1);
158 t3b_pcs_reset(mac);
159 }
160
161 memset(&mac->stats, 0, sizeof(mac->stats));
162 return 0;
163}
164
165static int t3b2_mac_reset(struct cmac *mac)

--- 8 unchanged lines hidden (view full) ---

174 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
175 else
176 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
177
178 /* PCS in reset */
179 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
180 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
181
161 t3b_pcs_reset(mac);
162 }
163
164 memset(&mac->stats, 0, sizeof(mac->stats));
165 return 0;
166}
167
168static int t3b2_mac_reset(struct cmac *mac)

--- 8 unchanged lines hidden (view full) ---

177 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
178 else
179 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
180
181 /* PCS in reset */
182 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
183 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
184
182 t3_os_sleep(10);
185 msleep(10);
183
184 /* Check for xgm Rx fifo empty */
185 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
186 0x80000000, 1, 5, 2)) {
187 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
188 macidx(mac));
189 return -1;
190 }

--- 6 unchanged lines hidden (view full) ---

197 val |= F_PCS_RESET_;
198 else if (uses_xaui(adap))
199 val |= F_PCS_RESET_ | F_XG2G_RESET_;
200 else
201 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
202 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
203 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
204 if ((val & F_PCS_RESET_) && adap->params.rev) {
186
187 /* Check for xgm Rx fifo empty */
188 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
189 0x80000000, 1, 5, 2)) {
190 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
191 macidx(mac));
192 return -1;
193 }

--- 6 unchanged lines hidden (view full) ---

200 val |= F_PCS_RESET_;
201 else if (uses_xaui(adap))
202 val |= F_PCS_RESET_ | F_XG2G_RESET_;
203 else
204 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
205 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
206 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
207 if ((val & F_PCS_RESET_) && adap->params.rev) {
205 t3_os_sleep(1);
208 msleep(1);
206 t3b_pcs_reset(mac);
207 }
208 t3_write_reg(adap, A_XGM_RX_CFG + oft,
209 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
210 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST );
211
212 /*Resume egress traffic to xgm*/
213 if (!macidx(mac))

--- 24 unchanged lines hidden (view full) ---

238{
239 if (mac->multiport)
240 idx = mac->ext_port + idx * mac->adapter->params.nports;
241 if (idx >= mac->nucast)
242 return -EINVAL;
243 set_addr_filter(mac, idx, addr);
244 if (mac->multiport && idx < mac->adapter->params.nports)
245 t3_vsc7323_set_addr(mac->adapter, addr, idx);
209 t3b_pcs_reset(mac);
210 }
211 t3_write_reg(adap, A_XGM_RX_CFG + oft,
212 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
213 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST );
214
215 /*Resume egress traffic to xgm*/
216 if (!macidx(mac))

--- 24 unchanged lines hidden (view full) ---

241{
242 if (mac->multiport)
243 idx = mac->ext_port + idx * mac->adapter->params.nports;
244 if (idx >= mac->nucast)
245 return -EINVAL;
246 set_addr_filter(mac, idx, addr);
247 if (mac->multiport && idx < mac->adapter->params.nports)
248 t3_vsc7323_set_addr(mac->adapter, addr, idx);
246
247 return 0;
248}
249
250/*
251 * Specify the number of exact address filters that should be reserved for
252 * unicast addresses. Caller should reload the unicast and multicast addresses
253 * after calling this.
254 */

--- 165 unchanged lines hidden (view full) ---

420int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
421{
422 u32 val;
423 adapter_t *adap = mac->adapter;
424 unsigned int oft = mac->offset;
425
426 if (duplex >= 0 && duplex != DUPLEX_FULL)
427 return -EINVAL;
249 return 0;
250}
251
252/*
253 * Specify the number of exact address filters that should be reserved for
254 * unicast addresses. Caller should reload the unicast and multicast addresses
255 * after calling this.
256 */

--- 165 unchanged lines hidden (view full) ---

422int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
423{
424 u32 val;
425 adapter_t *adap = mac->adapter;
426 unsigned int oft = mac->offset;
427
428 if (duplex >= 0 && duplex != DUPLEX_FULL)
429 return -EINVAL;
428 if (mac->multiport)
430 if (mac->multiport) {
431 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
432 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
433 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
434 A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
435 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
436
437 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
438 F_TXPAUSEEN);
429 return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port);
439 return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port);
440 }
430 if (speed >= 0) {
431 if (speed == SPEED_10)
432 val = V_PORTSPEED(0);
433 else if (speed == SPEED_100)
434 val = V_PORTSPEED(1);
435 else if (speed == SPEED_1000)
436 val = V_PORTSPEED(2);
437 else if (speed == SPEED_10000)

--- 8 unchanged lines hidden (view full) ---

446 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
447 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
448 if (fc & PAUSE_TX)
449 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
450 A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
451 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
452
453 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
441 if (speed >= 0) {
442 if (speed == SPEED_10)
443 val = V_PORTSPEED(0);
444 else if (speed == SPEED_100)
445 val = V_PORTSPEED(1);
446 else if (speed == SPEED_1000)
447 val = V_PORTSPEED(2);
448 else if (speed == SPEED_10000)

--- 8 unchanged lines hidden (view full) ---

457 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
458 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
459 if (fc & PAUSE_TX)
460 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
461 A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
462 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
463
464 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
454 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
465 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
455 return 0;
456}
457
458int t3_mac_enable(struct cmac *mac, int which)
459{
460 int idx = macidx(mac);
461 adapter_t *adap = mac->adapter;
462 unsigned int oft = mac->offset;
463 struct mac_stats *s = &mac->stats;
464
465 if (mac->multiport)
466 return t3_vsc7323_enable(adap, mac->ext_port, which);
467
468 if (which & MAC_DIRECTION_TX) {
466 return 0;
467}
468
469int t3_mac_enable(struct cmac *mac, int which)
470{
471 int idx = macidx(mac);
472 adapter_t *adap = mac->adapter;
473 unsigned int oft = mac->offset;
474 struct mac_stats *s = &mac->stats;
475
476 if (mac->multiport)
477 return t3_vsc7323_enable(adap, mac->ext_port, which);
478
479 if (which & MAC_DIRECTION_TX) {
469 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
470 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
471 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
472 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
473 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
474
480 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
481 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
482 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
483 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
484
485 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
486
475 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
476 mac->tx_mcnt = s->tx_frames;
477 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
478 A_TP_PIO_DATA)));
479 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
480 A_XGM_TX_SPI4_SOP_EOP_CNT +
481 oft)));
482 mac->rx_mcnt = s->rx_frames;

--- 5 unchanged lines hidden (view full) ---

488 }
489 if (which & MAC_DIRECTION_RX)
490 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
491 return 0;
492}
493
494int t3_mac_disable(struct cmac *mac, int which)
495{
487 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
488 mac->tx_mcnt = s->tx_frames;
489 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
490 A_TP_PIO_DATA)));
491 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
492 A_XGM_TX_SPI4_SOP_EOP_CNT +
493 oft)));
494 mac->rx_mcnt = s->rx_frames;

--- 5 unchanged lines hidden (view full) ---

500 }
501 if (which & MAC_DIRECTION_RX)
502 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
503 return 0;
504}
505
506int t3_mac_disable(struct cmac *mac, int which)
507{
496 int idx = macidx(mac);
497 adapter_t *adap = mac->adapter;
498 int val;
499
500 if (mac->multiport)
501 return t3_vsc7323_disable(adap, mac->ext_port, which);
502
503 if (which & MAC_DIRECTION_TX) {
508 adapter_t *adap = mac->adapter;
509 int val;
510
511 if (mac->multiport)
512 return t3_vsc7323_disable(adap, mac->ext_port, which);
513
514 if (which & MAC_DIRECTION_TX) {
515 val = t3_read_reg(adap, A_MPS_CFG);
504 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
516 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
505 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
506 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
507 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
508 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
509 mac->txen = 0;
510 }
511 if (which & MAC_DIRECTION_RX) {
512 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
513 F_PCS_RESET_, 0);
517 mac->txen = 0;
518 }
519 if (which & MAC_DIRECTION_RX) {
520 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
521 F_PCS_RESET_, 0);
514 t3_os_sleep(100);
522 msleep(100);
515 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
516 val = F_MAC_RESET_;
517 if (is_10G(adap))
518 val |= F_PCS_RESET_;
519 else if (uses_xaui(adap))
520 val |= F_PCS_RESET_ | F_XG2G_RESET_;
521 else
522 val |= F_RGMII_RESET_ | F_XG2G_RESET_;

--- 7 unchanged lines hidden (view full) ---

530 int status;
531 unsigned int tx_tcnt, tx_xcnt;
532 adapter_t *adap = mac->adapter;
533 struct mac_stats *s = &mac->stats;
534 unsigned int tx_mcnt = (unsigned int)s->tx_frames;
535 unsigned int rx_mcnt = (unsigned int)s->rx_frames;
536 unsigned int rx_xcnt;
537
523 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
524 val = F_MAC_RESET_;
525 if (is_10G(adap))
526 val |= F_PCS_RESET_;
527 else if (uses_xaui(adap))
528 val |= F_PCS_RESET_ | F_XG2G_RESET_;
529 else
530 val |= F_RGMII_RESET_ | F_XG2G_RESET_;

--- 7 unchanged lines hidden (view full) ---

538 int status;
539 unsigned int tx_tcnt, tx_xcnt;
540 adapter_t *adap = mac->adapter;
541 struct mac_stats *s = &mac->stats;
542 unsigned int tx_mcnt = (unsigned int)s->tx_frames;
543 unsigned int rx_mcnt = (unsigned int)s->rx_frames;
544 unsigned int rx_xcnt;
545
546 if (mac->multiport) {
547 tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
548 rx_mcnt = t3_read_reg(adap, A_XGM_STAT_RX_FRAMES_LOW);
549 } else {
550 tx_mcnt = (unsigned int)s->tx_frames;
551 rx_mcnt = (unsigned int)s->rx_frames;
552 }
538 status = 0;
539 tx_xcnt = 1; /* By default tx_xcnt is making progress*/
540 tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/
541 rx_xcnt = 1; /* By default rx_xcnt is making progress*/
542 if (tx_mcnt == mac->tx_mcnt) {
543 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
544 A_XGM_TX_SPI4_SOP_EOP_CNT +
545 mac->offset)));

--- 22 unchanged lines hidden (view full) ---

568 goto out;
569 }
570 } else {
571 mac->toggle_cnt = 0;
572 goto rxcheck;
573 }
574
575rxcheck:
553 status = 0;
554 tx_xcnt = 1; /* By default tx_xcnt is making progress*/
555 tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/
556 rx_xcnt = 1; /* By default rx_xcnt is making progress*/
557 if (tx_mcnt == mac->tx_mcnt) {
558 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
559 A_XGM_TX_SPI4_SOP_EOP_CNT +
560 mac->offset)));

--- 22 unchanged lines hidden (view full) ---

583 goto out;
584 }
585 } else {
586 mac->toggle_cnt = 0;
587 goto rxcheck;
588 }
589
590rxcheck:
576 if (rx_mcnt != mac->rx_mcnt)
591 if (rx_mcnt != mac->rx_mcnt) {
577 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
578 A_XGM_RX_SPI4_SOP_EOP_CNT +
592 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
593 A_XGM_RX_SPI4_SOP_EOP_CNT +
579 mac->offset)));
580 else
594 mac->offset))) +
595 (s->rx_fifo_ovfl - mac->rx_ocnt);
596 mac->rx_ocnt = s->rx_fifo_ovfl;
597 } else
581 goto out;
582
583 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0) {
598 goto out;
599
600 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0) {
584 status = 2;
601 if (!mac->multiport)
602 status = 2;
585 goto out;
586 }
587
588out:
589 mac->tx_tcnt = tx_tcnt;
590 mac->tx_xcnt = tx_xcnt;
591 mac->tx_mcnt = s->tx_frames;
592 mac->rx_xcnt = rx_xcnt;

--- 24 unchanged lines hidden (view full) ---

617#define RMON_UPDATE(mac, name, reg) \
618 (mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
619#define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
620 (mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
621 ((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
622
623 u32 v, lo;
624
603 goto out;
604 }
605
606out:
607 mac->tx_tcnt = tx_tcnt;
608 mac->tx_xcnt = tx_xcnt;
609 mac->tx_mcnt = s->tx_frames;
610 mac->rx_xcnt = rx_xcnt;

--- 24 unchanged lines hidden (view full) ---

635#define RMON_UPDATE(mac, name, reg) \
636 (mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
637#define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
638 (mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
639 ((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
640
641 u32 v, lo;
642
643 if (mac->multiport)
644 return t3_vsc7323_update_stats(mac);
645
625 RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
626 RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
627 RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
628 RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
629 RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
630 RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
631 RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
632 RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);

--- 41 unchanged lines hidden --- 		646 RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
647 RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
648 RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
649 RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
650 RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
651 RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
652 RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
653 RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);

--- 41 unchanged lines hidden ---