1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar91xx_chip.c 221160 2011-04-28 11:13:26Z adrian $");
29
30#include <sys/param.h>
31#include <machine/cpuregs.h>
32
33#include <mips/sentry5/s5reg.h>
34
35#include "opt_ddb.h"
36
37#include <sys/param.h>
38#include <sys/conf.h>
39#include <sys/kernel.h>
40#include <sys/systm.h>
41#include <sys/bus.h>
42#include <sys/cons.h>
43#include <sys/kdb.h>
44#include <sys/reboot.h>
45
46#include <vm/vm.h>
47#include <vm/vm_page.h>
48
49#include <net/ethernet.h>
50
51#include <machine/clock.h>
52#include <machine/cpu.h>
53#include <machine/hwfunc.h>
54#include <machine/md_var.h>
55#include <machine/trap.h>
56#include <machine/vmparam.h>
57
58#include <mips/atheros/ar71xxreg.h>
59#include <mips/atheros/ar91xxreg.h>
60
61#include <mips/atheros/ar71xx_cpudef.h>
62#include <mips/atheros/ar91xx_chip.h>
63
64static void
65ar91xx_chip_detect_mem_size(void)
66{
67}
68
69static void
70ar91xx_chip_detect_sys_frequency(void)
71{
72 uint32_t pll;
73 uint32_t freq;
74 uint32_t div;
75
76 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
77
78 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
79 freq = div * AR91XX_BASE_FREQ;
80
81 u_ar71xx_cpu_freq = freq;
82
83 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
84 u_ar71xx_ddr_freq = freq / div;
85
86 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
87 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
88}
89
90static void
91ar91xx_chip_device_stop(uint32_t mask)
92{
93 uint32_t reg;
94
95 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
96 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
97}
98
99static void
100ar91xx_chip_device_start(uint32_t mask)
101{
102 uint32_t reg;
103
104 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
105 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
106}
107
108static int
109ar91xx_chip_device_stopped(uint32_t mask)
110{
111 uint32_t reg;
112
113 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
114 return ((reg & mask) == mask);
115}
116
117static void
118ar91xx_chip_set_pll_ge0(int speed)
119{
120 uint32_t pll;
121
122 switch(speed) {
123 case 10:
124 pll = AR91XX_PLL_VAL_10;
125 break;
126 case 100:
127 pll = AR91XX_PLL_VAL_100;
128 break;
129 case 1000:
130 pll = AR91XX_PLL_VAL_1000;
131 break;
132 default:
133 printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
134 speed);
135 return;
136 }
137 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
138 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, AR91XX_ETH0_PLL_SHIFT);
139}
140
141static void
142ar91xx_chip_set_pll_ge1(int speed)
143{
144 uint32_t pll;
145
146 switch(speed) {
147 case 10:
148 pll = AR91XX_PLL_VAL_10;
149 break;
150 case 100:
151 pll = AR91XX_PLL_VAL_100;
152 break;
153 case 1000:
154 pll = AR91XX_PLL_VAL_1000;
155 break;
156 default:
157 printf("ar91xx_chip_set_pll_ge0: invalid speed %d\n",
158 speed);
159 return;
160 }
161 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
162 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, AR91XX_ETH1_PLL_SHIFT);
163}
164
165static void
166ar91xx_chip_ddr_flush_ge0(void)
167{
168 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
169}
170
171static void
172ar91xx_chip_ddr_flush_ge1(void)
173{
174 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
175}
176
177static void
178ar91xx_chip_ddr_flush_ip2(void)
179{
180 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
181}
182
183
184static uint32_t
185ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
186{
187 return 0;
188}
189
190static void
191ar91xx_chip_init_usb_peripheral(void)
192{
193 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
194 DELAY(100);
195
196 ar71xx_device_start(RST_RESET_USB_HOST);
197 DELAY(100);
198
199 ar71xx_device_start(RST_RESET_USB_PHY);
200 DELAY(100);
201
202 /* Wireless */
203 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
204 DELAY(1000);
205
206 ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
207 DELAY(1000);
208}
209
210struct ar71xx_cpu_def ar91xx_chip_def = {
211 &ar91xx_chip_detect_mem_size,
212 &ar91xx_chip_detect_sys_frequency,
213 &ar91xx_chip_device_stop,
214 &ar91xx_chip_device_start,
215 &ar91xx_chip_device_stopped,
216 &ar91xx_chip_set_pll_ge0,
217 &ar91xx_chip_set_pll_ge1,
218 &ar91xx_chip_ddr_flush_ge0,
219 &ar91xx_chip_ddr_flush_ge1,
220 &ar91xx_chip_get_eth_pll,
221 &ar91xx_chip_ddr_flush_ip2,
222 &ar91xx_chip_init_usb_peripheral,
223};