1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
27 * $FreeBSD: head/sys/dev/jme/if_jmereg.h 183264 2008-09-22 06:17:21Z yongari $
| 27 * $FreeBSD: head/sys/dev/jme/if_jmereg.h 183814 2008-10-13 01:11:28Z yongari $
|
28 */
29
30#ifndef _IF_JMEREG_H
31#define _IF_JMEREG_H
32
33/*
34 * JMicron Inc. PCI vendor ID
35 */
36#define VENDORID_JMICRON 0x197B
37
38/*
39 * JMC250 PCI device ID
40 */
41#define DEVICEID_JMC250 0x0250
42#define DEVICEREVID_JMC250_A0 0x00
43#define DEVICEREVID_JMC250_A2 0x11
44
45/*
46 * JMC260 PCI device ID
47 */
48#define DEVICEID_JMC260 0x0260
49#define DEVICEREVID_JMC260_A0 0x00
50
| 28 */
29
30#ifndef _IF_JMEREG_H
31#define _IF_JMEREG_H
32
33/*
34 * JMicron Inc. PCI vendor ID
35 */
36#define VENDORID_JMICRON 0x197B
37
38/*
39 * JMC250 PCI device ID
40 */
41#define DEVICEID_JMC250 0x0250
42#define DEVICEREVID_JMC250_A0 0x00
43#define DEVICEREVID_JMC250_A2 0x11
44
45/*
46 * JMC260 PCI device ID
47 */
48#define DEVICEID_JMC260 0x0260
49#define DEVICEREVID_JMC260_A0 0x00
50
|
| 51#define DEVICEID_JMC2XX_MASK 0x0FF0
52
|
51/* JMC250 PCI configuration register. */
52#define JME_PCI_BAR0 0x10 /* 16KB memory window. */
53
54#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
55
56#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
57
58#define JME_PCI_BAR3 0x20 /* 64KB memory window. */
59
60#define JME_PCI_EROM 0x30
61
62#define JME_PCI_DBG 0x9C
63
64#define JME_PCI_SPI 0xB0
65
66#define SPI_ENB 0x00000010
67#define SPI_SO_STATUS 0x00000008
68#define SPI_SI_CTRL 0x00000004
69#define SPI_SCK_CTRL 0x00000002
70#define SPI_CS_N_CTRL 0x00000001
71
72#define JME_PCI_PHYCFG0 0xC0
73
74#define JME_PCI_PHYCFG1 0xC4
75
76#define JME_PCI_PHYCFG2 0xC8
77
78#define JME_PCI_PHYCFG3 0xCC
79
80#define JME_PCI_PIPECTL1 0xD0
81
82#define JME_PCI_PIPECTL2 0xD4
83
84/* PCIe link error/status. */
85#define JME_PCI_LES 0xD8
86
87/* propeietary register 0. */
88#define JME_PCI_PE0 0xE0
89#define PE0_SPI_EXIST 0x00200000
90#define PE0_PME_D0 0x00100000
91#define PE0_PME_D3H 0x00080000
92#define PE0_PME_SPI_PAD 0x00040000
93#define PE0_MASK_ASPM 0x00020000
94#define PE0_EEPROM_RW_DIS 0x00008000
95#define PE0_PCI_INTA 0x00001000
96#define PE0_PCI_INTB 0x00002000
97#define PE0_PCI_INTC 0x00003000
98#define PE0_PCI_INTD 0x00004000
99#define PE0_PCI_SVSSID_WR_ENB 0x00000800
100#define PE0_MSIX_SIZE_8 0x00000700
101#define PE0_MSIX_SIZE_7 0x00000600
102#define PE0_MSIX_SIZE_6 0x00000500
103#define PE0_MSIX_SIZE_5 0x00000400
104#define PE0_MSIX_SIZE_4 0x00000300
105#define PE0_MSIX_SIZE_3 0x00000200
106#define PE0_MSIX_SIZE_2 0x00000100
107#define PE0_MSIX_SIZE_1 0x00000000
108#define PE0_MSIX_SIZE_DEF 0x00000700
109#define PE0_MSIX_CAP_DIS 0x00000080
110#define PE0_MSI_PVMC_ENB 0x00000040
111#define PE0_LCAP_EXIT_LAT_MASK 0x00000038
112#define PE0_LCAP_EXIT_LAT_DEF 0x00000038
113#define PE0_PM_AUXC_MASK 0x00000007
114#define PE0_PM_AUXC_DEF 0x00000007
115
116#define JME_PCI_PE1 0xE4
117
118#define JME_PCI_PHYTEST 0xF8
119
120#define JME_PCI_GPR 0xFC
121
122/*
123 * JMC Register Map.
124 * -----------------------------------------------------------------------
125 * Register Size IO space Memory space
126 * -----------------------------------------------------------------------
127 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~
128 * BAR1 + 0x7F BAR0 + 0x7F
129 * -----------------------------------------------------------------------
130 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~
131 * BAR2 + 0x7F BAR0 + 0x47F
132 * -----------------------------------------------------------------------
133 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~
134 * BAR2 + 0x7F BAR0 + 0x87F
135 * -----------------------------------------------------------------------
136 * To simplify register access fuctions and to get better performance
137 * this driver doesn't support IO space access. It could be implemented
138 * as a function which selects appropriate BARs to access requested
139 * register.
140 */
141
142/* Tx control and status. */
143#define JME_TXCSR 0x0000
144#define TXCSR_QWEIGHT_MASK 0x0F000000
145#define TXCSR_QWEIGHT_SHIFT 24
146#define TXCSR_TXQ_SEL_MASK 0x00070000
147#define TXCSR_TXQ_SEL_SHIFT 16
148#define TXCSR_TXQ_START 0x00000001
149#define TXCSR_TXQ_START_SHIFT 8
150#define TXCSR_FIFO_THRESH_4QW 0x00000000
151#define TXCSR_FIFO_THRESH_8QW 0x00000040
152#define TXCSR_FIFO_THRESH_12QW 0x00000080
153#define TXCSR_FIFO_THRESH_16QW 0x000000C0
154#define TXCSR_DMA_SIZE_64 0x00000000
155#define TXCSR_DMA_SIZE_128 0x00000010
156#define TXCSR_DMA_SIZE_256 0x00000020
157#define TXCSR_DMA_SIZE_512 0x00000030
158#define TXCSR_DMA_BURST 0x00000004
159#define TXCSR_TX_SUSPEND 0x00000002
160#define TXCSR_TX_ENB 0x00000001
161#define TXCSR_TXQ0 0
162#define TXCSR_TXQ1 1
163#define TXCSR_TXQ2 2
164#define TXCSR_TXQ3 3
165#define TXCSR_TXQ4 4
166#define TXCSR_TXQ5 5
167#define TXCSR_TXQ6 6
168#define TXCSR_TXQ7 7
169#define TXCSR_TXQ_WEIGHT(x) \
170 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK)
171#define TXCSR_TXQ_WEIGHT_MIN 0
172#define TXCSR_TXQ_WEIGHT_MAX 15
173#define TXCSR_TXQ_N_SEL(x) \
174 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK)
175#define TXCSR_TXQ_N_START(x) \
176 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x)))
177
178/* Tx queue descriptor base address. 16bytes alignment required. */
179#define JME_TXDBA_LO 0x0004
180#define JME_TXDBA_HI 0x0008
181
182/* Tx queue descriptor count. multiple of 16(max = 1024). */
183#define JME_TXQDC 0x000C
184#define TXQDC_MASK 0x0000007F0
185
186/* Tx queue next descriptor address. */
187#define JME_TXNDA 0x0010
188#define TXNDA_ADDR_MASK 0xFFFFFFF0
189#define TXNDA_DESC_EMPTY 0x00000008
190#define TXNDA_DESC_VALID 0x00000004
191#define TXNDA_DESC_WAIT 0x00000002
192#define TXNDA_DESC_FETCH 0x00000001
193
194/* Tx MAC control ans status. */
195#define JME_TXMAC 0x0014
196#define TXMAC_IFG2_MASK 0xC0000000
197#define TXMAC_IFG2_DEFAULT 0x40000000
198#define TXMAC_IFG1_MASK 0x30000000
199#define TXMAC_IFG1_DEFAULT 0x20000000
200#define TXMAC_THRESH_1_PKT 0x00000300
201#define TXMAC_THRESH_1_2_PKT 0x00000200
202#define TXMAC_THRESH_1_4_PKT 0x00000100
203#define TXMAC_THRESH_1_8_PKT 0x00000000
204#define TXMAC_FRAME_BURST 0x00000080
205#define TXMAC_CARRIER_EXT 0x00000040
206#define TXMAC_IFG_ENB 0x00000020
207#define TXMAC_BACKOFF 0x00000010
208#define TXMAC_CARRIER_SENSE 0x00000008
209#define TXMAC_COLL_ENB 0x00000004
210#define TXMAC_CRC_ENB 0x00000002
211#define TXMAC_PAD_ENB 0x00000001
212
213/* Tx pause frame control. */
214#define JME_TXPFC 0x0018
215#define TXPFC_VLAN_TAG_MASK 0xFFFF0000
216#define TXPFC_VLAN_TAG_SHIFT 16
217#define TXPFC_VLAN_ENB 0x00008000
218#define TXPFC_PAUSE_ENB 0x00000001
219
220/* Tx timer/retry at half duplex. */
221#define JME_TXTRHD 0x001C
222#define TXTRHD_RT_PERIOD_ENB 0x80000000
223#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00
224#define TXTRHD_RT_PERIOD_SHIFT 8
225#define TXTRHD_RT_LIMIT_ENB 0x00000080
226#define TXTRHD_RT_LIMIT_MASK 0x0000007F
227#define TXTRHD_RT_LIMIT_SHIFT 0
228#define TXTRHD_RT_PERIOD_DEFAULT 8192
229#define TXTRHD_RT_LIMIT_DEFAULT 8
230
231/* Rx control & status. */
232#define JME_RXCSR 0x0020
233#define RXCSR_FIFO_FTHRESH_16T 0x00000000
234#define RXCSR_FIFO_FTHRESH_32T 0x10000000
235#define RXCSR_FIFO_FTHRESH_64T 0x20000000
236#define RXCSR_FIFO_FTHRESH_128T 0x30000000
237#define RXCSR_FIFO_FTHRESH_MASK 0x30000000
238#define RXCSR_FIFO_THRESH_16QW 0x00000000
239#define RXCSR_FIFO_THRESH_32QW 0x04000000
240#define RXCSR_FIFO_THRESH_64QW 0x08000000
241#define RXCSR_FIFO_THRESH_128QW 0x0C000000
242#define RXCSR_FIFO_THRESH_MASK 0x0C000000
243#define RXCSR_DMA_SIZE_16 0x00000000
244#define RXCSR_DMA_SIZE_32 0x01000000
245#define RXCSR_DMA_SIZE_64 0x02000000
246#define RXCSR_DMA_SIZE_128 0x03000000
247#define RXCSR_RXQ_SEL_MASK 0x00030000
248#define RXCSR_RXQ_SEL_SHIFT 16
249#define RXCSR_DESC_RT_GAP_MASK 0x0000F000
250#define RXCSR_DESC_RT_GAP_SHIFT 12
251#define RXCSR_DESC_RT_GAP_256 0x00000000
252#define RXCSR_DESC_RT_GAP_512 0x00001000
253#define RXCSR_DESC_RT_GAP_1024 0x00002000
254#define RXCSR_DESC_RT_GAP_2048 0x00003000
255#define RXCSR_DESC_RT_GAP_4096 0x00004000
256#define RXCSR_DESC_RT_GAP_8192 0x00005000
257#define RXCSR_DESC_RT_GAP_16384 0x00006000
258#define RXCSR_DESC_RT_GAP_32768 0x00007000
259#define RXCSR_DESC_RT_CNT_MASK 0x00000F00
260#define RXCSR_DESC_RT_CNT_SHIFT 8
261#define RXCSR_PASS_WAKEUP_PKT 0x00000040
262#define RXCSR_PASS_MAGIC_PKT 0x00000020
263#define RXCSR_PASS_RUNT_PKT 0x00000010
264#define RXCSR_PASS_BAD_PKT 0x00000008
265#define RXCSR_RXQ_START 0x00000004
266#define RXCSR_RX_SUSPEND 0x00000002
267#define RXCSR_RX_ENB 0x00000001
268
269#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT)
270#define RXCSR_RXQ0 0
271#define RXCSR_RXQ1 1
272#define RXCSR_RXQ2 2
273#define RXCSR_RXQ3 3
274#define RXCSR_DESC_RT_CNT(x) \
275 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
276#define RXCSR_DESC_RT_CNT_DEFAULT 32
277
278/* Rx queue descriptor base address. 16bytes alignment needed. */
279#define JME_RXDBA_LO 0x0024
280#define JME_RXDBA_HI 0x0028
281
282/* Rx queue descriptor count. multiple of 16(max = 1024). */
283#define JME_RXQDC 0x002C
284#define RXQDC_MASK 0x0000007F0
285
286/* Rx queue next descriptor address. */
287#define JME_RXNDA 0x0030
288#define RXNDA_ADDR_MASK 0xFFFFFFF0
289#define RXNDA_DESC_EMPTY 0x00000008
290#define RXNDA_DESC_VALID 0x00000004
291#define RXNDA_DESC_WAIT 0x00000002
292#define RXNDA_DESC_FETCH 0x00000001
293
294/* Rx MAC control and status. */
295#define JME_RXMAC 0x0034
296#define RXMAC_RSS_UNICAST 0x00000000
297#define RXMAC_RSS_UNI_MULTICAST 0x00010000
298#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000
299#define RXMAC_RSS_ALLFRAME 0x00030000
300#define RXMAC_PROMISC 0x00000800
301#define RXMAC_BROADCAST 0x00000400
302#define RXMAC_MULTICAST 0x00000200
303#define RXMAC_UNICAST 0x00000100
304#define RXMAC_ALLMULTI 0x00000080
305#define RXMAC_MULTICAST_FILTER 0x00000040
306#define RXMAC_COLL_DET_ENB 0x00000020
307#define RXMAC_FC_ENB 0x00000008
308#define RXMAC_VLAN_ENB 0x00000004
309#define RXMAC_PAD_10BYTES 0x00000002
310#define RXMAC_CSUM_ENB 0x00000001
311
312/* Rx unicast MAC address. */
313#define JME_PAR0 0x0038
314#define JME_PAR1 0x003C
315
316/* Rx multicast address hash table. */
317#define JME_MAR0 0x0040
318#define JME_MAR1 0x0044
319
320/* Wakeup frame output data port. */
321#define JME_WFODP 0x0048
322
323/* Wakeup frame output interface. */
324#define JME_WFOI 0x004C
325#define WFOI_MASK_0_31 0x00000000
326#define WFOI_MASK_31_63 0x00000010
327#define WFOI_MASK_64_95 0x00000020
328#define WFOI_MASK_96_127 0x00000030
329#define WFOI_MASK_SEL 0x00000008
330#define WFOI_CRC_SEL 0x00000000
331#define WFOI_WAKEUP_FRAME_MASK 0x00000007
332#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK)
333
334/* Station management interface. */
335#define JME_SMI 0x0050
336#define SMI_DATA_MASK 0xFFFF0000
337#define SMI_DATA_SHIFT 16
338#define SMI_REG_ADDR_MASK 0x0000F800
339#define SMI_REG_ADDR_SHIFT 11
340#define SMI_PHY_ADDR_MASK 0x000007C0
341#define SMI_PHY_ADDR_SHIFT 6
342#define SMI_OP_WRITE 0x00000020
343#define SMI_OP_READ 0x00000000
344#define SMI_OP_EXECUTE 0x00000010
345#define SMI_MDIO 0x00000008
346#define SMI_MDOE 0x00000004
347#define SMI_MDC 0x00000002
348#define SMI_MDEN 0x00000001
349#define SMI_REG_ADDR(x) \
350 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK)
351#define SMI_PHY_ADDR(x) \
352 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK)
353
354/* Global host control. */
355#define JME_GHC 0x0054
356#define GHC_LOOPBACK 0x80000000
357#define GHC_RESET 0x40000000
358#define GHC_FULL_DUPLEX 0x00000040
359#define GHC_SPEED_UNKNOWN 0x00000000
360#define GHC_SPEED_10 0x00000010
361#define GHC_SPEED_100 0x00000020
362#define GHC_SPEED_1000 0x00000030
363#define GHC_SPEED_MASK 0x00000030
364#define GHC_LINK_OFF 0x00000004
365#define GHC_LINK_ON 0x00000002
366#define GHC_LINK_STAT_POLLING 0x00000001
367
368/* Power management control and status. */
369#define JME_PMCS 0x0060
370#define PMCS_WAKEUP_FRAME_7 0x80000000
371#define PMCS_WAKEUP_FRAME_6 0x40000000
372#define PMCS_WAKEUP_FRAME_5 0x20000000
373#define PMCS_WAKEUP_FRAME_4 0x10000000
374#define PMCS_WAKEUP_FRAME_3 0x08000000
375#define PMCS_WAKEUP_FRAME_2 0x04000000
376#define PMCS_WAKEUP_FRAME_1 0x02000000
377#define PMCS_WAKEUP_FRAME_0 0x01000000
378#define PMCS_LINK_FAIL 0x00040000
379#define PMCS_LINK_RISING 0x00020000
380#define PMCS_MAGIC_FRAME 0x00010000
381#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000
382#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000
383#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000
384#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000
385#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800
386#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400
387#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200
388#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100
389#define PMCS_LINK_FAIL_ENB 0x00000004
390#define PMCS_LINK_RISING_ENB 0x00000002
391#define PMCS_MAGIC_FRAME_ENB 0x00000001
392#define PMCS_WOL_ENB_MASK 0x0000FFFF
393
394/* Giga PHY & EEPROM registers. */
395#define JME_PHY_EEPROM_BASE_ADDR 0x0400
396
397#define JME_GIGAR0LO 0x0400
398#define JME_GIGAR0HI 0x0404
399#define JME_GIGARALO 0x0408
400#define JME_GIGARAHI 0x040C
401#define JME_GIGARBLO 0x0410
402#define JME_GIGARBHI 0x0414
403#define JME_GIGARCLO 0x0418
404#define JME_GIGARCHI 0x041C
405#define JME_GIGARDLO 0x0420
406#define JME_GIGARDHI 0x0424
407
408/* BIST status and control. */
409#define JME_GIGACSR 0x0428
410#define GIGACSR_STATUS 0x40000000
411#define GIGACSR_CTRL_MASK 0x30000000
412#define GIGACSR_CTRL_DEFAULT 0x30000000
413#define GIGACSR_TX_CLK_MASK 0x0F000000
414#define GIGACSR_RX_CLK_MASK 0x00F00000
415#define GIGACSR_TX_CLK_INV 0x00080000
416#define GIGACSR_RX_CLK_INV 0x00040000
417#define GIGACSR_PHY_RST 0x00010000
418#define GIGACSR_IRQ_N_O 0x00001000
419#define GIGACSR_BIST_OK 0x00000200
420#define GIGACSR_BIST_DONE 0x00000100
421#define GIGACSR_BIST_LED_ENB 0x00000010
422#define GIGACSR_BIST_MASK 0x00000003
423
424/* PHY Link Status. */
425#define JME_LNKSTS 0x0430
426#define LINKSTS_SPEED_10 0x00000000
427#define LINKSTS_SPEED_100 0x00004000
428#define LINKSTS_SPEED_1000 0x00008000
429#define LINKSTS_FULL_DUPLEX 0x00002000
430#define LINKSTS_PAGE_RCVD 0x00001000
431#define LINKSTS_SPDDPX_RESOLVED 0x00000800
432#define LINKSTS_UP 0x00000400
433#define LINKSTS_ANEG_COMP 0x00000200
434#define LINKSTS_MDI_CROSSOVR 0x00000040
435#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002
436#define LINKSTS_LPAR_PAUSE 0x00000001
437
438/* SMB control and status. */
439#define JME_SMBCSR 0x0440
440#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000
441#define SMBCSR_WR_DATA_NACK 0x00040000
442#define SMBCSR_CMD_NACK 0x00020000
443#define SMBCSR_RELOAD 0x00010000
444#define SMBCSR_CMD_ADDR_MASK 0x0000FF00
445#define SMBCSR_SCL_STAT 0x00000080
446#define SMBCSR_SDA_STAT 0x00000040
447#define SMBCSR_EEPROM_PRESENT 0x00000020
448#define SMBCSR_INIT_LD_DONE 0x00000010
449#define SMBCSR_HW_BUSY_MASK 0x0000000F
450#define SMBCSR_HW_IDLE 0x00000000
451
452/* SMB interface. */
453#define JME_SMBINTF 0x0444
454#define SMBINTF_RD_DATA_MASK 0xFF000000
455#define SMBINTF_RD_DATA_SHIFT 24
456#define SMBINTF_WR_DATA_MASK 0x00FF0000
457#define SMBINTF_WR_DATA_SHIFT 16
458#define SMBINTF_ADDR_MASK 0x0000FF00
459#define SMBINTF_ADDR_SHIFT 8
460#define SMBINTF_RD 0x00000020
461#define SMBINTF_WR 0x00000000
462#define SMBINTF_CMD_TRIGGER 0x00000010
463#define SMBINTF_BUSY 0x00000010
464#define SMBINTF_FAST_MODE 0x00000008
465#define SMBINTF_GPIO_SCL 0x00000004
466#define SMBINTF_GPIO_SDA 0x00000002
467#define SMBINTF_GPIO_ENB 0x00000001
468
469#define JME_EEPROM_SIG0 0x55
470#define JME_EEPROM_SIG1 0xAA
471#define JME_EEPROM_DESC_BYTES 3
472#define JME_EEPROM_DESC_END 0x80
473#define JME_EEPROM_FUNC_MASK 0x70
474#define JME_EEPROM_FUNC_SHIFT 4
475#define JME_EEPROM_PAGE_MASK 0x0F
476#define JME_EEPROM_PAGE_SHIFT 0
477
478#define JME_EEPROM_FUNC0 0
479/* PCI configuration space. */
480#define JME_EEPROM_PAGE_BAR0 0
481/* 128 bytes I/O window. */
482#define JME_EEPROM_PAGE_BAR1 1
483/* 256 bytes I/O window. */
484#define JME_EEPROM_PAGE_BAR2 2
485
486#define JME_EEPROM_END 0xFF
487
488#define JME_EEPROM_MKDESC(f, p) \
489 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \
490 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT))
491
492/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */
493#define JME_EEPINTF 0x0448
494#define EEPINTF_DATA_MASK 0xFFFF0000
495#define EEPINTF_DATA_SHIFT 16
496#define EEPINTF_ADDR_MASK 0x0000FC00
497#define EEPINTF_ADDR_SHIFT 10
498#define EEPRINTF_OP_MASK 0x00000300
499#define EEPINTF_OP_EXECUTE 0x00000080
500#define EEPINTF_DATA_OUT 0x00000008
501#define EEPINTF_DATA_IN 0x00000004
502#define EEPINTF_CLK 0x00000002
503#define EEPINTF_SEL 0x00000001
504
505/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */
506#define JME_EEPCSR 0x044C
507#define EEPCSR_EEPROM_RELOAD 0x00000002
508#define EEPCSR_EEPROM_PRESENT 0x00000001
509
510/* Misc registers. */
511#define JME_MISC_BASE_ADDR 0x800
512
513/* Timer control and status. */
514#define JME_TMCSR 0x0800
515#define TMCSR_SW_INTR 0x80000000
516#define TMCSR_TIMER_INTR 0x10000000
517#define TMCSR_TIMER_ENB 0x01000000
518#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF
519
520/* GPIO control and status. */
521#define JME_GPIO 0x0804
522#define GPIO_4_SPI_IN 0x80000000
523#define GPIO_3_SPI_IN 0x40000000
524#define GPIO_4_SPI_OUT 0x20000000
525#define GPIO_4_SPI_OUT_ENB 0x10000000
526#define GPIO_3_SPI_OUT 0x08000000
527#define GPIO_3_SPI_OUT_ENB 0x04000000
528#define GPIO_3_4_LED 0x00000000
529#define GPIO_3_4_GPIO 0x02000000
530#define GPIO_2_CLKREQN_IN 0x00100000
531#define GPIO_2_CLKREQN_OUT 0x00040000
532#define GPIO_2_CLKREQN_OUT_ENB 0x00020000
533#define GPIO_1_LED42_IN 0x00001000
534#define GPIO_1_LED42_OUT 0x00000400
535#define GPIO_1_LED42_OUT_ENB 0x00000200
536#define GPIO_1_LED42_ENB 0x00000100
537#define GPIO_0_SDA_IN 0x00000010
538#define GPIO_0_SDA_OUT 0x00000004
539#define GPIO_0_SDA_OUT_ENB 0x00000002
540#define GPIO_0_SDA_ENB 0x00000001
541
542/* General purpose register 0. */
543#define JME_GPREG0 0x0808
544#define GPREG0_SH_POST_DW7_DIS 0x80000000
545#define GPREG0_SH_POST_DW6_DIS 0x40000000
546#define GPREG0_SH_POST_DW5_DIS 0x20000000
547#define GPREG0_SH_POST_DW4_DIS 0x10000000
548#define GPREG0_SH_POST_DW3_DIS 0x08000000
549#define GPREG0_SH_POST_DW2_DIS 0x04000000
550#define GPREG0_SH_POST_DW1_DIS 0x02000000
551#define GPREG0_SH_POST_DW0_DIS 0x01000000
552#define GPREG0_DMA_RD_REQ_8 0x00000000
553#define GPREG0_DMA_RD_REQ_6 0x00100000
554#define GPREG0_DMA_RD_REQ_5 0x00200000
555#define GPREG0_DMA_RD_REQ_4 0x00300000
556#define GPREG0_POST_DW0_ENB 0x00040000
557#define GPREG0_PCC_CLR_DIS 0x00020000
558#define GPREG0_FORCE_SCL_OUT 0x00010000
559#define GPREG0_DL_RSTB_DIS 0x00008000
560#define GPREG0_STICKY_RESET 0x00004000
561#define GPREG0_DL_RSTB_CFG_DIS 0x00002000
562#define GPREG0_LINK_CHG_POLL 0x00001000
563#define GPREG0_LINK_CHG_DIRECT 0x00000000
564#define GPREG0_MSI_GEN_SEL 0x00000800
565#define GPREG0_SMB_PAD_PU_DIS 0x00000400
566#define GPREG0_PCC_UNIT_16US 0x00000000
567#define GPREG0_PCC_UNIT_256US 0x00000100
568#define GPREG0_PCC_UNIT_US 0x00000200
569#define GPREG0_PCC_UNIT_MS 0x00000300
570#define GPREG0_PCC_UNIT_MASK 0x00000300
571#define GPREG0_INTR_EVENT_ENB 0x00000080
572#define GPREG0_PME_ENB 0x00000020
573#define GPREG0_PHY_ADDR_MASK 0x0000001F
574#define GPREG0_PHY_ADDR_SHIFT 0
575#define GPREG0_PHY_ADDR 1
576
577/* General purpose register 1. */
578#define JME_GPREG1 0x080C
579#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */
580#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */
581#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */
582#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */
583#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */
584#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */
585#define GPREG1_INTDLY_MASK 0x00000007
586
587/* MSIX entry number of interrupt source. */
588#define JME_MSINUM_BASE 0x0810
589#define JME_MSINUM_END 0x081F
590#define MSINUM_MASK 0x7FFFFFFF
591#define MSINUM_ENTRY_MASK 7
592#define MSINUM_REG_INDEX(x) ((x) / 8)
593#define MSINUM_INTR_SOURCE(x, y) \
594 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4))
595#define MSINUM_NUM_INTR_SOURCE 32
596
597/* Interrupt event status. */
598#define JME_INTR_STATUS 0x0820
599#define INTR_SW 0x80000000
600#define INTR_TIMER 0x40000000
601#define INTR_LINKCHG 0x20000000
602#define INTR_PAUSE 0x10000000
603#define INTR_MAGIC_PKT 0x08000000
604#define INTR_WAKEUP_PKT 0x04000000
605#define INTR_RXQ0_COAL_TO 0x02000000
606#define INTR_RXQ1_COAL_TO 0x01000000
607#define INTR_RXQ2_COAL_TO 0x00800000
608#define INTR_RXQ3_COAL_TO 0x00400000
609#define INTR_TXQ_COAL_TO 0x00200000
610#define INTR_RXQ0_COAL 0x00100000
611#define INTR_RXQ1_COAL 0x00080000
612#define INTR_RXQ2_COAL 0x00040000
613#define INTR_RXQ3_COAL 0x00020000
614#define INTR_TXQ_COAL 0x00010000
615#define INTR_RXQ3_DESC_EMPTY 0x00008000
616#define INTR_RXQ2_DESC_EMPTY 0x00004000
617#define INTR_RXQ1_DESC_EMPTY 0x00002000
618#define INTR_RXQ0_DESC_EMPTY 0x00001000
619#define INTR_RXQ3_COMP 0x00000800
620#define INTR_RXQ2_COMP 0x00000400
621#define INTR_RXQ1_COMP 0x00000200
622#define INTR_RXQ0_COMP 0x00000100
623#define INTR_TXQ7_COMP 0x00000080
624#define INTR_TXQ6_COMP 0x00000040
625#define INTR_TXQ5_COMP 0x00000020
626#define INTR_TXQ4_COMP 0x00000010
627#define INTR_TXQ3_COMP 0x00000008
628#define INTR_TXQ2_COMP 0x00000004
629#define INTR_TXQ1_COMP 0x00000002
630#define INTR_TXQ0_COMP 0x00000001
631
632#define INTR_RXQ_COAL_TO \
633 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \
634 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO)
635
636#define INTR_RXQ_COAL \
637 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \
638 INTR_RXQ3_COAL)
639
640#define INTR_RXQ_COMP \
641 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
642 INTR_RXQ3_COMP)
643
644#define INTR_RXQ_DESC_EMPTY \
645 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \
646 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY)
647
648#define INTR_RXQ_COMP \
649 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
650 INTR_RXQ3_COMP)
651
652#define INTR_TXQ_COMP \
653 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \
654 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \
655 INTR_TXQ6_COMP | INTR_TXQ7_COMP)
656
657#define JME_INTRS \
658 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \
659 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY)
660
661#define N_INTR_SW 31
662#define N_INTR_TIMER 30
663#define N_INTR_LINKCHG 29
664#define N_INTR_PAUSE 28
665#define N_INTR_MAGIC_PKT 27
666#define N_INTR_WAKEUP_PKT 26
667#define N_INTR_RXQ0_COAL_TO 25
668#define N_INTR_RXQ1_COAL_TO 24
669#define N_INTR_RXQ2_COAL_TO 23
670#define N_INTR_RXQ3_COAL_TO 22
671#define N_INTR_TXQ_COAL_TO 21
672#define N_INTR_RXQ0_COAL 20
673#define N_INTR_RXQ1_COAL 19
674#define N_INTR_RXQ2_COAL 18
675#define N_INTR_RXQ3_COAL 17
676#define N_INTR_TXQ_COAL 16
677#define N_INTR_RXQ3_DESC_EMPTY 15
678#define N_INTR_RXQ2_DESC_EMPTY 14
679#define N_INTR_RXQ1_DESC_EMPTY 13
680#define N_INTR_RXQ0_DESC_EMPTY 12
681#define N_INTR_RXQ3_COMP 11
682#define N_INTR_RXQ2_COMP 10
683#define N_INTR_RXQ1_COMP 9
684#define N_INTR_RXQ0_COMP 8
685#define N_INTR_TXQ7_COMP 7
686#define N_INTR_TXQ6_COMP 6
687#define N_INTR_TXQ5_COMP 5
688#define N_INTR_TXQ4_COMP 4
689#define N_INTR_TXQ3_COMP 3
690#define N_INTR_TXQ2_COMP 2
691#define N_INTR_TXQ1_COMP 1
692#define N_INTR_TXQ0_COMP 0
693
694/* Interrupt request status. */
695#define JME_INTR_REQ_STATUS 0x0824
696
697/* Interrupt enable - setting port. */
698#define JME_INTR_MASK_SET 0x0828
699
700/* Interrupt enable - clearing port. */
701#define JME_INTR_MASK_CLR 0x082C
702
703/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */
704#define JME_PCCRX0 0x0830
705#define JME_PCCRX1 0x0834
706#define JME_PCCRX2 0x0838
707#define JME_PCCRX3 0x083C
708#define PCCRX_COAL_TO_MASK 0xFFFF0000
709#define PCCRX_COAL_TO_SHIFT 16
710#define PCCRX_COAL_PKT_MASK 0x0000FF00
711#define PCCRX_COAL_PKT_SHIFT 8
712
713#define PCCRX_COAL_TO_MIN 1
714#define PCCRX_COAL_TO_DEFAULT 100
715#define PCCRX_COAL_TO_MAX 65535
716
717#define PCCRX_COAL_PKT_MIN 1
718#define PCCRX_COAL_PKT_DEFAULT 2
719#define PCCRX_COAL_PKT_MAX 255
720
721/* Packet completion coalescing control of Tx queue. */
722#define JME_PCCTX 0x0840
723#define PCCTX_COAL_TO_MASK 0xFFFF0000
724#define PCCTX_COAL_TO_SHIFT 16
725#define PCCTX_COAL_PKT_MASK 0x0000FF00
726#define PCCTX_COAL_PKT_SHIFT 8
727#define PCCTX_COAL_TXQ7 0x00000080
728#define PCCTX_COAL_TXQ6 0x00000040
729#define PCCTX_COAL_TXQ5 0x00000020
730#define PCCTX_COAL_TXQ4 0x00000010
731#define PCCTX_COAL_TXQ3 0x00000008
732#define PCCTX_COAL_TXQ2 0x00000004
733#define PCCTX_COAL_TXQ1 0x00000002
734#define PCCTX_COAL_TXQ0 0x00000001
735
736#define PCCTX_COAL_TO_MIN 1
737#define PCCTX_COAL_TO_DEFAULT 100
738#define PCCTX_COAL_TO_MAX 65535
739
740#define PCCTX_COAL_PKT_MIN 1
741#define PCCTX_COAL_PKT_DEFAULT 8
742#define PCCTX_COAL_PKT_MAX 255
743
744/* Chip mode and FPGA version. */
745#define JME_CHIPMODE 0x0844
746#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000
747#define CHIPMODE_FPGA_REV_SHIFT 16
748#define CHIPMODE_NOT_FPGA 0
749#define CHIPMODE_REV_MASK 0x0000FF00
750#define CHIPMODE_REV_SHIFT 8
751#define CHIPMODE_MODE_48P 0x0000000C
752#define CHIPMODE_MODE_64P 0x00000004
753#define CHIPMODE_MODE_128P_MAC 0x00000003
754#define CHIPMODE_MODE_128P_DBG 0x00000002
755#define CHIPMODE_MODE_128P_PHY 0x00000000
756
757/* Shadow status base address high/low. */
758#define JME_SHBASE_ADDR_HI 0x0848
759#define JME_SHBASE_ADDR_LO 0x084C
760#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0
761#define SHBASE_POST_FORCE 0x00000002
762#define SHBASE_POST_ENB 0x00000001
763
764/* Timer 1 and 2. */
765#define JME_TIMER1 0x0870
766#define JME_TIMER2 0x0874
767#define TIMER_ENB 0x01000000
768#define TIMER_CNT_MASK 0x00FFFFFF
769#define TIMER_CNT_SHIFT 0
770#define TIMER_UNIT 1024 /* 1024us */
771
772/* Aggresive power mode control. */
773#define JME_APMC 0x087C
774#define APMC_PCIE_SDOWN_STAT 0x80000000
775#define APMC_PCIE_SDOWN_ENB 0x40000000
776#define APMC_PSEUDO_HOT_PLUG 0x20000000
777#define APMC_EXT_PLUGIN_ENB 0x04000000
778#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000
779#define APMC_DIS_SRAM 0x00000004
780#define APMC_DIS_CLKPM 0x00000002
781#define APMC_DIS_CLKTX 0x00000001
782
783/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */
784#define JME_PCCSRX_BASE 0x0880
785#define JME_PCCSRX_END 0x088F
786#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4))
787#define PCCSRX_TO_MASK 0xFFFF0000
788#define PCCSRX_TO_SHIFT 16
789#define PCCSRX_PKT_CNT_MASK 0x0000FF00
790#define PCCSRX_PKT_CNT_SHIFT 8
791
792/* Packet completion coalesing status of Tx queue. */
793#define JME_PCCSTX 0x0890
794#define PCCSTX_TO_MASK 0xFFFF0000
795#define PCCSTX_TO_SHIFT 16
796#define PCCSTX_PKT_CNT_MASK 0x0000FF00
797#define PCCSTX_PKT_CNT_SHIFT 8
798
799/* Tx queues empty indicator. */
800#define JME_TXQEMPTY 0x0894
801#define TXQEMPTY_TXQ7 0x00000080
802#define TXQEMPTY_TXQ6 0x00000040
803#define TXQEMPTY_TXQ5 0x00000020
804#define TXQEMPTY_TXQ4 0x00000010
805#define TXQEMPTY_TXQ3 0x00000008
806#define TXQEMPTY_TXQ2 0x00000004
807#define TXQEMPTY_TXQ1 0x00000002
808#define TXQEMPTY_TXQ0 0x00000001
809#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y)))
810
811/* RSS control registers. */
812#define JME_RSS_BASE 0x0C00
813
814#define JME_RSSC 0x0C00
815#define RSSC_HASH_LEN_MASK 0x0000E000
816#define RSSC_HASH_64_ENTRY 0x0000A000
817#define RSSC_HASH_128_ENTRY 0x0000E000
818#define RSSC_HASH_NONE 0x00001000
819#define RSSC_HASH_IPV6 0x00000800
820#define RSSC_HASH_IPV4 0x00000400
821#define RSSC_HASH_IPV6_TCP 0x00000200
822#define RSSC_HASH_IPV4_TCP 0x00000100
823#define RSSC_NCPU_MASK 0x000000F8
824#define RSSC_NCPU_SHIFT 3
825#define RSSC_DIS_RSS 0x00000000
826#define RSSC_2RXQ_ENB 0x00000001
827#define RSSS_4RXQ_ENB 0x00000002
828
829/* CPU vector. */
830#define JME_RSSCPU 0x0C04
831#define RSSCPU_N_SEL(x) ((1 << (x))
832
833/* RSS Hash value. */
834#define JME_RSSHASH 0x0C10
835
836#define JME_RSSHASH_STAT 0x0C14
837
838#define JME_RSS_RDATA0 0x0C18
839
840#define JME_RSS_RDATA1 0x0C1C
841
842/* RSS secret key. */
843#define JME_RSSKEY_BASE 0x0C40
844#define JME_RSSKEY_LAST 0x0C64
845#define JME_RSSKEY_END 0x0C67
846#define HASHKEY_NBYTES 40
847#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4)))
848#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4)))
849
850/* RSS indirection table entries. */
851#define JME_RSSTBL_BASE 0x0C80
852#define JME_RSSTBL_END 0x0CFF
853#define RSSTBL_NENTRY 128
854#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4))
855#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4)))
856
857/* MSI-X table. */
858#define JME_MSIX_BASE_ADDR 0x2000
859
860#define JME_MSIX_BASE 0x2000
861#define JME_MSIX_END 0x207F
862#define JME_MSIX_NENTRY 8
863#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10))
864#define MSIX_ADDR_HI_OFF 0x00
865#define MSIX_ADDR_LO_OFF 0x04
866#define MSIX_ADDR_LO_MASK 0xFFFFFFFC
867#define MSIX_DATA_OFF 0x08
868#define MSIX_VECTOR_OFF 0x0C
869#define MSIX_VECTOR_RSVD 0x80000000
870#define MSIX_VECTOR_DIS 0x00000001
871
872/* MSI-X PBA. */
873#define JME_MSIX_PBA_BASE_ADDR 0x3000
874
875#define JME_MSIX_PBA 0x3000
876#define MSIX_PBA_RSVD_MASK 0xFFFFFF00
877#define MSIX_PBA_RSVD_SHIFT 8
878#define MSIX_PBA_PEND_MASK 0x000000FF
879#define MSIX_PBA_PEND_SHIFT 0
880#define MSIX_PBA_PEND_ENTRY7 0x00000080
881#define MSIX_PBA_PEND_ENTRY6 0x00000040
882#define MSIX_PBA_PEND_ENTRY5 0x00000020
883#define MSIX_PBA_PEND_ENTRY4 0x00000010
884#define MSIX_PBA_PEND_ENTRY3 0x00000008
885#define MSIX_PBA_PEND_ENTRY2 0x00000004
886#define MSIX_PBA_PEND_ENTRY1 0x00000002
887#define MSIX_PBA_PEND_ENTRY0 0x00000001
888
889#define JME_PHY_OUI 0x001B8C
890#define JME_PHY_MODEL 0x21
891#define JME_PHY_REV 0x01
892#define JME_PHY_ADDR 1
893
894/* JMC250 shadow status block. */
895struct jme_ssb {
896 uint32_t dw0;
897 uint32_t dw1;
898 uint32_t dw2;
899 uint32_t dw3;
900 uint32_t dw4;
901 uint32_t dw5;
902 uint32_t dw6;
903 uint32_t dw7;
904};
905
906/* JMC250 descriptor structures. */
907struct jme_desc {
908 uint32_t flags;
909 uint32_t buflen;
910 uint32_t addr_hi;
911 uint32_t addr_lo;
912};
913
914#define JME_TD_OWN 0x80000000
915#define JME_TD_INTR 0x40000000
916#define JME_TD_64BIT 0x20000000
917#define JME_TD_TCPCSUM 0x10000000
918#define JME_TD_UDPCSUM 0x08000000
919#define JME_TD_IPCSUM 0x04000000
920#define JME_TD_TSO 0x02000000
921#define JME_TD_VLAN_TAG 0x01000000
922#define JME_TD_VLAN_MASK 0x0000FFFF
923
924#define JME_TD_MSS_MASK 0xFFFC0000
925#define JME_TD_MSS_SHIFT 18
926#define JME_TD_BUF_LEN_MASK 0x0000FFFF
927#define JME_TD_BUF_LEN_SHIFT 0
928
929#define JME_TD_FRAME_LEN_MASK 0x0000FFFF
930#define JME_TD_FRAME_LEN_SHIFT 0
931
932/*
933 * Only the first Tx descriptor of a packet is updated
934 * after packet transmission.
935 */
936#define JME_TD_TMOUT 0x20000000
937#define JME_TD_RETRY_EXP 0x10000000
938#define JME_TD_COLLISION 0x08000000
939#define JME_TD_UNDERRUN 0x04000000
940#define JME_TD_EHDR_SIZE_MASK 0x000000FF
941#define JME_TD_EHDR_SIZE_SHIFT 0
942
943#define JME_TD_SEG_CNT_MASK 0xFFFF0000
944#define JME_TD_SEG_CNT_SHIFT 16
945#define JME_TD_RETRY_CNT_MASK 0x0000FFFF
946#define JME_TD_RETRY_CNT_SHIFT 0
947
948#define JME_RD_OWN 0x80000000
949#define JME_RD_INTR 0x40000000
950#define JME_RD_64BIT 0x20000000
951
952#define JME_RD_BUF_LEN_MASK 0x0000FFFF
953#define JME_RD_BUF_LEN_SHIFT 0
954
955/*
956 * Only the first Rx descriptor of a packet is updated
957 * after packet reception.
958 */
959#define JME_RD_MORE_FRAG 0x20000000
960#define JME_RD_TCP 0x10000000
961#define JME_RD_UDP 0x08000000
962#define JME_RD_IPCSUM 0x04000000
963#define JME_RD_TCPCSUM 0x02000000
964#define JME_RD_UDPCSUM 0x01000000
965#define JME_RD_VLAN_TAG 0x00800000
966#define JME_RD_IPV4 0x00400000
967#define JME_RD_IPV6 0x00200000
968#define JME_RD_PAUSE 0x00100000
969#define JME_RD_MAGIC 0x00080000
970#define JME_RD_WAKEUP 0x00040000
971#define JME_RD_BCAST 0x00030000
972#define JME_RD_MCAST 0x00020000
973#define JME_RD_UCAST 0x00010000
974#define JME_RD_VLAN_MASK 0x0000FFFF
975#define JME_RD_VLAN_SHIFT 0
976
977#define JME_RD_VALID 0x80000000
978#define JME_RD_CNT_MASK 0x7F000000
979#define JME_RD_CNT_SHIFT 24
980#define JME_RD_GIANT 0x00800000
981#define JME_RD_GMII_ERR 0x00400000
982#define JME_RD_NBL_RCVD 0x00200000
983#define JME_RD_COLL 0x00100000
984#define JME_RD_ABORT 0x00080000
985#define JME_RD_RUNT 0x00040000
986#define JME_RD_FIFO_OVRN 0x00020000
987#define JME_RD_CRC_ERR 0x00010000
988#define JME_RD_FRAME_LEN_MASK 0x0000FFFF
989
990#define JME_RX_ERR_STAT \
991 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \
992 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \
993 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR)
994
995#define JME_RD_ERR_MASK 0x00FF0000
996#define JME_RD_ERR_SHIFT 16
997#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT)
998#define JME_RX_ERR_BITS "\20" \
999 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \
1000 "\5COLL\6NBLRCVD\7GMIIERR\10"
1001
1002#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT)
1003#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK)
1004#define JME_RX_PAD_BYTES 10
1005
1006#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF
1007
1008#define JME_RD_RSS_HASH_MASK 0x00003F00
1009#define JME_RD_RSS_HASH_SHIFT 8
1010#define JME_RD_RSS_HASH_NONE 0x00000000
1011#define JME_RD_RSS_HASH_IPV4 0x00000100
1012#define JME_RD_RSS_HASH_IPV4TCP 0x00000200
1013#define JME_RD_RSS_HASH_IPV6 0x00000400
1014#define JME_RD_RSS_HASH_IPV6TCP 0x00001000
1015#define JME_RD_HASH_FN_NONE 0x00000000
1016#define JME_RD_HASH_FN_TOEPLITZ 0x00000001
1017
1018#endif
| 53/* JMC250 PCI configuration register. */
54#define JME_PCI_BAR0 0x10 /* 16KB memory window. */
55
56#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
57
58#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
59
60#define JME_PCI_BAR3 0x20 /* 64KB memory window. */
61
62#define JME_PCI_EROM 0x30
63
64#define JME_PCI_DBG 0x9C
65
66#define JME_PCI_SPI 0xB0
67
68#define SPI_ENB 0x00000010
69#define SPI_SO_STATUS 0x00000008
70#define SPI_SI_CTRL 0x00000004
71#define SPI_SCK_CTRL 0x00000002
72#define SPI_CS_N_CTRL 0x00000001
73
74#define JME_PCI_PHYCFG0 0xC0
75
76#define JME_PCI_PHYCFG1 0xC4
77
78#define JME_PCI_PHYCFG2 0xC8
79
80#define JME_PCI_PHYCFG3 0xCC
81
82#define JME_PCI_PIPECTL1 0xD0
83
84#define JME_PCI_PIPECTL2 0xD4
85
86/* PCIe link error/status. */
87#define JME_PCI_LES 0xD8
88
89/* propeietary register 0. */
90#define JME_PCI_PE0 0xE0
91#define PE0_SPI_EXIST 0x00200000
92#define PE0_PME_D0 0x00100000
93#define PE0_PME_D3H 0x00080000
94#define PE0_PME_SPI_PAD 0x00040000
95#define PE0_MASK_ASPM 0x00020000
96#define PE0_EEPROM_RW_DIS 0x00008000
97#define PE0_PCI_INTA 0x00001000
98#define PE0_PCI_INTB 0x00002000
99#define PE0_PCI_INTC 0x00003000
100#define PE0_PCI_INTD 0x00004000
101#define PE0_PCI_SVSSID_WR_ENB 0x00000800
102#define PE0_MSIX_SIZE_8 0x00000700
103#define PE0_MSIX_SIZE_7 0x00000600
104#define PE0_MSIX_SIZE_6 0x00000500
105#define PE0_MSIX_SIZE_5 0x00000400
106#define PE0_MSIX_SIZE_4 0x00000300
107#define PE0_MSIX_SIZE_3 0x00000200
108#define PE0_MSIX_SIZE_2 0x00000100
109#define PE0_MSIX_SIZE_1 0x00000000
110#define PE0_MSIX_SIZE_DEF 0x00000700
111#define PE0_MSIX_CAP_DIS 0x00000080
112#define PE0_MSI_PVMC_ENB 0x00000040
113#define PE0_LCAP_EXIT_LAT_MASK 0x00000038
114#define PE0_LCAP_EXIT_LAT_DEF 0x00000038
115#define PE0_PM_AUXC_MASK 0x00000007
116#define PE0_PM_AUXC_DEF 0x00000007
117
118#define JME_PCI_PE1 0xE4
119
120#define JME_PCI_PHYTEST 0xF8
121
122#define JME_PCI_GPR 0xFC
123
124/*
125 * JMC Register Map.
126 * -----------------------------------------------------------------------
127 * Register Size IO space Memory space
128 * -----------------------------------------------------------------------
129 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~
130 * BAR1 + 0x7F BAR0 + 0x7F
131 * -----------------------------------------------------------------------
132 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~
133 * BAR2 + 0x7F BAR0 + 0x47F
134 * -----------------------------------------------------------------------
135 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~
136 * BAR2 + 0x7F BAR0 + 0x87F
137 * -----------------------------------------------------------------------
138 * To simplify register access fuctions and to get better performance
139 * this driver doesn't support IO space access. It could be implemented
140 * as a function which selects appropriate BARs to access requested
141 * register.
142 */
143
144/* Tx control and status. */
145#define JME_TXCSR 0x0000
146#define TXCSR_QWEIGHT_MASK 0x0F000000
147#define TXCSR_QWEIGHT_SHIFT 24
148#define TXCSR_TXQ_SEL_MASK 0x00070000
149#define TXCSR_TXQ_SEL_SHIFT 16
150#define TXCSR_TXQ_START 0x00000001
151#define TXCSR_TXQ_START_SHIFT 8
152#define TXCSR_FIFO_THRESH_4QW 0x00000000
153#define TXCSR_FIFO_THRESH_8QW 0x00000040
154#define TXCSR_FIFO_THRESH_12QW 0x00000080
155#define TXCSR_FIFO_THRESH_16QW 0x000000C0
156#define TXCSR_DMA_SIZE_64 0x00000000
157#define TXCSR_DMA_SIZE_128 0x00000010
158#define TXCSR_DMA_SIZE_256 0x00000020
159#define TXCSR_DMA_SIZE_512 0x00000030
160#define TXCSR_DMA_BURST 0x00000004
161#define TXCSR_TX_SUSPEND 0x00000002
162#define TXCSR_TX_ENB 0x00000001
163#define TXCSR_TXQ0 0
164#define TXCSR_TXQ1 1
165#define TXCSR_TXQ2 2
166#define TXCSR_TXQ3 3
167#define TXCSR_TXQ4 4
168#define TXCSR_TXQ5 5
169#define TXCSR_TXQ6 6
170#define TXCSR_TXQ7 7
171#define TXCSR_TXQ_WEIGHT(x) \
172 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK)
173#define TXCSR_TXQ_WEIGHT_MIN 0
174#define TXCSR_TXQ_WEIGHT_MAX 15
175#define TXCSR_TXQ_N_SEL(x) \
176 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK)
177#define TXCSR_TXQ_N_START(x) \
178 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x)))
179
180/* Tx queue descriptor base address. 16bytes alignment required. */
181#define JME_TXDBA_LO 0x0004
182#define JME_TXDBA_HI 0x0008
183
184/* Tx queue descriptor count. multiple of 16(max = 1024). */
185#define JME_TXQDC 0x000C
186#define TXQDC_MASK 0x0000007F0
187
188/* Tx queue next descriptor address. */
189#define JME_TXNDA 0x0010
190#define TXNDA_ADDR_MASK 0xFFFFFFF0
191#define TXNDA_DESC_EMPTY 0x00000008
192#define TXNDA_DESC_VALID 0x00000004
193#define TXNDA_DESC_WAIT 0x00000002
194#define TXNDA_DESC_FETCH 0x00000001
195
196/* Tx MAC control ans status. */
197#define JME_TXMAC 0x0014
198#define TXMAC_IFG2_MASK 0xC0000000
199#define TXMAC_IFG2_DEFAULT 0x40000000
200#define TXMAC_IFG1_MASK 0x30000000
201#define TXMAC_IFG1_DEFAULT 0x20000000
202#define TXMAC_THRESH_1_PKT 0x00000300
203#define TXMAC_THRESH_1_2_PKT 0x00000200
204#define TXMAC_THRESH_1_4_PKT 0x00000100
205#define TXMAC_THRESH_1_8_PKT 0x00000000
206#define TXMAC_FRAME_BURST 0x00000080
207#define TXMAC_CARRIER_EXT 0x00000040
208#define TXMAC_IFG_ENB 0x00000020
209#define TXMAC_BACKOFF 0x00000010
210#define TXMAC_CARRIER_SENSE 0x00000008
211#define TXMAC_COLL_ENB 0x00000004
212#define TXMAC_CRC_ENB 0x00000002
213#define TXMAC_PAD_ENB 0x00000001
214
215/* Tx pause frame control. */
216#define JME_TXPFC 0x0018
217#define TXPFC_VLAN_TAG_MASK 0xFFFF0000
218#define TXPFC_VLAN_TAG_SHIFT 16
219#define TXPFC_VLAN_ENB 0x00008000
220#define TXPFC_PAUSE_ENB 0x00000001
221
222/* Tx timer/retry at half duplex. */
223#define JME_TXTRHD 0x001C
224#define TXTRHD_RT_PERIOD_ENB 0x80000000
225#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00
226#define TXTRHD_RT_PERIOD_SHIFT 8
227#define TXTRHD_RT_LIMIT_ENB 0x00000080
228#define TXTRHD_RT_LIMIT_MASK 0x0000007F
229#define TXTRHD_RT_LIMIT_SHIFT 0
230#define TXTRHD_RT_PERIOD_DEFAULT 8192
231#define TXTRHD_RT_LIMIT_DEFAULT 8
232
233/* Rx control & status. */
234#define JME_RXCSR 0x0020
235#define RXCSR_FIFO_FTHRESH_16T 0x00000000
236#define RXCSR_FIFO_FTHRESH_32T 0x10000000
237#define RXCSR_FIFO_FTHRESH_64T 0x20000000
238#define RXCSR_FIFO_FTHRESH_128T 0x30000000
239#define RXCSR_FIFO_FTHRESH_MASK 0x30000000
240#define RXCSR_FIFO_THRESH_16QW 0x00000000
241#define RXCSR_FIFO_THRESH_32QW 0x04000000
242#define RXCSR_FIFO_THRESH_64QW 0x08000000
243#define RXCSR_FIFO_THRESH_128QW 0x0C000000
244#define RXCSR_FIFO_THRESH_MASK 0x0C000000
245#define RXCSR_DMA_SIZE_16 0x00000000
246#define RXCSR_DMA_SIZE_32 0x01000000
247#define RXCSR_DMA_SIZE_64 0x02000000
248#define RXCSR_DMA_SIZE_128 0x03000000
249#define RXCSR_RXQ_SEL_MASK 0x00030000
250#define RXCSR_RXQ_SEL_SHIFT 16
251#define RXCSR_DESC_RT_GAP_MASK 0x0000F000
252#define RXCSR_DESC_RT_GAP_SHIFT 12
253#define RXCSR_DESC_RT_GAP_256 0x00000000
254#define RXCSR_DESC_RT_GAP_512 0x00001000
255#define RXCSR_DESC_RT_GAP_1024 0x00002000
256#define RXCSR_DESC_RT_GAP_2048 0x00003000
257#define RXCSR_DESC_RT_GAP_4096 0x00004000
258#define RXCSR_DESC_RT_GAP_8192 0x00005000
259#define RXCSR_DESC_RT_GAP_16384 0x00006000
260#define RXCSR_DESC_RT_GAP_32768 0x00007000
261#define RXCSR_DESC_RT_CNT_MASK 0x00000F00
262#define RXCSR_DESC_RT_CNT_SHIFT 8
263#define RXCSR_PASS_WAKEUP_PKT 0x00000040
264#define RXCSR_PASS_MAGIC_PKT 0x00000020
265#define RXCSR_PASS_RUNT_PKT 0x00000010
266#define RXCSR_PASS_BAD_PKT 0x00000008
267#define RXCSR_RXQ_START 0x00000004
268#define RXCSR_RX_SUSPEND 0x00000002
269#define RXCSR_RX_ENB 0x00000001
270
271#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT)
272#define RXCSR_RXQ0 0
273#define RXCSR_RXQ1 1
274#define RXCSR_RXQ2 2
275#define RXCSR_RXQ3 3
276#define RXCSR_DESC_RT_CNT(x) \
277 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
278#define RXCSR_DESC_RT_CNT_DEFAULT 32
279
280/* Rx queue descriptor base address. 16bytes alignment needed. */
281#define JME_RXDBA_LO 0x0024
282#define JME_RXDBA_HI 0x0028
283
284/* Rx queue descriptor count. multiple of 16(max = 1024). */
285#define JME_RXQDC 0x002C
286#define RXQDC_MASK 0x0000007F0
287
288/* Rx queue next descriptor address. */
289#define JME_RXNDA 0x0030
290#define RXNDA_ADDR_MASK 0xFFFFFFF0
291#define RXNDA_DESC_EMPTY 0x00000008
292#define RXNDA_DESC_VALID 0x00000004
293#define RXNDA_DESC_WAIT 0x00000002
294#define RXNDA_DESC_FETCH 0x00000001
295
296/* Rx MAC control and status. */
297#define JME_RXMAC 0x0034
298#define RXMAC_RSS_UNICAST 0x00000000
299#define RXMAC_RSS_UNI_MULTICAST 0x00010000
300#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000
301#define RXMAC_RSS_ALLFRAME 0x00030000
302#define RXMAC_PROMISC 0x00000800
303#define RXMAC_BROADCAST 0x00000400
304#define RXMAC_MULTICAST 0x00000200
305#define RXMAC_UNICAST 0x00000100
306#define RXMAC_ALLMULTI 0x00000080
307#define RXMAC_MULTICAST_FILTER 0x00000040
308#define RXMAC_COLL_DET_ENB 0x00000020
309#define RXMAC_FC_ENB 0x00000008
310#define RXMAC_VLAN_ENB 0x00000004
311#define RXMAC_PAD_10BYTES 0x00000002
312#define RXMAC_CSUM_ENB 0x00000001
313
314/* Rx unicast MAC address. */
315#define JME_PAR0 0x0038
316#define JME_PAR1 0x003C
317
318/* Rx multicast address hash table. */
319#define JME_MAR0 0x0040
320#define JME_MAR1 0x0044
321
322/* Wakeup frame output data port. */
323#define JME_WFODP 0x0048
324
325/* Wakeup frame output interface. */
326#define JME_WFOI 0x004C
327#define WFOI_MASK_0_31 0x00000000
328#define WFOI_MASK_31_63 0x00000010
329#define WFOI_MASK_64_95 0x00000020
330#define WFOI_MASK_96_127 0x00000030
331#define WFOI_MASK_SEL 0x00000008
332#define WFOI_CRC_SEL 0x00000000
333#define WFOI_WAKEUP_FRAME_MASK 0x00000007
334#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK)
335
336/* Station management interface. */
337#define JME_SMI 0x0050
338#define SMI_DATA_MASK 0xFFFF0000
339#define SMI_DATA_SHIFT 16
340#define SMI_REG_ADDR_MASK 0x0000F800
341#define SMI_REG_ADDR_SHIFT 11
342#define SMI_PHY_ADDR_MASK 0x000007C0
343#define SMI_PHY_ADDR_SHIFT 6
344#define SMI_OP_WRITE 0x00000020
345#define SMI_OP_READ 0x00000000
346#define SMI_OP_EXECUTE 0x00000010
347#define SMI_MDIO 0x00000008
348#define SMI_MDOE 0x00000004
349#define SMI_MDC 0x00000002
350#define SMI_MDEN 0x00000001
351#define SMI_REG_ADDR(x) \
352 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK)
353#define SMI_PHY_ADDR(x) \
354 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK)
355
356/* Global host control. */
357#define JME_GHC 0x0054
358#define GHC_LOOPBACK 0x80000000
359#define GHC_RESET 0x40000000
360#define GHC_FULL_DUPLEX 0x00000040
361#define GHC_SPEED_UNKNOWN 0x00000000
362#define GHC_SPEED_10 0x00000010
363#define GHC_SPEED_100 0x00000020
364#define GHC_SPEED_1000 0x00000030
365#define GHC_SPEED_MASK 0x00000030
366#define GHC_LINK_OFF 0x00000004
367#define GHC_LINK_ON 0x00000002
368#define GHC_LINK_STAT_POLLING 0x00000001
369
370/* Power management control and status. */
371#define JME_PMCS 0x0060
372#define PMCS_WAKEUP_FRAME_7 0x80000000
373#define PMCS_WAKEUP_FRAME_6 0x40000000
374#define PMCS_WAKEUP_FRAME_5 0x20000000
375#define PMCS_WAKEUP_FRAME_4 0x10000000
376#define PMCS_WAKEUP_FRAME_3 0x08000000
377#define PMCS_WAKEUP_FRAME_2 0x04000000
378#define PMCS_WAKEUP_FRAME_1 0x02000000
379#define PMCS_WAKEUP_FRAME_0 0x01000000
380#define PMCS_LINK_FAIL 0x00040000
381#define PMCS_LINK_RISING 0x00020000
382#define PMCS_MAGIC_FRAME 0x00010000
383#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000
384#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000
385#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000
386#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000
387#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800
388#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400
389#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200
390#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100
391#define PMCS_LINK_FAIL_ENB 0x00000004
392#define PMCS_LINK_RISING_ENB 0x00000002
393#define PMCS_MAGIC_FRAME_ENB 0x00000001
394#define PMCS_WOL_ENB_MASK 0x0000FFFF
395
396/* Giga PHY & EEPROM registers. */
397#define JME_PHY_EEPROM_BASE_ADDR 0x0400
398
399#define JME_GIGAR0LO 0x0400
400#define JME_GIGAR0HI 0x0404
401#define JME_GIGARALO 0x0408
402#define JME_GIGARAHI 0x040C
403#define JME_GIGARBLO 0x0410
404#define JME_GIGARBHI 0x0414
405#define JME_GIGARCLO 0x0418
406#define JME_GIGARCHI 0x041C
407#define JME_GIGARDLO 0x0420
408#define JME_GIGARDHI 0x0424
409
410/* BIST status and control. */
411#define JME_GIGACSR 0x0428
412#define GIGACSR_STATUS 0x40000000
413#define GIGACSR_CTRL_MASK 0x30000000
414#define GIGACSR_CTRL_DEFAULT 0x30000000
415#define GIGACSR_TX_CLK_MASK 0x0F000000
416#define GIGACSR_RX_CLK_MASK 0x00F00000
417#define GIGACSR_TX_CLK_INV 0x00080000
418#define GIGACSR_RX_CLK_INV 0x00040000
419#define GIGACSR_PHY_RST 0x00010000
420#define GIGACSR_IRQ_N_O 0x00001000
421#define GIGACSR_BIST_OK 0x00000200
422#define GIGACSR_BIST_DONE 0x00000100
423#define GIGACSR_BIST_LED_ENB 0x00000010
424#define GIGACSR_BIST_MASK 0x00000003
425
426/* PHY Link Status. */
427#define JME_LNKSTS 0x0430
428#define LINKSTS_SPEED_10 0x00000000
429#define LINKSTS_SPEED_100 0x00004000
430#define LINKSTS_SPEED_1000 0x00008000
431#define LINKSTS_FULL_DUPLEX 0x00002000
432#define LINKSTS_PAGE_RCVD 0x00001000
433#define LINKSTS_SPDDPX_RESOLVED 0x00000800
434#define LINKSTS_UP 0x00000400
435#define LINKSTS_ANEG_COMP 0x00000200
436#define LINKSTS_MDI_CROSSOVR 0x00000040
437#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002
438#define LINKSTS_LPAR_PAUSE 0x00000001
439
440/* SMB control and status. */
441#define JME_SMBCSR 0x0440
442#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000
443#define SMBCSR_WR_DATA_NACK 0x00040000
444#define SMBCSR_CMD_NACK 0x00020000
445#define SMBCSR_RELOAD 0x00010000
446#define SMBCSR_CMD_ADDR_MASK 0x0000FF00
447#define SMBCSR_SCL_STAT 0x00000080
448#define SMBCSR_SDA_STAT 0x00000040
449#define SMBCSR_EEPROM_PRESENT 0x00000020
450#define SMBCSR_INIT_LD_DONE 0x00000010
451#define SMBCSR_HW_BUSY_MASK 0x0000000F
452#define SMBCSR_HW_IDLE 0x00000000
453
454/* SMB interface. */
455#define JME_SMBINTF 0x0444
456#define SMBINTF_RD_DATA_MASK 0xFF000000
457#define SMBINTF_RD_DATA_SHIFT 24
458#define SMBINTF_WR_DATA_MASK 0x00FF0000
459#define SMBINTF_WR_DATA_SHIFT 16
460#define SMBINTF_ADDR_MASK 0x0000FF00
461#define SMBINTF_ADDR_SHIFT 8
462#define SMBINTF_RD 0x00000020
463#define SMBINTF_WR 0x00000000
464#define SMBINTF_CMD_TRIGGER 0x00000010
465#define SMBINTF_BUSY 0x00000010
466#define SMBINTF_FAST_MODE 0x00000008
467#define SMBINTF_GPIO_SCL 0x00000004
468#define SMBINTF_GPIO_SDA 0x00000002
469#define SMBINTF_GPIO_ENB 0x00000001
470
471#define JME_EEPROM_SIG0 0x55
472#define JME_EEPROM_SIG1 0xAA
473#define JME_EEPROM_DESC_BYTES 3
474#define JME_EEPROM_DESC_END 0x80
475#define JME_EEPROM_FUNC_MASK 0x70
476#define JME_EEPROM_FUNC_SHIFT 4
477#define JME_EEPROM_PAGE_MASK 0x0F
478#define JME_EEPROM_PAGE_SHIFT 0
479
480#define JME_EEPROM_FUNC0 0
481/* PCI configuration space. */
482#define JME_EEPROM_PAGE_BAR0 0
483/* 128 bytes I/O window. */
484#define JME_EEPROM_PAGE_BAR1 1
485/* 256 bytes I/O window. */
486#define JME_EEPROM_PAGE_BAR2 2
487
488#define JME_EEPROM_END 0xFF
489
490#define JME_EEPROM_MKDESC(f, p) \
491 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \
492 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT))
493
494/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */
495#define JME_EEPINTF 0x0448
496#define EEPINTF_DATA_MASK 0xFFFF0000
497#define EEPINTF_DATA_SHIFT 16
498#define EEPINTF_ADDR_MASK 0x0000FC00
499#define EEPINTF_ADDR_SHIFT 10
500#define EEPRINTF_OP_MASK 0x00000300
501#define EEPINTF_OP_EXECUTE 0x00000080
502#define EEPINTF_DATA_OUT 0x00000008
503#define EEPINTF_DATA_IN 0x00000004
504#define EEPINTF_CLK 0x00000002
505#define EEPINTF_SEL 0x00000001
506
507/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */
508#define JME_EEPCSR 0x044C
509#define EEPCSR_EEPROM_RELOAD 0x00000002
510#define EEPCSR_EEPROM_PRESENT 0x00000001
511
512/* Misc registers. */
513#define JME_MISC_BASE_ADDR 0x800
514
515/* Timer control and status. */
516#define JME_TMCSR 0x0800
517#define TMCSR_SW_INTR 0x80000000
518#define TMCSR_TIMER_INTR 0x10000000
519#define TMCSR_TIMER_ENB 0x01000000
520#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF
521
522/* GPIO control and status. */
523#define JME_GPIO 0x0804
524#define GPIO_4_SPI_IN 0x80000000
525#define GPIO_3_SPI_IN 0x40000000
526#define GPIO_4_SPI_OUT 0x20000000
527#define GPIO_4_SPI_OUT_ENB 0x10000000
528#define GPIO_3_SPI_OUT 0x08000000
529#define GPIO_3_SPI_OUT_ENB 0x04000000
530#define GPIO_3_4_LED 0x00000000
531#define GPIO_3_4_GPIO 0x02000000
532#define GPIO_2_CLKREQN_IN 0x00100000
533#define GPIO_2_CLKREQN_OUT 0x00040000
534#define GPIO_2_CLKREQN_OUT_ENB 0x00020000
535#define GPIO_1_LED42_IN 0x00001000
536#define GPIO_1_LED42_OUT 0x00000400
537#define GPIO_1_LED42_OUT_ENB 0x00000200
538#define GPIO_1_LED42_ENB 0x00000100
539#define GPIO_0_SDA_IN 0x00000010
540#define GPIO_0_SDA_OUT 0x00000004
541#define GPIO_0_SDA_OUT_ENB 0x00000002
542#define GPIO_0_SDA_ENB 0x00000001
543
544/* General purpose register 0. */
545#define JME_GPREG0 0x0808
546#define GPREG0_SH_POST_DW7_DIS 0x80000000
547#define GPREG0_SH_POST_DW6_DIS 0x40000000
548#define GPREG0_SH_POST_DW5_DIS 0x20000000
549#define GPREG0_SH_POST_DW4_DIS 0x10000000
550#define GPREG0_SH_POST_DW3_DIS 0x08000000
551#define GPREG0_SH_POST_DW2_DIS 0x04000000
552#define GPREG0_SH_POST_DW1_DIS 0x02000000
553#define GPREG0_SH_POST_DW0_DIS 0x01000000
554#define GPREG0_DMA_RD_REQ_8 0x00000000
555#define GPREG0_DMA_RD_REQ_6 0x00100000
556#define GPREG0_DMA_RD_REQ_5 0x00200000
557#define GPREG0_DMA_RD_REQ_4 0x00300000
558#define GPREG0_POST_DW0_ENB 0x00040000
559#define GPREG0_PCC_CLR_DIS 0x00020000
560#define GPREG0_FORCE_SCL_OUT 0x00010000
561#define GPREG0_DL_RSTB_DIS 0x00008000
562#define GPREG0_STICKY_RESET 0x00004000
563#define GPREG0_DL_RSTB_CFG_DIS 0x00002000
564#define GPREG0_LINK_CHG_POLL 0x00001000
565#define GPREG0_LINK_CHG_DIRECT 0x00000000
566#define GPREG0_MSI_GEN_SEL 0x00000800
567#define GPREG0_SMB_PAD_PU_DIS 0x00000400
568#define GPREG0_PCC_UNIT_16US 0x00000000
569#define GPREG0_PCC_UNIT_256US 0x00000100
570#define GPREG0_PCC_UNIT_US 0x00000200
571#define GPREG0_PCC_UNIT_MS 0x00000300
572#define GPREG0_PCC_UNIT_MASK 0x00000300
573#define GPREG0_INTR_EVENT_ENB 0x00000080
574#define GPREG0_PME_ENB 0x00000020
575#define GPREG0_PHY_ADDR_MASK 0x0000001F
576#define GPREG0_PHY_ADDR_SHIFT 0
577#define GPREG0_PHY_ADDR 1
578
579/* General purpose register 1. */
580#define JME_GPREG1 0x080C
581#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */
582#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */
583#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */
584#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */
585#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */
586#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */
587#define GPREG1_INTDLY_MASK 0x00000007
588
589/* MSIX entry number of interrupt source. */
590#define JME_MSINUM_BASE 0x0810
591#define JME_MSINUM_END 0x081F
592#define MSINUM_MASK 0x7FFFFFFF
593#define MSINUM_ENTRY_MASK 7
594#define MSINUM_REG_INDEX(x) ((x) / 8)
595#define MSINUM_INTR_SOURCE(x, y) \
596 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4))
597#define MSINUM_NUM_INTR_SOURCE 32
598
599/* Interrupt event status. */
600#define JME_INTR_STATUS 0x0820
601#define INTR_SW 0x80000000
602#define INTR_TIMER 0x40000000
603#define INTR_LINKCHG 0x20000000
604#define INTR_PAUSE 0x10000000
605#define INTR_MAGIC_PKT 0x08000000
606#define INTR_WAKEUP_PKT 0x04000000
607#define INTR_RXQ0_COAL_TO 0x02000000
608#define INTR_RXQ1_COAL_TO 0x01000000
609#define INTR_RXQ2_COAL_TO 0x00800000
610#define INTR_RXQ3_COAL_TO 0x00400000
611#define INTR_TXQ_COAL_TO 0x00200000
612#define INTR_RXQ0_COAL 0x00100000
613#define INTR_RXQ1_COAL 0x00080000
614#define INTR_RXQ2_COAL 0x00040000
615#define INTR_RXQ3_COAL 0x00020000
616#define INTR_TXQ_COAL 0x00010000
617#define INTR_RXQ3_DESC_EMPTY 0x00008000
618#define INTR_RXQ2_DESC_EMPTY 0x00004000
619#define INTR_RXQ1_DESC_EMPTY 0x00002000
620#define INTR_RXQ0_DESC_EMPTY 0x00001000
621#define INTR_RXQ3_COMP 0x00000800
622#define INTR_RXQ2_COMP 0x00000400
623#define INTR_RXQ1_COMP 0x00000200
624#define INTR_RXQ0_COMP 0x00000100
625#define INTR_TXQ7_COMP 0x00000080
626#define INTR_TXQ6_COMP 0x00000040
627#define INTR_TXQ5_COMP 0x00000020
628#define INTR_TXQ4_COMP 0x00000010
629#define INTR_TXQ3_COMP 0x00000008
630#define INTR_TXQ2_COMP 0x00000004
631#define INTR_TXQ1_COMP 0x00000002
632#define INTR_TXQ0_COMP 0x00000001
633
634#define INTR_RXQ_COAL_TO \
635 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \
636 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO)
637
638#define INTR_RXQ_COAL \
639 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \
640 INTR_RXQ3_COAL)
641
642#define INTR_RXQ_COMP \
643 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
644 INTR_RXQ3_COMP)
645
646#define INTR_RXQ_DESC_EMPTY \
647 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \
648 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY)
649
650#define INTR_RXQ_COMP \
651 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
652 INTR_RXQ3_COMP)
653
654#define INTR_TXQ_COMP \
655 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \
656 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \
657 INTR_TXQ6_COMP | INTR_TXQ7_COMP)
658
659#define JME_INTRS \
660 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \
661 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY)
662
663#define N_INTR_SW 31
664#define N_INTR_TIMER 30
665#define N_INTR_LINKCHG 29
666#define N_INTR_PAUSE 28
667#define N_INTR_MAGIC_PKT 27
668#define N_INTR_WAKEUP_PKT 26
669#define N_INTR_RXQ0_COAL_TO 25
670#define N_INTR_RXQ1_COAL_TO 24
671#define N_INTR_RXQ2_COAL_TO 23
672#define N_INTR_RXQ3_COAL_TO 22
673#define N_INTR_TXQ_COAL_TO 21
674#define N_INTR_RXQ0_COAL 20
675#define N_INTR_RXQ1_COAL 19
676#define N_INTR_RXQ2_COAL 18
677#define N_INTR_RXQ3_COAL 17
678#define N_INTR_TXQ_COAL 16
679#define N_INTR_RXQ3_DESC_EMPTY 15
680#define N_INTR_RXQ2_DESC_EMPTY 14
681#define N_INTR_RXQ1_DESC_EMPTY 13
682#define N_INTR_RXQ0_DESC_EMPTY 12
683#define N_INTR_RXQ3_COMP 11
684#define N_INTR_RXQ2_COMP 10
685#define N_INTR_RXQ1_COMP 9
686#define N_INTR_RXQ0_COMP 8
687#define N_INTR_TXQ7_COMP 7
688#define N_INTR_TXQ6_COMP 6
689#define N_INTR_TXQ5_COMP 5
690#define N_INTR_TXQ4_COMP 4
691#define N_INTR_TXQ3_COMP 3
692#define N_INTR_TXQ2_COMP 2
693#define N_INTR_TXQ1_COMP 1
694#define N_INTR_TXQ0_COMP 0
695
696/* Interrupt request status. */
697#define JME_INTR_REQ_STATUS 0x0824
698
699/* Interrupt enable - setting port. */
700#define JME_INTR_MASK_SET 0x0828
701
702/* Interrupt enable - clearing port. */
703#define JME_INTR_MASK_CLR 0x082C
704
705/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */
706#define JME_PCCRX0 0x0830
707#define JME_PCCRX1 0x0834
708#define JME_PCCRX2 0x0838
709#define JME_PCCRX3 0x083C
710#define PCCRX_COAL_TO_MASK 0xFFFF0000
711#define PCCRX_COAL_TO_SHIFT 16
712#define PCCRX_COAL_PKT_MASK 0x0000FF00
713#define PCCRX_COAL_PKT_SHIFT 8
714
715#define PCCRX_COAL_TO_MIN 1
716#define PCCRX_COAL_TO_DEFAULT 100
717#define PCCRX_COAL_TO_MAX 65535
718
719#define PCCRX_COAL_PKT_MIN 1
720#define PCCRX_COAL_PKT_DEFAULT 2
721#define PCCRX_COAL_PKT_MAX 255
722
723/* Packet completion coalescing control of Tx queue. */
724#define JME_PCCTX 0x0840
725#define PCCTX_COAL_TO_MASK 0xFFFF0000
726#define PCCTX_COAL_TO_SHIFT 16
727#define PCCTX_COAL_PKT_MASK 0x0000FF00
728#define PCCTX_COAL_PKT_SHIFT 8
729#define PCCTX_COAL_TXQ7 0x00000080
730#define PCCTX_COAL_TXQ6 0x00000040
731#define PCCTX_COAL_TXQ5 0x00000020
732#define PCCTX_COAL_TXQ4 0x00000010
733#define PCCTX_COAL_TXQ3 0x00000008
734#define PCCTX_COAL_TXQ2 0x00000004
735#define PCCTX_COAL_TXQ1 0x00000002
736#define PCCTX_COAL_TXQ0 0x00000001
737
738#define PCCTX_COAL_TO_MIN 1
739#define PCCTX_COAL_TO_DEFAULT 100
740#define PCCTX_COAL_TO_MAX 65535
741
742#define PCCTX_COAL_PKT_MIN 1
743#define PCCTX_COAL_PKT_DEFAULT 8
744#define PCCTX_COAL_PKT_MAX 255
745
746/* Chip mode and FPGA version. */
747#define JME_CHIPMODE 0x0844
748#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000
749#define CHIPMODE_FPGA_REV_SHIFT 16
750#define CHIPMODE_NOT_FPGA 0
751#define CHIPMODE_REV_MASK 0x0000FF00
752#define CHIPMODE_REV_SHIFT 8
753#define CHIPMODE_MODE_48P 0x0000000C
754#define CHIPMODE_MODE_64P 0x00000004
755#define CHIPMODE_MODE_128P_MAC 0x00000003
756#define CHIPMODE_MODE_128P_DBG 0x00000002
757#define CHIPMODE_MODE_128P_PHY 0x00000000
758
759/* Shadow status base address high/low. */
760#define JME_SHBASE_ADDR_HI 0x0848
761#define JME_SHBASE_ADDR_LO 0x084C
762#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0
763#define SHBASE_POST_FORCE 0x00000002
764#define SHBASE_POST_ENB 0x00000001
765
766/* Timer 1 and 2. */
767#define JME_TIMER1 0x0870
768#define JME_TIMER2 0x0874
769#define TIMER_ENB 0x01000000
770#define TIMER_CNT_MASK 0x00FFFFFF
771#define TIMER_CNT_SHIFT 0
772#define TIMER_UNIT 1024 /* 1024us */
773
774/* Aggresive power mode control. */
775#define JME_APMC 0x087C
776#define APMC_PCIE_SDOWN_STAT 0x80000000
777#define APMC_PCIE_SDOWN_ENB 0x40000000
778#define APMC_PSEUDO_HOT_PLUG 0x20000000
779#define APMC_EXT_PLUGIN_ENB 0x04000000
780#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000
781#define APMC_DIS_SRAM 0x00000004
782#define APMC_DIS_CLKPM 0x00000002
783#define APMC_DIS_CLKTX 0x00000001
784
785/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */
786#define JME_PCCSRX_BASE 0x0880
787#define JME_PCCSRX_END 0x088F
788#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4))
789#define PCCSRX_TO_MASK 0xFFFF0000
790#define PCCSRX_TO_SHIFT 16
791#define PCCSRX_PKT_CNT_MASK 0x0000FF00
792#define PCCSRX_PKT_CNT_SHIFT 8
793
794/* Packet completion coalesing status of Tx queue. */
795#define JME_PCCSTX 0x0890
796#define PCCSTX_TO_MASK 0xFFFF0000
797#define PCCSTX_TO_SHIFT 16
798#define PCCSTX_PKT_CNT_MASK 0x0000FF00
799#define PCCSTX_PKT_CNT_SHIFT 8
800
801/* Tx queues empty indicator. */
802#define JME_TXQEMPTY 0x0894
803#define TXQEMPTY_TXQ7 0x00000080
804#define TXQEMPTY_TXQ6 0x00000040
805#define TXQEMPTY_TXQ5 0x00000020
806#define TXQEMPTY_TXQ4 0x00000010
807#define TXQEMPTY_TXQ3 0x00000008
808#define TXQEMPTY_TXQ2 0x00000004
809#define TXQEMPTY_TXQ1 0x00000002
810#define TXQEMPTY_TXQ0 0x00000001
811#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y)))
812
813/* RSS control registers. */
814#define JME_RSS_BASE 0x0C00
815
816#define JME_RSSC 0x0C00
817#define RSSC_HASH_LEN_MASK 0x0000E000
818#define RSSC_HASH_64_ENTRY 0x0000A000
819#define RSSC_HASH_128_ENTRY 0x0000E000
820#define RSSC_HASH_NONE 0x00001000
821#define RSSC_HASH_IPV6 0x00000800
822#define RSSC_HASH_IPV4 0x00000400
823#define RSSC_HASH_IPV6_TCP 0x00000200
824#define RSSC_HASH_IPV4_TCP 0x00000100
825#define RSSC_NCPU_MASK 0x000000F8
826#define RSSC_NCPU_SHIFT 3
827#define RSSC_DIS_RSS 0x00000000
828#define RSSC_2RXQ_ENB 0x00000001
829#define RSSS_4RXQ_ENB 0x00000002
830
831/* CPU vector. */
832#define JME_RSSCPU 0x0C04
833#define RSSCPU_N_SEL(x) ((1 << (x))
834
835/* RSS Hash value. */
836#define JME_RSSHASH 0x0C10
837
838#define JME_RSSHASH_STAT 0x0C14
839
840#define JME_RSS_RDATA0 0x0C18
841
842#define JME_RSS_RDATA1 0x0C1C
843
844/* RSS secret key. */
845#define JME_RSSKEY_BASE 0x0C40
846#define JME_RSSKEY_LAST 0x0C64
847#define JME_RSSKEY_END 0x0C67
848#define HASHKEY_NBYTES 40
849#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4)))
850#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4)))
851
852/* RSS indirection table entries. */
853#define JME_RSSTBL_BASE 0x0C80
854#define JME_RSSTBL_END 0x0CFF
855#define RSSTBL_NENTRY 128
856#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4))
857#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4)))
858
859/* MSI-X table. */
860#define JME_MSIX_BASE_ADDR 0x2000
861
862#define JME_MSIX_BASE 0x2000
863#define JME_MSIX_END 0x207F
864#define JME_MSIX_NENTRY 8
865#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10))
866#define MSIX_ADDR_HI_OFF 0x00
867#define MSIX_ADDR_LO_OFF 0x04
868#define MSIX_ADDR_LO_MASK 0xFFFFFFFC
869#define MSIX_DATA_OFF 0x08
870#define MSIX_VECTOR_OFF 0x0C
871#define MSIX_VECTOR_RSVD 0x80000000
872#define MSIX_VECTOR_DIS 0x00000001
873
874/* MSI-X PBA. */
875#define JME_MSIX_PBA_BASE_ADDR 0x3000
876
877#define JME_MSIX_PBA 0x3000
878#define MSIX_PBA_RSVD_MASK 0xFFFFFF00
879#define MSIX_PBA_RSVD_SHIFT 8
880#define MSIX_PBA_PEND_MASK 0x000000FF
881#define MSIX_PBA_PEND_SHIFT 0
882#define MSIX_PBA_PEND_ENTRY7 0x00000080
883#define MSIX_PBA_PEND_ENTRY6 0x00000040
884#define MSIX_PBA_PEND_ENTRY5 0x00000020
885#define MSIX_PBA_PEND_ENTRY4 0x00000010
886#define MSIX_PBA_PEND_ENTRY3 0x00000008
887#define MSIX_PBA_PEND_ENTRY2 0x00000004
888#define MSIX_PBA_PEND_ENTRY1 0x00000002
889#define MSIX_PBA_PEND_ENTRY0 0x00000001
890
891#define JME_PHY_OUI 0x001B8C
892#define JME_PHY_MODEL 0x21
893#define JME_PHY_REV 0x01
894#define JME_PHY_ADDR 1
895
896/* JMC250 shadow status block. */
897struct jme_ssb {
898 uint32_t dw0;
899 uint32_t dw1;
900 uint32_t dw2;
901 uint32_t dw3;
902 uint32_t dw4;
903 uint32_t dw5;
904 uint32_t dw6;
905 uint32_t dw7;
906};
907
908/* JMC250 descriptor structures. */
909struct jme_desc {
910 uint32_t flags;
911 uint32_t buflen;
912 uint32_t addr_hi;
913 uint32_t addr_lo;
914};
915
916#define JME_TD_OWN 0x80000000
917#define JME_TD_INTR 0x40000000
918#define JME_TD_64BIT 0x20000000
919#define JME_TD_TCPCSUM 0x10000000
920#define JME_TD_UDPCSUM 0x08000000
921#define JME_TD_IPCSUM 0x04000000
922#define JME_TD_TSO 0x02000000
923#define JME_TD_VLAN_TAG 0x01000000
924#define JME_TD_VLAN_MASK 0x0000FFFF
925
926#define JME_TD_MSS_MASK 0xFFFC0000
927#define JME_TD_MSS_SHIFT 18
928#define JME_TD_BUF_LEN_MASK 0x0000FFFF
929#define JME_TD_BUF_LEN_SHIFT 0
930
931#define JME_TD_FRAME_LEN_MASK 0x0000FFFF
932#define JME_TD_FRAME_LEN_SHIFT 0
933
934/*
935 * Only the first Tx descriptor of a packet is updated
936 * after packet transmission.
937 */
938#define JME_TD_TMOUT 0x20000000
939#define JME_TD_RETRY_EXP 0x10000000
940#define JME_TD_COLLISION 0x08000000
941#define JME_TD_UNDERRUN 0x04000000
942#define JME_TD_EHDR_SIZE_MASK 0x000000FF
943#define JME_TD_EHDR_SIZE_SHIFT 0
944
945#define JME_TD_SEG_CNT_MASK 0xFFFF0000
946#define JME_TD_SEG_CNT_SHIFT 16
947#define JME_TD_RETRY_CNT_MASK 0x0000FFFF
948#define JME_TD_RETRY_CNT_SHIFT 0
949
950#define JME_RD_OWN 0x80000000
951#define JME_RD_INTR 0x40000000
952#define JME_RD_64BIT 0x20000000
953
954#define JME_RD_BUF_LEN_MASK 0x0000FFFF
955#define JME_RD_BUF_LEN_SHIFT 0
956
957/*
958 * Only the first Rx descriptor of a packet is updated
959 * after packet reception.
960 */
961#define JME_RD_MORE_FRAG 0x20000000
962#define JME_RD_TCP 0x10000000
963#define JME_RD_UDP 0x08000000
964#define JME_RD_IPCSUM 0x04000000
965#define JME_RD_TCPCSUM 0x02000000
966#define JME_RD_UDPCSUM 0x01000000
967#define JME_RD_VLAN_TAG 0x00800000
968#define JME_RD_IPV4 0x00400000
969#define JME_RD_IPV6 0x00200000
970#define JME_RD_PAUSE 0x00100000
971#define JME_RD_MAGIC 0x00080000
972#define JME_RD_WAKEUP 0x00040000
973#define JME_RD_BCAST 0x00030000
974#define JME_RD_MCAST 0x00020000
975#define JME_RD_UCAST 0x00010000
976#define JME_RD_VLAN_MASK 0x0000FFFF
977#define JME_RD_VLAN_SHIFT 0
978
979#define JME_RD_VALID 0x80000000
980#define JME_RD_CNT_MASK 0x7F000000
981#define JME_RD_CNT_SHIFT 24
982#define JME_RD_GIANT 0x00800000
983#define JME_RD_GMII_ERR 0x00400000
984#define JME_RD_NBL_RCVD 0x00200000
985#define JME_RD_COLL 0x00100000
986#define JME_RD_ABORT 0x00080000
987#define JME_RD_RUNT 0x00040000
988#define JME_RD_FIFO_OVRN 0x00020000
989#define JME_RD_CRC_ERR 0x00010000
990#define JME_RD_FRAME_LEN_MASK 0x0000FFFF
991
992#define JME_RX_ERR_STAT \
993 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \
994 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \
995 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR)
996
997#define JME_RD_ERR_MASK 0x00FF0000
998#define JME_RD_ERR_SHIFT 16
999#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT)
1000#define JME_RX_ERR_BITS "\20" \
1001 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \
1002 "\5COLL\6NBLRCVD\7GMIIERR\10"
1003
1004#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT)
1005#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK)
1006#define JME_RX_PAD_BYTES 10
1007
1008#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF
1009
1010#define JME_RD_RSS_HASH_MASK 0x00003F00
1011#define JME_RD_RSS_HASH_SHIFT 8
1012#define JME_RD_RSS_HASH_NONE 0x00000000
1013#define JME_RD_RSS_HASH_IPV4 0x00000100
1014#define JME_RD_RSS_HASH_IPV4TCP 0x00000200
1015#define JME_RD_RSS_HASH_IPV6 0x00000400
1016#define JME_RD_RSS_HASH_IPV6TCP 0x00001000
1017#define JME_RD_HASH_FN_NONE 0x00000000
1018#define JME_RD_HASH_FN_TOEPLITZ 0x00000001
1019
1020#endif
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