1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2008
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 */
7
8#ifndef _KWBIMAGE_H_
9#define _KWBIMAGE_H_
10
11#include <compiler.h>
12#include <stdint.h>
13
14#ifdef __GNUC__
15#define __packed __attribute((packed))
16#else
17#define __packed
18#endif
19
20#define KWBIMAGE_MAX_CONFIG	((0x1dc - 0x20)/sizeof(struct reg_config))
21#define MAX_TEMPBUF_LEN		32
22
23/* NAND ECC Mode */
24#define IBR_HDR_ECC_DEFAULT		0x00
25#define IBR_HDR_ECC_FORCED_HAMMING	0x01
26#define IBR_HDR_ECC_FORCED_RS		0x02
27#define IBR_HDR_ECC_DISABLED		0x03
28
29/* Boot Type - block ID */
30#define IBR_HDR_I2C_ID			0x4D
31#define IBR_HDR_SPI_ID			0x5A
32#define IBR_HDR_NAND_ID			0x8B
33#define IBR_HDR_SATA_ID			0x78
34#define IBR_HDR_PEX_ID			0x9C
35#define IBR_HDR_UART_ID			0x69
36#define IBR_HDR_SDIO_ID			0xAE
37#define IBR_DEF_ATTRIB			0x00
38
39/* Structure of the main header, version 0 (Kirkwood, Dove) */
40struct main_hdr_v0 {
41	uint8_t  blockid;		/* 0x0       */
42	uint8_t  nandeccmode;		/* 0x1       */
43	uint16_t nandpagesize;		/* 0x2-0x3   */
44	uint32_t blocksize;		/* 0x4-0x7   */
45	uint8_t  version;		/* 0x8       */
46	uint8_t  rsvd1[3];		/* 0x9-0xB   */
47	uint32_t srcaddr;		/* 0xC-0xF   */
48	uint32_t destaddr;		/* 0x10-0x13 */
49	uint32_t execaddr;		/* 0x14-0x17 */
50	uint8_t  satapiomode;		/* 0x18      */
51	uint8_t  nandblocksize;		/* 0x19      */
52	union {
53	uint8_t  nandbadblklocation;    /* 0x1A      */
54	uint16_t ddrinitdelay;		/* 0x1A-0x1B */
55	};
56	uint8_t  rsvd2;			/* 0x1C      */
57	uint8_t  bin;			/* 0x1D      */
58	uint8_t  ext;			/* 0x1E      */
59	uint8_t  checksum;		/* 0x1F      */
60} __packed;
61
62struct ext_hdr_v0_reg {
63	uint32_t raddr;
64	uint32_t rdata;
65} __packed;
66
67/* Structure of the extension header, version 0 (Kirkwood, Dove) */
68struct ext_hdr_v0 {
69	/*
70	 * Beware that extension header offsets specified in 88AP510 Functional
71	 * Specifications are relative to the start of the main header, not to
72	 * the start of the extension header itself.
73	 */
74	uint32_t offset;		/* 0x0-0x3     */
75	uint8_t  rsvd1[8];		/* 0x4-0xB     */
76	uint32_t enddelay;		/* 0xC-0xF     */
77	uint32_t match_addr;		/* 0x10-0x13   */
78	uint32_t match_mask;		/* 0x14-0x17   */
79	uint32_t match_value;		/* 0x18-0x1B   */
80	uint8_t  ddrwritetype;		/* 0x1C        */
81	uint8_t  ddrresetmpp;		/* 0x1D        */
82	uint8_t  ddrclkenmpp;		/* 0x1E        */
83	uint8_t  ddrinitdelay;		/* 0x1F        */
84	struct ext_hdr_v0_reg rcfg[55]; /* 0x20-0x1D7  */
85	uint8_t  rsvd2[7];		/* 0x1D8-0x1DE */
86	uint8_t  checksum;		/* 0x1DF       */
87} __packed;
88
89/* Structure of the binary code header, version 0 (Dove) */
90struct bin_hdr_v0 {
91	uint32_t match_addr;		/* 0x00-0x03  */
92	uint32_t match_mask;		/* 0x04-0x07  */
93	uint32_t match_value;		/* 0x08-0x0B  */
94	uint32_t offset;		/* 0x0C-0x0F  */
95	uint32_t destaddr;		/* 0x10-0x13  */
96	uint32_t size;			/* 0x14-0x17  */
97	uint32_t execaddr;		/* 0x18-0x1B  */
98	uint32_t params[4];		/* 0x1C-0x2B  */
99	uint8_t  params_flags;		/* 0x2C       */
100	uint8_t  rsvd1;			/* 0x2D       */
101	uint8_t  rsvd2;			/* 0x2E       */
102	uint8_t  checksum;		/* 0x2F       */
103	uint8_t  code[2000];		/* 0x30-0x7FF */
104} __packed;
105
106/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
107struct main_hdr_v1 {
108	uint8_t  blockid;               /* 0x0       */
109	uint8_t  flags;                 /* 0x1       */
110	uint16_t nandpagesize;          /* 0x2-0x3   */
111	uint32_t blocksize;             /* 0x4-0x7   */
112	uint8_t  version;               /* 0x8       */
113	uint8_t  headersz_msb;          /* 0x9       */
114	uint16_t headersz_lsb;          /* 0xA-0xB   */
115	uint32_t srcaddr;               /* 0xC-0xF   */
116	uint32_t destaddr;              /* 0x10-0x13 */
117	uint32_t execaddr;              /* 0x14-0x17 */
118	uint8_t  options;               /* 0x18      */
119	uint8_t  nandblocksize;         /* 0x19      */
120	uint8_t  nandbadblklocation;    /* 0x1A      */
121	uint8_t  reserved4;             /* 0x1B      */
122	uint16_t reserved5;             /* 0x1C-0x1D */
123	uint8_t  ext;                   /* 0x1E      */
124	uint8_t  checksum;              /* 0x1F      */
125} __packed;
126
127/*
128 * Main header options
129 */
130#define MAIN_HDR_V1_OPT_BAUD_DEFAULT	0
131#define MAIN_HDR_V1_OPT_BAUD_2400	0x1
132#define MAIN_HDR_V1_OPT_BAUD_4800	0x2
133#define MAIN_HDR_V1_OPT_BAUD_9600	0x3
134#define MAIN_HDR_V1_OPT_BAUD_19200	0x4
135#define MAIN_HDR_V1_OPT_BAUD_38400	0x5
136#define MAIN_HDR_V1_OPT_BAUD_57600	0x6
137#define MAIN_HDR_V1_OPT_BAUD_115200	0x7
138
139/*
140 * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x)
141 */
142struct opt_hdr_v1 {
143	uint8_t  headertype;
144	uint8_t  headersz_msb;
145	uint16_t headersz_lsb;
146	char     data[0];
147} __packed;
148
149/*
150 * Public Key data in DER format
151 */
152struct pubkey_der_v1 {
153	uint8_t key[524];
154} __packed;
155
156/*
157 * Signature (RSA 2048)
158 */
159struct sig_v1 {
160	uint8_t sig[256];
161} __packed;
162
163/*
164 * Structure of secure header (Armada XP/375/38x/39x)
165 */
166struct secure_hdr_v1 {
167	uint8_t  headertype;		/* 0x0 */
168	uint8_t  headersz_msb;		/* 0x1 */
169	uint16_t headersz_lsb;		/* 0x2 - 0x3 */
170	uint32_t reserved1;		/* 0x4 - 0x7 */
171	struct pubkey_der_v1 kak;	/* 0x8 - 0x213 */
172	uint8_t  jtag_delay;		/* 0x214 */
173	uint8_t  reserved2;		/* 0x215 */
174	uint16_t reserved3;		/* 0x216 - 0x217 */
175	uint32_t boxid;			/* 0x218 - 0x21B */
176	uint32_t flashid;		/* 0x21C - 0x21F */
177	struct sig_v1 hdrsig;		/* 0x220 - 0x31F */
178	struct sig_v1 imgsig;		/* 0x320 - 0x41F */
179	struct pubkey_der_v1 csk[16];	/* 0x420 - 0x24DF */
180	struct sig_v1 csksig;		/* 0x24E0 - 0x25DF */
181	uint8_t  next;			/* 0x25E0 */
182	uint8_t  reserved4;		/* 0x25E1 */
183	uint16_t reserved5;		/* 0x25E2 - 0x25E3 */
184} __packed;
185
186/*
187 * Structure of register set
188 */
189struct register_set_hdr_v1 {
190	uint8_t  headertype;		/* 0x0 */
191	uint8_t  headersz_msb;		/* 0x1 */
192	uint16_t headersz_lsb;		/* 0x2 - 0x3 */
193	union {
194		struct {
195			uint32_t address;	/* 0x4+8*N - 0x7+8*N */
196			uint32_t value;		/* 0x8+8*N - 0xB+8*N */
197		} __packed entry;
198		struct {
199			uint8_t  next;		/* 0xC+8*N */
200			uint8_t  delay;		/* 0xD+8*N */
201			uint16_t reserved;	/* 0xE+8*N - 0xF+8*N */
202		} __packed last_entry;
203	} data[];
204} __packed;
205
206/*
207 * Value 0 in register_set_hdr_v1 delay field is special.
208 * Instead of delay it setup SDRAM Controller.
209 */
210#define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
211#define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
212
213/*
214 * Various values for the opt_hdr_v1->headertype field, describing the
215 * different types of optional headers. The "secure" header contains
216 * informations related to secure boot (encryption keys, etc.). The
217 * "binary" header contains ARM binary code to be executed prior to
218 * executing the main payload (usually the bootloader). This is
219 * typically used to execute DDR3 training code. The "register" header
220 * allows to describe a set of (address, value) tuples that are
221 * generally used to configure the DRAM controller.
222 */
223#define OPT_HDR_V1_SECURE_TYPE   0x1
224#define OPT_HDR_V1_BINARY_TYPE   0x2
225#define OPT_HDR_V1_REGISTER_TYPE 0x3
226
227/*
228 * Byte 8 of the image header contains the version number. In the v0
229 * header, byte 8 was reserved, and always set to 0. In the v1 header,
230 * byte 8 has been changed to a proper field, set to 1.
231 */
232static inline unsigned int kwbimage_version(const void *header)
233{
234	const unsigned char *ptr = header;
235	return ptr[8];
236}
237
238static inline size_t kwbheader_size(const void *header)
239{
240	if (kwbimage_version(header) == 0) {
241		const struct main_hdr_v0 *hdr = header;
242
243		/*
244		 * First extension header starts immediately after the main
245		 * header without any padding. Between extension headers is
246		 * 0x20 byte padding. There is no padding after the last
247		 * extension header. First binary code header starts immediately
248		 * after the last extension header (or immediately after the
249		 * main header if there is no extension header) without any
250		 * padding. There is no padding between binary code headers and
251		 * neither after the last binary code header.
252		 */
253		return sizeof(*hdr) +
254		       hdr->ext * sizeof(struct ext_hdr_v0) +
255		       ((hdr->ext > 1) ? ((hdr->ext - 1) * 0x20) : 0) +
256		       hdr->bin * sizeof(struct bin_hdr_v0);
257	} else {
258		const struct main_hdr_v1 *hdr = header;
259
260		return (hdr->headersz_msb << 16) |
261		       le16_to_cpu(hdr->headersz_lsb);
262	}
263}
264
265static inline size_t kwbheader_size_for_csum(const void *header)
266{
267	if (kwbimage_version(header) == 0)
268		return sizeof(struct main_hdr_v0);
269	else
270		return kwbheader_size(header);
271}
272
273static inline struct ext_hdr_v0 *ext_hdr_v0_first(void *img)
274{
275	struct main_hdr_v0 *mhdr;
276
277	if (kwbimage_version(img) != 0)
278		return NULL;
279
280	mhdr = img;
281	if (mhdr->ext)
282		return (struct ext_hdr_v0 *)(mhdr + 1);
283	else
284		return NULL;
285}
286
287static inline void *_ext_hdr_v0_end(struct main_hdr_v0 *mhdr)
288{
289	return (uint8_t *)mhdr + kwbheader_size(mhdr) - mhdr->bin * sizeof(struct bin_hdr_v0);
290}
291
292static inline struct ext_hdr_v0 *ext_hdr_v0_next(void *img, struct ext_hdr_v0 *cur)
293{
294	if ((void *)(cur + 1) < _ext_hdr_v0_end(img))
295		return (struct ext_hdr_v0 *)((uint8_t *)(cur + 1) + 0x20);
296	else
297		return NULL;
298}
299
300#define for_each_ext_hdr_v0(ehdr, img)			\
301	for ((ehdr) = ext_hdr_v0_first((img));		\
302	     (ehdr) != NULL;				\
303	     (ehdr) = ext_hdr_v0_next((img), (ehdr)))
304
305static inline struct bin_hdr_v0 *bin_hdr_v0_first(void *img)
306{
307	struct main_hdr_v0 *mhdr;
308
309	if (kwbimage_version(img) != 0)
310		return NULL;
311
312	mhdr = img;
313	if (mhdr->bin)
314		return _ext_hdr_v0_end(mhdr);
315	else
316		return NULL;
317}
318
319#define for_each_bin_hdr_v0(bhdr, img)							\
320	for ((bhdr) = bin_hdr_v0_first((img));						\
321	     (bhdr) && (void *)(bhdr) < (void *)((uint8_t *)img + kwbheader_size(img));	\
322	     (bhdr) = (struct bin_hdr_v0 *)((bhdr))+1)
323
324static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
325{
326	return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
327}
328
329static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr,
330					const void *mhdr_end)
331{
332	uint32_t ohdr_size;
333
334	if ((const void *)(ohdr + 1) > mhdr_end)
335		return 0;
336
337	ohdr_size = opt_hdr_v1_size(ohdr);
338	if (ohdr_size < 8 || (const void *)((const uint8_t *)ohdr + ohdr_size) > mhdr_end)
339		return 0;
340
341	return 1;
342}
343
344static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) {
345	struct main_hdr_v1 *mhdr;
346
347	if (kwbimage_version(img) != 1)
348		return NULL;
349
350	mhdr = img;
351	if (mhdr->ext)
352		return (struct opt_hdr_v1 *)(mhdr + 1);
353	else
354		return NULL;
355}
356
357static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur)
358{
359	uint32_t size = opt_hdr_v1_size(cur);
360
361	return (uint8_t *)cur + size - 4;
362}
363
364static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur)
365{
366	return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur));
367}
368
369static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur)
370{
371	if (*opt_hdr_v1_ext(cur))
372		return _opt_hdr_v1_next(cur);
373	else
374		return NULL;
375}
376
377#define for_each_opt_hdr_v1(ohdr, img)		\
378	for ((ohdr) = opt_hdr_v1_first((img));	\
379	     (ohdr) != NULL;			\
380	     (ohdr) = opt_hdr_v1_next((ohdr)))
381
382#endif /* _KWBIMAGE_H_ */
383