1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Defines APIs and structures that allow software to interact with a 4 * TPM2 device 5 * 6 * Copyright (c) 2020 Linaro 7 * Copyright (c) 2018 Bootlin 8 * 9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/ 10 * 11 * Author: Miquel Raynal <miquel.raynal@bootlin.com> 12 */ 13 14#ifndef __TPM_V2_H 15#define __TPM_V2_H 16 17#include <tpm-common.h> 18 19struct udevice; 20 21#define TPM2_DIGEST_LEN 32 22 23#define TPM2_SHA1_DIGEST_SIZE 20 24#define TPM2_SHA256_DIGEST_SIZE 32 25#define TPM2_SHA384_DIGEST_SIZE 48 26#define TPM2_SHA512_DIGEST_SIZE 64 27#define TPM2_SM3_256_DIGEST_SIZE 32 28 29#define TPM2_MAX_PCRS 32 30#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8) 31#define TPM2_MAX_CAP_BUFFER 1024 32#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \ 33 sizeof(u32)) / sizeof(struct tpms_tagged_property)) 34 35#define TPM2_HDR_LEN 10 36 37/* 38 * We deviate from this draft of the specification by increasing the value of 39 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2 40 * implementations that have enabled a larger than typical number of PCR 41 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included 42 * in a future revision of the specification. 43 */ 44#define TPM2_NUM_PCR_BANKS 16 45 46/* Definition of (UINT32) TPM2_CAP Constants */ 47#define TPM2_CAP_PCRS 0x00000005U 48#define TPM2_CAP_TPM_PROPERTIES 0x00000006U 49 50/* Definition of (UINT32) TPM2_PT Constants */ 51#define TPM2_PT_GROUP (u32)(0x00000100) 52#define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1) 53#define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5) 54#define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18) 55#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30) 56#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31) 57 58/* 59 * event types, cf. 60 * "TCG Server Management Domain Firmware Profile Specification", 61 * rev 1.00, 2020-05-01 62 */ 63#define EV_POST_CODE ((u32)0x00000001) 64#define EV_NO_ACTION ((u32)0x00000003) 65#define EV_SEPARATOR ((u32)0x00000004) 66#define EV_ACTION ((u32)0x00000005) 67#define EV_TAG ((u32)0x00000006) 68#define EV_S_CRTM_CONTENTS ((u32)0x00000007) 69#define EV_S_CRTM_VERSION ((u32)0x00000008) 70#define EV_CPU_MICROCODE ((u32)0x00000009) 71#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A) 72#define EV_TABLE_OF_DEVICES ((u32)0x0000000B) 73#define EV_COMPACT_HASH ((u32)0x0000000C) 74 75/* 76 * event types, cf. 77 * "TCG PC Client Platform Firmware Profile Specification", Family "2.0" 78 * Level 00 Version 1.05 Revision 23, May 7, 2021 79 */ 80#define EV_EFI_EVENT_BASE ((u32)0x80000000) 81#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001) 82#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002) 83#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003) 84#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004) 85#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005) 86#define EV_EFI_GPT_EVENT ((u32)0x80000006) 87#define EV_EFI_ACTION ((u32)0x80000007) 88#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008) 89#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009) 90#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A) 91#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B) 92#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C) 93#define EV_EFI_HCRTM_EVENT ((u32)0x80000010) 94#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0) 95#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1) 96#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2) 97 98#define EFI_CALLING_EFI_APPLICATION \ 99 "Calling EFI Application from Boot Option" 100#define EFI_RETURNING_FROM_EFI_APPLICATION \ 101 "Returning from EFI Application from Boot Option" 102#define EFI_EXIT_BOOT_SERVICES_INVOCATION \ 103 "Exit Boot Services Invocation" 104#define EFI_EXIT_BOOT_SERVICES_FAILED \ 105 "Exit Boot Services Returned with Failure" 106#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \ 107 "Exit Boot Services Returned with Success" 108#define EFI_DTB_EVENT_STRING \ 109 "DTB DATA" 110 111/* TPMS_TAGGED_PROPERTY Structure */ 112struct tpms_tagged_property { 113 u32 property; 114 u32 value; 115} __packed; 116 117/* TPMS_PCR_SELECTION Structure */ 118struct tpms_pcr_selection { 119 u16 hash; 120 u8 size_of_select; 121 u8 pcr_select[TPM2_PCR_SELECT_MAX]; 122} __packed; 123 124/* TPML_PCR_SELECTION Structure */ 125struct tpml_pcr_selection { 126 u32 count; 127 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS]; 128} __packed; 129 130/* TPML_TAGGED_TPM_PROPERTY Structure */ 131struct tpml_tagged_tpm_property { 132 u32 count; 133 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES]; 134} __packed; 135 136/* TPMU_CAPABILITIES Union */ 137union tpmu_capabilities { 138 /* 139 * Non exhaustive. Only added the structs needed for our 140 * current code 141 */ 142 struct tpml_pcr_selection assigned_pcr; 143 struct tpml_tagged_tpm_property tpm_properties; 144} __packed; 145 146/* TPMS_CAPABILITY_DATA Structure */ 147struct tpms_capability_data { 148 u32 capability; 149 union tpmu_capabilities data; 150} __packed; 151 152/** 153 * SHA1 Event Log Entry Format 154 * 155 * @pcr_index: PCRIndex event extended to 156 * @event_type: Type of event (see EFI specs) 157 * @digest: Value extended into PCR index 158 * @event_size: Size of event 159 * @event: Event data 160 */ 161struct tcg_pcr_event { 162 u32 pcr_index; 163 u32 event_type; 164 u8 digest[TPM2_SHA1_DIGEST_SIZE]; 165 u32 event_size; 166 u8 event[]; 167} __packed; 168 169/** 170 * Definition of TPMU_HA Union 171 */ 172union tpmu_ha { 173 u8 sha1[TPM2_SHA1_DIGEST_SIZE]; 174 u8 sha256[TPM2_SHA256_DIGEST_SIZE]; 175 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE]; 176 u8 sha384[TPM2_SHA384_DIGEST_SIZE]; 177 u8 sha512[TPM2_SHA512_DIGEST_SIZE]; 178} __packed; 179 180/** 181 * Definition of TPMT_HA Structure 182 * 183 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms 184 * @digest: Digest value for a given algorithm 185 */ 186struct tpmt_ha { 187 u16 hash_alg; 188 union tpmu_ha digest; 189} __packed; 190 191/** 192 * Definition of TPML_DIGEST_VALUES Structure 193 * 194 * @count: Number of algorithms supported by hardware 195 * @digests: struct for algorithm id and hash value 196 */ 197struct tpml_digest_values { 198 u32 count; 199 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS]; 200} __packed; 201 202/** 203 * Crypto Agile Log Entry Format 204 * 205 * @pcr_index: PCRIndex event extended to 206 * @event_type: Type of event 207 * @digests: List of digestsextended to PCR index 208 * @event_size: Size of the event data 209 * @event: Event data 210 */ 211struct tcg_pcr_event2 { 212 u32 pcr_index; 213 u32 event_type; 214 struct tpml_digest_values digests; 215 u32 event_size; 216 u8 event[]; 217} __packed; 218 219/** 220 * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information 221 * 222 * @algorithm_id: algorithm defined in enum tpm2_algorithms 223 * @digest_size: size of the algorithm 224 */ 225struct tcg_efi_spec_id_event_algorithm_size { 226 u16 algorithm_id; 227 u16 digest_size; 228} __packed; 229 230#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" 231#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2 232#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0 233#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2 234 235/** 236 * struct TCG_EfiSpecIDEventStruct - content of the event log header 237 * 238 * @signature: signature, set to Spec ID Event03 239 * @platform_class: class defined in TCG ACPI Specification 240 * Client Common Header. 241 * @spec_version_minor: minor version 242 * @spec_version_major: major version 243 * @spec_version_errata: major version 244 * @uintn_size: size of the efi_uintn_t fields used in various 245 * data structures used in this specification. 246 * 0x01 indicates u32 and 0x02 indicates u64 247 * @number_of_algorithms: hashing algorithms used in this event log 248 * @digest_sizes: array of number_of_algorithms pairs 249 * 1st member defines the algorithm id 250 * 2nd member defines the algorithm size 251 */ 252struct tcg_efi_spec_id_event { 253 u8 signature[16]; 254 u32 platform_class; 255 u8 spec_version_minor; 256 u8 spec_version_major; 257 u8 spec_errata; 258 u8 uintn_size; 259 u32 number_of_algorithms; 260 struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; 261} __packed; 262 263/** 264 * TPM2 Structure Tags for command/response buffers. 265 * 266 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication. 267 * @TPM2_ST_SESSIONS: the command needs an authentication. 268 */ 269enum tpm2_structures { 270 TPM2_ST_NO_SESSIONS = 0x8001, 271 TPM2_ST_SESSIONS = 0x8002, 272}; 273 274/** 275 * TPM2 type of boolean. 276 */ 277enum tpm2_yes_no { 278 TPMI_YES = 1, 279 TPMI_NO = 0, 280}; 281 282/** 283 * TPM2 startup values. 284 * 285 * @TPM2_SU_CLEAR: reset the internal state. 286 * @TPM2_SU_STATE: restore saved state (if any). 287 */ 288enum tpm2_startup_types { 289 TPM2_SU_CLEAR = 0x0000, 290 TPM2_SU_STATE = 0x0001, 291}; 292 293/** 294 * TPM2 permanent handles. 295 * 296 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy. 297 * @TPM2_RS_PW: indicates a password. 298 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy. 299 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy. 300 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy. 301 */ 302enum tpm2_handles { 303 TPM2_RH_OWNER = 0x40000001, 304 TPM2_RS_PW = 0x40000009, 305 TPM2_RH_LOCKOUT = 0x4000000A, 306 TPM2_RH_ENDORSEMENT = 0x4000000B, 307 TPM2_RH_PLATFORM = 0x4000000C, 308}; 309 310/** 311 * TPM2 command codes used at the beginning of a buffer, gives the command. 312 * 313 * @TPM2_CC_STARTUP: TPM2_Startup(). 314 * @TPM2_CC_SELF_TEST: TPM2_SelfTest(). 315 * @TPM2_CC_CLEAR: TPM2_Clear(). 316 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl(). 317 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth(). 318 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy(). 319 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset(). 320 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters(). 321 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility(). 322 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom(). 323 * @TPM2_CC_PCR_READ: TPM2_PCR_Read(). 324 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend(). 325 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue(). 326 */ 327enum tpm2_command_codes { 328 TPM2_CC_STARTUP = 0x0144, 329 TPM2_CC_SELF_TEST = 0x0143, 330 TPM2_CC_HIER_CONTROL = 0x0121, 331 TPM2_CC_CLEAR = 0x0126, 332 TPM2_CC_CLEARCONTROL = 0x0127, 333 TPM2_CC_HIERCHANGEAUTH = 0x0129, 334 TPM2_CC_NV_DEFINE_SPACE = 0x012a, 335 TPM2_CC_PCR_SETAUTHPOL = 0x012C, 336 TPM2_CC_NV_WRITE = 0x0137, 337 TPM2_CC_NV_WRITELOCK = 0x0138, 338 TPM2_CC_DAM_RESET = 0x0139, 339 TPM2_CC_DAM_PARAMETERS = 0x013A, 340 TPM2_CC_NV_READ = 0x014E, 341 TPM2_CC_GET_CAPABILITY = 0x017A, 342 TPM2_CC_GET_RANDOM = 0x017B, 343 TPM2_CC_PCR_READ = 0x017E, 344 TPM2_CC_PCR_EXTEND = 0x0182, 345 TPM2_CC_PCR_SETAUTHVAL = 0x0183, 346}; 347 348/** 349 * TPM2 return codes. 350 */ 351enum tpm2_return_codes { 352 TPM2_RC_SUCCESS = 0x0000, 353 TPM2_RC_BAD_TAG = 0x001E, 354 TPM2_RC_FMT1 = 0x0080, 355 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003, 356 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004, 357 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015, 358 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022, 359 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B, 360 TPM2_RC_VER1 = 0x0100, 361 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000, 362 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001, 363 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020, 364 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025, 365 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043, 366 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044, 367 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045, 368 TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c, 369 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053, 370 TPM2_RC_WARN = 0x0900, 371 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A, 372 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010, 373 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021, 374}; 375 376/** 377 * TPM2 algorithms. 378 */ 379enum tpm2_algorithms { 380 TPM2_ALG_SHA1 = 0x04, 381 TPM2_ALG_XOR = 0x0A, 382 TPM2_ALG_SHA256 = 0x0B, 383 TPM2_ALG_SHA384 = 0x0C, 384 TPM2_ALG_SHA512 = 0x0D, 385 TPM2_ALG_NULL = 0x10, 386 TPM2_ALG_SM3_256 = 0x12, 387}; 388 389extern const enum tpm2_algorithms tpm2_supported_algorithms[4]; 390 391static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a) 392{ 393 switch (a) { 394 case TPM2_ALG_SHA1: 395 return TPM2_SHA1_DIGEST_SIZE; 396 case TPM2_ALG_SHA256: 397 return TPM2_SHA256_DIGEST_SIZE; 398 case TPM2_ALG_SHA384: 399 return TPM2_SHA384_DIGEST_SIZE; 400 case TPM2_ALG_SHA512: 401 return TPM2_SHA512_DIGEST_SIZE; 402 default: 403 return 0; 404 } 405} 406 407#define tpm2_algorithm_to_mask(a) (1 << (a)) 408 409/* NV index attributes */ 410enum tpm_index_attrs { 411 TPMA_NV_PPWRITE = 1UL << 0, 412 TPMA_NV_OWNERWRITE = 1UL << 1, 413 TPMA_NV_AUTHWRITE = 1UL << 2, 414 TPMA_NV_POLICYWRITE = 1UL << 3, 415 TPMA_NV_COUNTER = 1UL << 4, 416 TPMA_NV_BITS = 1UL << 5, 417 TPMA_NV_EXTEND = 1UL << 6, 418 TPMA_NV_POLICY_DELETE = 1UL << 10, 419 TPMA_NV_WRITELOCKED = 1UL << 11, 420 TPMA_NV_WRITEALL = 1UL << 12, 421 TPMA_NV_WRITEDEFINE = 1UL << 13, 422 TPMA_NV_WRITE_STCLEAR = 1UL << 14, 423 TPMA_NV_GLOBALLOCK = 1UL << 15, 424 TPMA_NV_PPREAD = 1UL << 16, 425 TPMA_NV_OWNERREAD = 1UL << 17, 426 TPMA_NV_AUTHREAD = 1UL << 18, 427 TPMA_NV_POLICYREAD = 1UL << 19, 428 TPMA_NV_NO_DA = 1UL << 25, 429 TPMA_NV_ORDERLY = 1UL << 26, 430 TPMA_NV_CLEAR_STCLEAR = 1UL << 27, 431 TPMA_NV_READLOCKED = 1UL << 28, 432 TPMA_NV_WRITTEN = 1UL << 29, 433 TPMA_NV_PLATFORMCREATE = 1UL << 30, 434 TPMA_NV_READ_STCLEAR = 1UL << 31, 435 436 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD | 437 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD, 438 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE | 439 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE, 440}; 441 442enum { 443 TPM_ACCESS_VALID = 1 << 7, 444 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5, 445 TPM_ACCESS_REQUEST_PENDING = 1 << 2, 446 TPM_ACCESS_REQUEST_USE = 1 << 1, 447 TPM_ACCESS_ESTABLISHMENT = 1 << 0, 448}; 449 450enum { 451 TPM_STS_FAMILY_SHIFT = 26, 452 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT, 453 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT, 454 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25, 455 TPM_STS_COMMAND_CANCEL = 1 << 24, 456 TPM_STS_BURST_COUNT_SHIFT = 8, 457 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT, 458 TPM_STS_VALID = 1 << 7, 459 TPM_STS_COMMAND_READY = 1 << 6, 460 TPM_STS_GO = 1 << 5, 461 TPM_STS_DATA_AVAIL = 1 << 4, 462 TPM_STS_DATA_EXPECT = 1 << 3, 463 TPM_STS_SELF_TEST_DONE = 1 << 2, 464 TPM_STS_RESPONSE_RETRY = 1 << 1, 465 TPM_STS_READ_ZERO = 0x23 466}; 467 468enum { 469 TPM_CMD_COUNT_OFFSET = 2, 470 TPM_CMD_ORDINAL_OFFSET = 6, 471 TPM_MAX_BUF_SIZE = 1260, 472}; 473 474enum { 475 /* Secure storage for firmware settings */ 476 TPM_HT_PCR = 0, 477 TPM_HT_NV_INDEX, 478 TPM_HT_HMAC_SESSION, 479 TPM_HT_POLICY_SESSION, 480 481 HR_SHIFT = 24, 482 HR_PCR = TPM_HT_PCR << HR_SHIFT, 483 HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT, 484 HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT, 485 HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT, 486}; 487 488/** 489 * struct tcg2_event_log - Container for managing the platform event log 490 * 491 * @log: Address of the log 492 * @log_position: Current entry position 493 * @log_size: Log space available 494 * @found: Boolean indicating if an existing log was discovered 495 */ 496struct tcg2_event_log { 497 u8 *log; 498 u32 log_position; 499 u32 log_size; 500 bool found; 501}; 502 503/** 504 * Create a list of digests of the supported PCR banks for a given input data 505 * 506 * @dev TPM device 507 * @input Data 508 * @length Length of the data to calculate the digest 509 * @digest_list List of digests to fill in 510 * 511 * Return: zero on success, negative errno otherwise 512 */ 513int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, 514 struct tpml_digest_values *digest_list); 515 516/** 517 * Get the event size of the specified digests 518 * 519 * @digest_list List of digests for the event 520 * 521 * Return: Size in bytes of the event 522 */ 523u32 tcg2_event_get_size(struct tpml_digest_values *digest_list); 524 525/** 526 * tcg2_get_active_pcr_banks 527 * 528 * @dev TPM device 529 * @active_pcr_banks Bitmask of PCR algorithms supported 530 * 531 * Return: zero on success, negative errno otherwise 532 */ 533int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks); 534 535/** 536 * tcg2_log_append - Append an event to an event log 537 * 538 * @pcr_index Index of the PCR 539 * @event_type Type of event 540 * @digest_list List of digests to add 541 * @size Size of event 542 * @event Event data 543 * @log Log buffer to append the event to 544 */ 545void tcg2_log_append(u32 pcr_index, u32 event_type, 546 struct tpml_digest_values *digest_list, u32 size, 547 const u8 *event, u8 *log); 548 549/** 550 * Extend the PCR with specified digests 551 * 552 * @dev TPM device 553 * @pcr_index Index of the PCR 554 * @digest_list List of digests to extend 555 * 556 * Return: zero on success, negative errno otherwise 557 */ 558int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, 559 struct tpml_digest_values *digest_list); 560 561/** 562 * Read the PCR into a list of digests 563 * 564 * @dev TPM device 565 * @pcr_index Index of the PCR 566 * @digest_list List of digests to extend 567 * 568 * Return: zero on success, negative errno otherwise 569 */ 570int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, 571 struct tpml_digest_values *digest_list); 572 573/** 574 * Measure data into the TPM PCRs and the platform event log. 575 * 576 * @dev TPM device 577 * @log Platform event log 578 * @pcr_index Index of the PCR 579 * @size Size of the data or 0 for event only 580 * @data Pointer to the data or NULL for event only 581 * @event_type Event log type 582 * @event_size Size of the event 583 * @event Pointer to the event 584 * 585 * Return: zero on success, negative errno otherwise 586 */ 587int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, 588 u32 pcr_index, u32 size, const u8 *data, u32 event_type, 589 u32 event_size, const u8 *event); 590 591#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \ 592 tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \ 593 event) 594 595/** 596 * Prepare the event log buffer. This function tries to discover an existing 597 * event log in memory from a previous bootloader stage. If such a log exists 598 * and the PCRs are not extended, the log is "replayed" to extend the PCRs. 599 * If no log is discovered, create the log header. 600 * 601 * @dev TPM device 602 * @elog Platform event log. The log pointer and log_size 603 * members must be initialized to either 0 or to a valid 604 * memory region, in which case any existing log 605 * discovered will be copied to the specified memory 606 * region. 607 * @ignore_existing_log Boolean to indicate whether or not to ignore an 608 * existing platform log in memory 609 * 610 * Return: zero on success, negative errno otherwise 611 */ 612int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, 613 bool ignore_existing_log); 614 615/** 616 * Begin measurements. 617 * 618 * @dev TPM device 619 * @elog Platform event log. The log pointer and log_size 620 * members must be initialized to either 0 or to a valid 621 * memory region, in which case any existing log 622 * discovered will be copied to the specified memory 623 * region. 624 * @ignore_existing_log Boolean to indicate whether or not to ignore an 625 * existing platform log in memory 626 * 627 * Return: zero on success, negative errno otherwise 628 */ 629int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, 630 bool ignore_existing_log); 631 632/** 633 * Stop measurements and record separator events. 634 * 635 * @dev TPM device 636 * @elog Platform event log 637 * @error Boolean to indicate whether an error ocurred or not 638 */ 639void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, 640 bool error); 641 642/** 643 * Get the platform event log address and size. 644 * 645 * @dev TPM device 646 * @addr Address of the log 647 * @size Size of the log 648 * 649 * Return: zero on success, negative errno otherwise 650 */ 651int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size); 652 653/** 654 * Get the first TPM2 device found. 655 * 656 * @dev TPM device 657 * 658 * Return: zero on success, negative errno otherwise 659 */ 660int tcg2_platform_get_tpm2(struct udevice **dev); 661 662/** 663 * Platform-specific function for handling TPM startup errors 664 * 665 * @dev TPM device 666 * @rc The TPM response code 667 */ 668void tcg2_platform_startup_error(struct udevice *dev, int rc); 669 670/** 671 * Issue a TPM2_Startup command. 672 * 673 * @dev TPM device 674 * @mode TPM startup mode 675 * 676 * Return: code of the operation 677 */ 678u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode); 679 680/** 681 * Issue a TPM2_SelfTest command. 682 * 683 * @dev TPM device 684 * @full_test Asking to perform all tests or only the untested ones 685 * 686 * Return: code of the operation 687 */ 688u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test); 689 690/** 691 * Issue a TPM2_Clear command. 692 * 693 * @dev TPM device 694 * @handle Handle 695 * @pw Password 696 * @pw_sz Length of the password 697 * 698 * Return: code of the operation 699 */ 700u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw, 701 const ssize_t pw_sz); 702 703/** 704 * Issue a TPM_NV_DefineSpace command 705 * 706 * This allows a space to be defined with given attributes and policy 707 * 708 * @dev TPM device 709 * @space_index index of the area 710 * @space_size size of area in bytes 711 * @nv_attributes TPM_NV_ATTRIBUTES of the area 712 * @nv_policy policy to use 713 * @nv_policy_size size of the policy 714 * Return: return code of the operation 715 */ 716u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index, 717 size_t space_size, u32 nv_attributes, 718 const u8 *nv_policy, size_t nv_policy_size); 719 720/** 721 * Issue a TPM2_PCR_Extend command. 722 * 723 * @dev TPM device 724 * @index Index of the PCR 725 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms' 726 * @digest Value representing the event to be recorded 727 * @digest_len len of the hash 728 * 729 * Return: code of the operation 730 */ 731u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm, 732 const u8 *digest, u32 digest_len); 733 734/** 735 * Read data from the secure storage 736 * 737 * @dev TPM device 738 * @index Index of data to read 739 * @data Place to put data 740 * @count Number of bytes of data 741 * Return: code of the operation 742 */ 743u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count); 744 745/** 746 * Write data to the secure storage 747 * 748 * @dev TPM device 749 * @index Index of data to write 750 * @data Data to write 751 * @count Number of bytes of data 752 * Return: code of the operation 753 */ 754u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data, 755 u32 count); 756 757/** 758 * Issue a TPM2_PCR_Read command. 759 * 760 * @dev TPM device 761 * @idx Index of the PCR 762 * @idx_min_sz Minimum size in bytes of the pcrSelect array 763 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms' 764 * @data Output buffer for contents of the named PCR 765 * @digest_len len of the data 766 * @updates Optional out parameter: number of updates for this PCR 767 * 768 * Return: code of the operation 769 */ 770u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, 771 u16 algorithm, void *data, u32 digest_len, 772 unsigned int *updates); 773 774/** 775 * Issue a TPM2_GetCapability command. This implementation is limited 776 * to query property index that is 4-byte wide. 777 * 778 * @dev TPM device 779 * @capability Partition of capabilities 780 * @property Further definition of capability, limited to be 4 bytes wide 781 * @buf Output buffer for capability information 782 * @prop_count Size of output buffer 783 * 784 * Return: code of the operation 785 */ 786u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, 787 void *buf, size_t prop_count); 788 789/** 790 * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks 791 * 792 * @dev: TPM device 793 * @supported_pcr: bitmask with the algorithms supported 794 * @active_pcr: bitmask with the active algorithms 795 * @pcr_banks: number of PCR banks 796 * 797 * @return 0 on success, code of operation or negative errno on failure 798 */ 799int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, 800 u32 *pcr_banks); 801 802/** 803 * Issue a TPM2_DictionaryAttackLockReset command. 804 * 805 * @dev TPM device 806 * @pw Password 807 * @pw_sz Length of the password 808 * 809 * Return: code of the operation 810 */ 811u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz); 812 813/** 814 * Issue a TPM2_DictionaryAttackParameters command. 815 * 816 * @dev TPM device 817 * @pw Password 818 * @pw_sz Length of the password 819 * @max_tries Count of authorizations before lockout 820 * @recovery_time Time before decrementation of the failure count 821 * @lockout_recovery Time to wait after a lockout 822 * 823 * Return: code of the operation 824 */ 825u32 tpm2_dam_parameters(struct udevice *dev, const char *pw, 826 const ssize_t pw_sz, unsigned int max_tries, 827 unsigned int recovery_time, 828 unsigned int lockout_recovery); 829 830/** 831 * Issue a TPM2_HierarchyChangeAuth command. 832 * 833 * @dev TPM device 834 * @handle Handle 835 * @newpw New password 836 * @newpw_sz Length of the new password 837 * @oldpw Old password 838 * @oldpw_sz Length of the old password 839 * 840 * Return: code of the operation 841 */ 842int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw, 843 const ssize_t newpw_sz, const char *oldpw, 844 const ssize_t oldpw_sz); 845 846/** 847 * Issue a TPM_PCR_SetAuthPolicy command. 848 * 849 * @dev TPM device 850 * @pw Platform password 851 * @pw_sz Length of the password 852 * @index Index of the PCR 853 * @digest New key to access the PCR 854 * 855 * Return: code of the operation 856 */ 857u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw, 858 const ssize_t pw_sz, u32 index, const char *key); 859 860/** 861 * Issue a TPM_PCR_SetAuthValue command. 862 * 863 * @dev TPM device 864 * @pw Platform password 865 * @pw_sz Length of the password 866 * @index Index of the PCR 867 * @digest New key to access the PCR 868 * @key_sz Length of the new key 869 * 870 * Return: code of the operation 871 */ 872u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw, 873 const ssize_t pw_sz, u32 index, const char *key, 874 const ssize_t key_sz); 875 876/** 877 * Issue a TPM2_GetRandom command. 878 * 879 * @dev TPM device 880 * @param data output buffer for the random bytes 881 * @param count size of output buffer 882 * 883 * Return: return code of the operation 884 */ 885u32 tpm2_get_random(struct udevice *dev, void *data, u32 count); 886 887/** 888 * Lock data in the TPM 889 * 890 * Once locked the data cannot be written until after a reboot 891 * 892 * @dev TPM device 893 * @index Index of data to lock 894 * Return: code of the operation 895 */ 896u32 tpm2_write_lock(struct udevice *dev, u32 index); 897 898/** 899 * Disable access to any platform data 900 * 901 * This can be called to close off access to the firmware data in the data, 902 * before calling the kernel. 903 * 904 * @dev TPM device 905 * Return: code of the operation 906 */ 907u32 tpm2_disable_platform_hierarchy(struct udevice *dev); 908 909/** 910 * submit user specified data to the TPM and get response 911 * 912 * @dev TPM device 913 * @sendbuf: Buffer of the data to send 914 * @recvbuf: Buffer to save the response to 915 * @recv_size: Pointer to the size of the response buffer 916 * 917 * Return: code of the operation 918 */ 919u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf, 920 u8 *recvbuf, size_t *recv_size); 921 922/** 923 * tpm_cr50_report_state() - Report the Cr50 internal state 924 * 925 * @dev: TPM device 926 * @vendor_cmd: Vendor command number to send 927 * @vendor_subcmd: Vendor sub-command number to send 928 * @recvbuf: Buffer to save the response to 929 * @recv_size: Pointer to the size of the response buffer 930 * Return: result of the operation 931 */ 932u32 tpm2_report_state(struct udevice *dev, uint vendor_cmd, uint vendor_subcmd, 933 u8 *recvbuf, size_t *recv_size); 934 935/** 936 * tpm2_enable_nvcommits() - Tell TPM to commit NV data immediately 937 * 938 * For Chromium OS verified boot, we may reboot or reset at different times, 939 * possibly leaving non-volatile data unwritten by the TPM. 940 * 941 * This vendor command is used to indicate that non-volatile data should be 942 * written to its store immediately. 943 * 944 * @dev TPM device 945 * @vendor_cmd: Vendor command number to send 946 * @vendor_subcmd: Vendor sub-command number to send 947 * Return: result of the operation 948 */ 949u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, 950 uint vendor_subcmd); 951 952/** 953 * tpm2_auto_start() - start up the TPM and perform selftests. 954 * If a testable function has not been tested and is 955 * requested the TPM2 will return TPM_RC_NEEDS_TEST. 956 * 957 * @param dev TPM device 958 * Return: TPM2_RC_TESTING, if TPM2 self-test is in progress. 959 * TPM2_RC_SUCCESS, if testing of all functions is complete without 960 * functional failures. 961 * TPM2_RC_FAILURE, if any test failed. 962 * TPM2_RC_INITIALIZE, if the TPM has not gone through the Startup 963 * sequence 964 965 */ 966u32 tpm2_auto_start(struct udevice *dev); 967 968#endif /* __TPM_V2_H */ 969