1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8#ifndef __LINUX_MTD_SPINAND_H 9#define __LINUX_MTD_SPINAND_H 10 11#ifndef __UBOOT__ 12#include <linux/mutex.h> 13#include <linux/bitops.h> 14#include <linux/device.h> 15#include <linux/mtd/mtd.h> 16#include <linux/mtd/nand.h> 17#include <linux/spi/spi.h> 18#include <linux/spi/spi-mem.h> 19#else 20#include <spi.h> 21#include <spi-mem.h> 22#include <linux/mtd/nand.h> 23#endif 24 25/** 26 * Standard SPI NAND flash operations 27 */ 28 29#define SPINAND_RESET_OP \ 30 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 31 SPI_MEM_OP_NO_ADDR, \ 32 SPI_MEM_OP_NO_DUMMY, \ 33 SPI_MEM_OP_NO_DATA) 34 35#define SPINAND_WR_EN_DIS_OP(enable) \ 36 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 37 SPI_MEM_OP_NO_ADDR, \ 38 SPI_MEM_OP_NO_DUMMY, \ 39 SPI_MEM_OP_NO_DATA) 40 41#define SPINAND_READID_OP(naddr, ndummy, buf, len) \ 42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 43 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 44 SPI_MEM_OP_DUMMY(ndummy, 1), \ 45 SPI_MEM_OP_DATA_IN(len, buf, 1)) 46 47#define SPINAND_SET_FEATURE_OP(reg, valptr) \ 48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 49 SPI_MEM_OP_ADDR(1, reg, 1), \ 50 SPI_MEM_OP_NO_DUMMY, \ 51 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 52 53#define SPINAND_GET_FEATURE_OP(reg, valptr) \ 54 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 55 SPI_MEM_OP_ADDR(1, reg, 1), \ 56 SPI_MEM_OP_NO_DUMMY, \ 57 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 58 59#define SPINAND_BLK_ERASE_OP(addr) \ 60 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 61 SPI_MEM_OP_ADDR(3, addr, 1), \ 62 SPI_MEM_OP_NO_DUMMY, \ 63 SPI_MEM_OP_NO_DATA) 64 65#define SPINAND_PAGE_READ_OP(addr) \ 66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 67 SPI_MEM_OP_ADDR(3, addr, 1), \ 68 SPI_MEM_OP_NO_DUMMY, \ 69 SPI_MEM_OP_NO_DATA) 70 71#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \ 72 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 73 SPI_MEM_OP_ADDR(2, addr, 1), \ 74 SPI_MEM_OP_DUMMY(ndummy, 1), \ 75 SPI_MEM_OP_DATA_IN(len, buf, 1)) 76 77#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \ 78 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 79 SPI_MEM_OP_ADDR(3, addr, 1), \ 80 SPI_MEM_OP_DUMMY(ndummy, 1), \ 81 SPI_MEM_OP_DATA_IN(len, buf, 1)) 82 83#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ 84 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 85 SPI_MEM_OP_ADDR(2, addr, 1), \ 86 SPI_MEM_OP_DUMMY(ndummy, 1), \ 87 SPI_MEM_OP_DATA_IN(len, buf, 2)) 88 89#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ 90 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 91 SPI_MEM_OP_ADDR(3, addr, 1), \ 92 SPI_MEM_OP_DUMMY(ndummy, 1), \ 93 SPI_MEM_OP_DATA_IN(len, buf, 2)) 94 95#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ 96 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 97 SPI_MEM_OP_ADDR(2, addr, 1), \ 98 SPI_MEM_OP_DUMMY(ndummy, 1), \ 99 SPI_MEM_OP_DATA_IN(len, buf, 4)) 100 101#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ 102 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 103 SPI_MEM_OP_ADDR(3, addr, 1), \ 104 SPI_MEM_OP_DUMMY(ndummy, 1), \ 105 SPI_MEM_OP_DATA_IN(len, buf, 4)) 106 107#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ 108 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 109 SPI_MEM_OP_ADDR(2, addr, 2), \ 110 SPI_MEM_OP_DUMMY(ndummy, 2), \ 111 SPI_MEM_OP_DATA_IN(len, buf, 2)) 112 113#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \ 114 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 115 SPI_MEM_OP_ADDR(3, addr, 2), \ 116 SPI_MEM_OP_DUMMY(ndummy, 2), \ 117 SPI_MEM_OP_DATA_IN(len, buf, 2)) 118 119#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ 120 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 121 SPI_MEM_OP_ADDR(2, addr, 4), \ 122 SPI_MEM_OP_DUMMY(ndummy, 4), \ 123 SPI_MEM_OP_DATA_IN(len, buf, 4)) 124 125#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \ 126 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 127 SPI_MEM_OP_ADDR(3, addr, 4), \ 128 SPI_MEM_OP_DUMMY(ndummy, 4), \ 129 SPI_MEM_OP_DATA_IN(len, buf, 4)) 130 131#define SPINAND_PROG_EXEC_OP(addr) \ 132 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 133 SPI_MEM_OP_ADDR(3, addr, 1), \ 134 SPI_MEM_OP_NO_DUMMY, \ 135 SPI_MEM_OP_NO_DATA) 136 137#define SPINAND_PROG_LOAD(reset, addr, buf, len) \ 138 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 139 SPI_MEM_OP_ADDR(2, addr, 1), \ 140 SPI_MEM_OP_NO_DUMMY, \ 141 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 142 143#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \ 144 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 145 SPI_MEM_OP_ADDR(2, addr, 1), \ 146 SPI_MEM_OP_NO_DUMMY, \ 147 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 148 149/** 150 * Standard SPI NAND flash commands 151 */ 152#define SPINAND_CMD_PROG_LOAD_X4 0x32 153#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 154 155/* feature register */ 156#define REG_BLOCK_LOCK 0xa0 157#define BL_ALL_UNLOCKED 0x00 158 159/* configuration register */ 160#define REG_CFG 0xb0 161#define CFG_OTP_ENABLE BIT(6) 162#define CFG_ECC_ENABLE BIT(4) 163#define CFG_QUAD_ENABLE BIT(0) 164 165/* status register */ 166#define REG_STATUS 0xc0 167#define STATUS_BUSY BIT(0) 168#define STATUS_ERASE_FAILED BIT(2) 169#define STATUS_PROG_FAILED BIT(3) 170#define STATUS_ECC_MASK GENMASK(5, 4) 171#define STATUS_ECC_NO_BITFLIPS (0 << 4) 172#define STATUS_ECC_HAS_BITFLIPS (1 << 4) 173#define STATUS_ECC_UNCOR_ERROR (2 << 4) 174 175struct spinand_op; 176struct spinand_device; 177 178#define SPINAND_MAX_ID_LEN 4 179 180/** 181 * struct spinand_id - SPI NAND id structure 182 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 183 * be extended if required 184 * @len: ID length 185 */ 186struct spinand_id { 187 u8 data[SPINAND_MAX_ID_LEN]; 188 int len; 189}; 190 191enum spinand_readid_method { 192 SPINAND_READID_METHOD_OPCODE, 193 SPINAND_READID_METHOD_OPCODE_ADDR, 194 SPINAND_READID_METHOD_OPCODE_DUMMY, 195}; 196 197/** 198 * struct spinand_devid - SPI NAND device id structure 199 * @id: device id of current chip 200 * @len: number of bytes in device id 201 * @method: method to read chip id 202 * There are 3 possible variants: 203 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 204 * after read_id opcode. 205 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 206 * read_id opcode + 1-byte address. 207 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 208 * read_id opcode + 1 dummy byte. 209 */ 210struct spinand_devid { 211 const u8 *id; 212 const u8 len; 213 const enum spinand_readid_method method; 214}; 215 216/** 217 * struct manufacurer_ops - SPI NAND manufacturer specific operations 218 * @init: initialize a SPI NAND device 219 * @cleanup: cleanup a SPI NAND device 220 * 221 * Each SPI NAND manufacturer driver should implement this interface so that 222 * NAND chips coming from this vendor can be initialized properly. 223 */ 224struct spinand_manufacturer_ops { 225 int (*init)(struct spinand_device *spinand); 226 void (*cleanup)(struct spinand_device *spinand); 227}; 228 229/** 230 * struct spinand_manufacturer - SPI NAND manufacturer instance 231 * @id: manufacturer ID 232 * @name: manufacturer name 233 * @devid_len: number of bytes in device ID 234 * @chips: supported SPI NANDs under current manufacturer 235 * @nchips: number of SPI NANDs available in chips array 236 * @ops: manufacturer operations 237 */ 238struct spinand_manufacturer { 239 u8 id; 240 char *name; 241 const struct spinand_info *chips; 242 const size_t nchips; 243 const struct spinand_manufacturer_ops *ops; 244}; 245 246/* SPI NAND manufacturers */ 247extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 248extern const struct spinand_manufacturer macronix_spinand_manufacturer; 249extern const struct spinand_manufacturer micron_spinand_manufacturer; 250extern const struct spinand_manufacturer paragon_spinand_manufacturer; 251extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 252extern const struct spinand_manufacturer winbond_spinand_manufacturer; 253extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; 254extern const struct spinand_manufacturer xtx_spinand_manufacturer; 255 256/** 257 * struct spinand_op_variants - SPI NAND operation variants 258 * @ops: the list of variants for a given operation 259 * @nops: the number of variants 260 * 261 * Some operations like read-from-cache/write-to-cache have several variants 262 * depending on the number of IO lines you use to transfer data or address 263 * cycles. This structure is a way to describe the different variants supported 264 * by a chip and let the core pick the best one based on the SPI mem controller 265 * capabilities. 266 */ 267struct spinand_op_variants { 268 const struct spi_mem_op *ops; 269 unsigned int nops; 270}; 271 272#define SPINAND_OP_VARIANTS(name, ...) \ 273 const struct spinand_op_variants name = { \ 274 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 275 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 276 sizeof(struct spi_mem_op), \ 277 } 278 279/** 280 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 281 * chip 282 * @get_status: get the ECC status. Should return a positive number encoding 283 * the number of corrected bitflips if correction was possible or 284 * -EBADMSG if there are uncorrectable errors. I can also return 285 * other negative error codes if the error is not caused by 286 * uncorrectable bitflips 287 * @ooblayout: the OOB layout used by the on-die ECC implementation 288 */ 289struct spinand_ecc_info { 290 int (*get_status)(struct spinand_device *spinand, u8 status); 291 const struct mtd_ooblayout_ops *ooblayout; 292}; 293 294#define SPINAND_HAS_QE_BIT BIT(0) 295#define SPINAND_HAS_CR_FEAT_BIT BIT(1) 296 297/** 298 * struct spinand_info - Structure used to describe SPI NAND chips 299 * @model: model name 300 * @devid: device ID 301 * @flags: OR-ing of the SPINAND_XXX flags 302 * @memorg: memory organization 303 * @eccreq: ECC requirements 304 * @eccinfo: on-die ECC info 305 * @op_variants: operations variants 306 * @op_variants.read_cache: variants of the read-cache operation 307 * @op_variants.write_cache: variants of the write-cache operation 308 * @op_variants.update_cache: variants of the update-cache operation 309 * @select_target: function used to select a target/die. Required only for 310 * multi-die chips 311 * 312 * Each SPI NAND manufacturer driver should have a spinand_info table 313 * describing all the chips supported by the driver. 314 */ 315struct spinand_info { 316 const char *model; 317 struct spinand_devid devid; 318 u32 flags; 319 struct nand_memory_organization memorg; 320 struct nand_ecc_req eccreq; 321 struct spinand_ecc_info eccinfo; 322 struct { 323 const struct spinand_op_variants *read_cache; 324 const struct spinand_op_variants *write_cache; 325 const struct spinand_op_variants *update_cache; 326 } op_variants; 327 int (*select_target)(struct spinand_device *spinand, 328 unsigned int target); 329}; 330 331#define SPINAND_ID(__method, ...) \ 332 { \ 333 .id = (const u8[]){ __VA_ARGS__ }, \ 334 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 335 .method = __method, \ 336 } 337 338#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 339 { \ 340 .read_cache = __read, \ 341 .write_cache = __write, \ 342 .update_cache = __update, \ 343 } 344 345#define SPINAND_ECCINFO(__ooblayout, __get_status) \ 346 .eccinfo = { \ 347 .ooblayout = __ooblayout, \ 348 .get_status = __get_status, \ 349 } 350 351#define SPINAND_SELECT_TARGET(__func) \ 352 .select_target = __func, 353 354#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 355 __flags, ...) \ 356 { \ 357 .model = __model, \ 358 .devid = __id, \ 359 .memorg = __memorg, \ 360 .eccreq = __eccreq, \ 361 .op_variants = __op_variants, \ 362 .flags = __flags, \ 363 __VA_ARGS__ \ 364 } 365 366/** 367 * struct spinand_device - SPI NAND device instance 368 * @base: NAND device instance 369 * @slave: pointer to the SPI slave object 370 * @lock: lock used to serialize accesses to the NAND 371 * @id: NAND ID as returned by READ_ID 372 * @flags: NAND flags 373 * @op_templates: various SPI mem op templates 374 * @op_templates.read_cache: read cache op template 375 * @op_templates.write_cache: write cache op template 376 * @op_templates.update_cache: update cache op template 377 * @select_target: select a specific target/die. Usually called before sending 378 * a command addressing a page or an eraseblock embedded in 379 * this die. Only required if your chip exposes several dies 380 * @cur_target: currently selected target/die 381 * @eccinfo: on-die ECC information 382 * @cfg_cache: config register cache. One entry per die 383 * @databuf: bounce buffer for data 384 * @oobbuf: bounce buffer for OOB data 385 * @scratchbuf: buffer used for everything but page accesses. This is needed 386 * because the spi-mem interface explicitly requests that buffers 387 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 388 * the stack 389 * @manufacturer: SPI NAND manufacturer information 390 * @priv: manufacturer private data 391 */ 392struct spinand_device { 393 struct nand_device base; 394#ifndef __UBOOT__ 395 struct spi_mem *spimem; 396 struct mutex lock; 397#else 398 struct spi_slave *slave; 399#endif 400 struct spinand_id id; 401 u32 flags; 402 403 struct { 404 const struct spi_mem_op *read_cache; 405 const struct spi_mem_op *write_cache; 406 const struct spi_mem_op *update_cache; 407 } op_templates; 408 409 int (*select_target)(struct spinand_device *spinand, 410 unsigned int target); 411 unsigned int cur_target; 412 413 struct spinand_ecc_info eccinfo; 414 415 u8 *cfg_cache; 416 u8 *databuf; 417 u8 *oobbuf; 418 u8 *scratchbuf; 419 const struct spinand_manufacturer *manufacturer; 420 void *priv; 421}; 422 423/** 424 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 425 * @mtd: MTD instance 426 * 427 * Return: the SPI NAND device attached to @mtd. 428 */ 429static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 430{ 431 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 432} 433 434/** 435 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 436 * @spinand: SPI NAND device 437 * 438 * Return: the MTD device embedded in @spinand. 439 */ 440static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 441{ 442 return nanddev_to_mtd(&spinand->base); 443} 444 445/** 446 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 447 * @nand: NAND object 448 * 449 * Return: the SPI NAND device embedding @nand. 450 */ 451static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 452{ 453 return container_of(nand, struct spinand_device, base); 454} 455 456/** 457 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 458 * @spinand: SPI NAND device 459 * 460 * Return: the NAND device embedded in @spinand. 461 */ 462static inline struct nand_device * 463spinand_to_nand(struct spinand_device *spinand) 464{ 465 return &spinand->base; 466} 467 468#ifndef __UBOOT__ 469/** 470 * spinand_set_of_node - Attach a DT node to a SPI NAND device 471 * @spinand: SPI NAND device 472 * @np: DT node 473 * 474 * Attach a DT node to a SPI NAND device. 475 */ 476static inline void spinand_set_of_node(struct spinand_device *spinand, 477 const struct device_node *np) 478{ 479 nanddev_set_of_node(&spinand->base, np); 480} 481#else 482/** 483 * spinand_set_of_node - Attach a DT node to a SPI NAND device 484 * @spinand: SPI NAND device 485 * @node: ofnode 486 * 487 * Attach a DT node to a SPI NAND device. 488 */ 489static inline void spinand_set_ofnode(struct spinand_device *spinand, 490 ofnode node) 491{ 492 nanddev_set_ofnode(&spinand->base, node); 493} 494#endif /* __UBOOT__ */ 495 496int spinand_match_and_init(struct spinand_device *spinand, 497 const struct spinand_info *table, 498 unsigned int table_size, 499 enum spinand_readid_method rdid_method); 500 501int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 502int spinand_select_target(struct spinand_device *spinand, unsigned int target); 503 504#endif /* __LINUX_MTD_SPINAND_H */ 505