1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Porting to U-Boot:
4 *
5 * (C) Copyright 2010
6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 *
8 * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
9 *
10 * Lattice Semiconductor Corp. Copyright 2009
11 */
12
13#ifndef _VME_OPCODE_H
14#define _VME_OPCODE_H
15
16#define VME_VERSION_NUMBER "12.1"
17
18/* Maximum declarations. */
19
20#define VMEHEXMAX	60000L	/* The hex file is split 60K per file. */
21#define SCANMAX		64000L	/* The maximum SDR/SIR burst. */
22
23/*
24 *
25 * Supported JTAG state transitions.
26 *
27 */
28
29#define RESET		0x00
30#define IDLE		0x01
31#define IRPAUSE		0x02
32#define DRPAUSE		0x03
33#define SHIFTIR		0x04
34#define SHIFTDR		0x05
35/* 11/15/05 Nguyen changed to support DRCAPTURE*/
36#define DRCAPTURE	0x06
37
38/*
39 * Flow control register bit definitions.  A set bit indicates
40 * that the register currently exhibits the corresponding mode.
41 */
42
43#define INTEL_PRGM	0x0001	/* Intelligent programming is in effect. */
44#define CASCADE		0x0002	/* Currently splitting large SDR. */
45#define REPEATLOOP	0x0008	/* Currently executing a repeat loop. */
46#define SHIFTRIGHT	0x0080	/* The next data stream needs a right shift. */
47#define SHIFTLEFT	0x0100	/* The next data stream needs a left shift. */
48#define VERIFYUES	0x0200	/* Continue if fail is in effect. */
49
50/*
51 * DataType register bit definitions.  A set bit indicates
52 * that the register currently holds the corresponding type of data.
53 */
54
55#define EXPRESS		0x0001    /* Simultaneous program and verify. */
56#define SIR_DATA	0x0002    /* SIR is the active SVF command. */
57#define SDR_DATA	0x0004    /* SDR is the active SVF command. */
58#define COMPRESS	0x0008    /* Data is compressed. */
59#define TDI_DATA	0x0010    /* TDI data is present. */
60#define TDO_DATA	0x0020    /* TDO data is present. */
61#define MASK_DATA	0x0040    /* MASK data is present. */
62#define HEAP_IN		0x0080    /* Data is from the heap. */
63#define LHEAP_IN	0x0200    /* Data is from intel data buffer. */
64#define VARIABLE	0x0400    /* Data is from a declared variable. */
65#define CRC_DATA	0x0800	 /* CRC data is pressent. */
66#define CMASK_DATA	0x1000    /* CMASK data is pressent. */
67#define RMASK_DATA	0x2000	 /* RMASK data is pressent. */
68#define READ_DATA	0x4000    /* READ data is pressent. */
69#define DMASK_DATA	0x8000	 /* DMASK data is pressent. */
70
71/*
72 *
73 * Pin opcodes.
74 *
75 */
76
77#define signalENABLE	0x1C    /* ispENABLE pin. */
78#define signalTMS	0x1D    /* TMS pin. */
79#define signalTCK	0x1E    /* TCK pin. */
80#define signalTDI	0x1F    /* TDI pin. */
81#define signalTRST	0x20    /* TRST pin. */
82
83/*
84 *
85 * Supported vendors.
86 *
87 */
88
89#define VENDOR		0x56
90#define LATTICE		0x01
91#define ALTERA		0x02
92#define XILINX		0x03
93
94/*
95 * Opcode definitions.
96 *
97 * Note: opcodes must be unique.
98 */
99
100#define ENDDATA		0x00	/* The end of the current SDR data stream. */
101#define RUNTEST		0x01	/* The duration to stay at the stable state. */
102#define ENDDR		0x02	/* The stable state after SDR. */
103#define ENDIR		0x03	/* The stable state after SIR. */
104#define ENDSTATE	0x04	/* The stable state after RUNTEST. */
105#define TRST		0x05	/* Assert the TRST pin. */
106#define HIR		0x06	/*
107				 * The sum of the IR bits of the
108				 * leading devices.
109				 */
110#define TIR		0x07	/*
111				 * The sum of the IR bits of the trailing
112				 * devices.
113				 */
114#define HDR		0x08	/* The number of leading devices. */
115#define TDR		0x09	/* The number of trailing devices. */
116#define ispEN		0x0A	/* Assert the ispEN pin. */
117#define FREQUENCY	0x0B	/*
118				 * The maximum clock rate to run the JTAG state
119				 * machine.
120				 */
121#define STATE		0x10	/* Move to the next stable state. */
122#define SIR		0x11	/* The instruction stream follows. */
123#define SDR		0x12	/* The data stream follows. */
124#define TDI		0x13	/* The following data stream feeds into
125					the device. */
126#define TDO		0x14	/*
127				 * The following data stream is compared against
128				 * the device.
129				 */
130#define MASK		0x15	/* The following data stream is used as mask. */
131#define XSDR		0x16	/*
132				 * The following data stream is for simultaneous
133				 * program and verify.
134				 */
135#define XTDI		0x17	/* The following data stream is for shift in
136				 * only. It must be stored for the next
137				 * XSDR.
138				 */
139#define XTDO		0x18	/*
140				 * There is not data stream.  The data stream
141				 * was stored from the previous XTDI.
142				 */
143#define MEM		0x19	/*
144				 * The maximum memory needed to allocate in
145				 * order hold one row of data.
146				 */
147#define WAIT		0x1A	/* The duration of delay to observe. */
148#define TCK		0x1B	/* The number of TCK pulses. */
149#define SHR		0x23	/*
150				 * Set the flow control register for
151				 * right shift
152				 */
153#define SHL		0x24	/*
154				 * Set the flow control register for left shift.
155				 */
156#define HEAP		0x32	/* The memory size needed to hold one loop. */
157#define REPEAT		0x33	/* The beginning of the loop. */
158#define LEFTPAREN	0x35	/* The beginning of data following the loop. */
159#define VAR		0x55	/* Plac holder for loop data. */
160#define SEC		0x1C	/*
161				 * The delay time in seconds that must be
162				 * observed.
163				 */
164#define SMASK		0x1D	/* The mask for TDI data. */
165#define MAX_WAIT	0x1E	/* The absolute maximum wait time. */
166#define ON		0x1F	/* Assert the targeted pin. */
167#define OFF		0x20	/* Dis-assert the targeted pin. */
168#define SETFLOW		0x30	/* Change the flow control register. */
169#define RESETFLOW	0x31	/* Clear the flow control register. */
170
171#define CRC		0x47	/*
172				 * The following data stream is used for CRC
173				 * calculation.
174				 */
175#define CMASK		0x48	/*
176				 * The following data stream is used as mask
177				 * for CRC calculation.
178				 */
179#define RMASK		0x49	/*
180				 * The following data stream is used as mask
181				 * for read and save.
182				 */
183#define READ		0x50	/*
184				 * The following data stream is used for read
185				 * and save.
186				 */
187#define ENDLOOP		0x59	/* The end of the repeat loop. */
188#define SECUREHEAP	0x60	/* Used to secure the HEAP opcode. */
189#define VUES		0x61	/* Support continue if fail. */
190#define DMASK		0x62	/*
191				 * The following data stream is used for dynamic
192				 * I/O.
193				 */
194#define COMMENT		0x63	/* Support SVF comments in the VME file. */
195#define HEADER		0x64	/* Support header in VME file. */
196#define FILE_CRC	0x65	/* Support crc-protected VME file. */
197#define LCOUNT		0x66	/* Support intelligent programming. */
198#define LDELAY		0x67	/* Support intelligent programming. */
199#define LSDR		0x68	/* Support intelligent programming. */
200#define LHEAP		0x69	/*
201				 * Memory needed to hold intelligent data
202				 * buffer
203				 */
204#define CONTINUE	0x70	/* Allow continuation. */
205#define LVDS		0x71	/* Support LVDS. */
206#define ENDVME		0x7F	/* End of the VME file. */
207#define ENDFILE		0xFF	/* End of file. */
208
209/*
210 *
211 * ispVM Embedded Return Codes.
212 *
213 */
214
215#define VME_VERIFICATION_FAILURE	-1
216#define VME_FILE_READ_FAILURE		-2
217#define VME_VERSION_FAILURE		-3
218#define VME_INVALID_FILE		-4
219#define VME_ARGUMENT_FAILURE		-5
220#define VME_CRC_FAILURE			-6
221
222#define g_ucPinTDI	0x01
223#define g_ucPinTCK	0x02
224#define g_ucPinTMS	0x04
225#define g_ucPinENABLE	0x08
226#define g_ucPinTRST	0x10
227
228/*
229 *
230 * Type definitions.
231 *
232 */
233
234/* Support LVDS */
235typedef struct {
236	unsigned short usPositiveIndex;
237	unsigned short usNegativeIndex;
238	unsigned char  ucUpdate;
239} LVDSPair;
240
241typedef enum {
242	min_lattice_iface_type,		/* insert all new types after this */
243	lattice_jtag_mode,		/* jtag/tap  */
244	max_lattice_iface_type		/* insert all new types before this */
245} Lattice_iface;
246
247typedef enum {
248	min_lattice_type,
249	Lattice_XP2,			/* Lattice XP2 Family */
250	max_lattice_type		/* insert all new types before this */
251} Lattice_Family;
252
253typedef struct {
254	Lattice_Family	family;	/* part type */
255	Lattice_iface	iface;	/* interface type */
256	size_t		size;	/* bytes of data part can accept */
257	void		*iface_fns; /* interface function table */
258	void		*base;	/* base interface address */
259	int		cookie;	/* implementation specific cookie */
260	char		*desc;	/* description string */
261} Lattice_desc;			/* end, typedef Altera_desc */
262
263/* Board specific implementation specific function types */
264typedef void (*Lattice_jtag_init)(void);
265typedef void (*Lattice_jtag_set_tdi)(int v);
266typedef void (*Lattice_jtag_set_tms)(int v);
267typedef void (*Lattice_jtag_set_tck)(int v);
268typedef int (*Lattice_jtag_get_tdo)(void);
269
270typedef struct {
271	Lattice_jtag_init	jtag_init;
272	Lattice_jtag_set_tdi	jtag_set_tdi;
273	Lattice_jtag_set_tms	jtag_set_tms;
274	Lattice_jtag_set_tck	jtag_set_tck;
275	Lattice_jtag_get_tdo	jtag_get_tdo;
276} lattice_board_specific_func;
277
278void writePort(unsigned char pins, unsigned char value);
279unsigned char readPort(void);
280void sclock(void);
281void ispVMDelay(unsigned short int a_usMicroSecondDelay);
282void calibration(void);
283
284int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize);
285int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize);
286int lattice_info(Lattice_desc *desc);
287
288void ispVMStart(void);
289void ispVMEnd(void);
290extern void ispVMFreeMem(void);
291signed char ispVMCode(void);
292void ispVMDelay(unsigned short int a_usMicroSecondDelay);
293void ispVMCalculateCRC32(unsigned char a_ucData);
294unsigned char GetByte(void);
295void writePort(unsigned char pins, unsigned char value);
296unsigned char readPort(void);
297void sclock(void);
298#endif
299