1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2009
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 */
6
7#ifndef _IMXIMAGE_H_
8#define _IMXIMAGE_H_
9
10#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
11#define MAX_PLUGIN_CODE_SIZE (64 * 1024)
12#define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */
13#define APP_CODE_BARKER	0xB1
14#define DCD_BARKER	0xB17219E9
15
16/* Specify the offset of the IVT in the IMX header as expected by BootROM */
17#define BOOTROM_IVT_HDR_OFFSET	0xC00
18
19/*
20 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
21 *       mach-imx/imximage.cfg because tools/imximage.c can not
22 *       cross-include headers from arch/arm/ and vice-versa.
23 */
24#define CMD_DATA_STR	"DATA"
25
26/* Initial Vector Table Offset */
27#define FLASH_OFFSET_UNDEFINED	0xFFFFFFFF
28#define FLASH_OFFSET_STANDARD	0x400
29#define FLASH_OFFSET_NAND	FLASH_OFFSET_STANDARD
30#define FLASH_OFFSET_SD		FLASH_OFFSET_STANDARD
31#define FLASH_OFFSET_SPI	FLASH_OFFSET_STANDARD
32#define FLASH_OFFSET_ONENAND	0x100
33#define FLASH_OFFSET_NOR	0x1000
34#define FLASH_OFFSET_SATA	FLASH_OFFSET_STANDARD
35#define FLASH_OFFSET_QSPI	0x1000
36#define FLASH_OFFSET_FLEXSPI	0x1000
37
38/* Initial Load Region Size */
39#define FLASH_LOADSIZE_UNDEFINED	0xFFFFFFFF
40#define FLASH_LOADSIZE_STANDARD		0x1000
41#define FLASH_LOADSIZE_NAND		FLASH_LOADSIZE_STANDARD
42#define FLASH_LOADSIZE_SD		FLASH_LOADSIZE_STANDARD
43#define FLASH_LOADSIZE_SPI		FLASH_LOADSIZE_STANDARD
44#define FLASH_LOADSIZE_ONENAND		0x400
45#define FLASH_LOADSIZE_NOR		0x0 /* entire image */
46#define FLASH_LOADSIZE_SATA		FLASH_LOADSIZE_STANDARD
47#define FLASH_LOADSIZE_QSPI		0x0 /* entire image */
48
49/* Command tags and parameters */
50#define IVT_HEADER_TAG			0xD1
51#define IVT_VERSION			0x40
52#define IVT_VERSION_V3			0x41
53#define DCD_HEADER_TAG			0xD2
54#define DCD_VERSION			0x40
55#define DCD_WRITE_DATA_COMMAND_TAG	0xCC
56#define DCD_WRITE_DATA_PARAM		0x4
57#define DCD_WRITE_CLR_BIT_PARAM		0xC
58#define DCD_WRITE_SET_BIT_PARAM		0x1C
59#define DCD_CHECK_DATA_COMMAND_TAG	0xCF
60#define DCD_CHECK_BITS_SET_PARAM	0x14
61#define DCD_CHECK_BITS_CLR_PARAM	0x04
62
63#ifndef __ASSEMBLY__
64enum imximage_cmd {
65	CMD_INVALID,
66	CMD_IMAGE_VERSION,
67	CMD_BOOT_FROM,
68	CMD_BOOT_OFFSET,
69	CMD_WRITE_DATA,
70	CMD_WRITE_CLR_BIT,
71	CMD_WRITE_SET_BIT,
72	CMD_CHECK_BITS_SET,
73	CMD_CHECK_BITS_CLR,
74	CMD_CSF,
75	CMD_PLUGIN,
76	/* Following on i.MX8MQ/MM */
77	CMD_FIT,
78	CMD_SIGNED_HDMI,
79	CMD_LOADER,
80	CMD_SECOND_LOADER,
81	CMD_DDR_FW,
82	CMD_ROM_VERSION,
83};
84
85enum imximage_fld_types {
86	CFG_INVALID = -1,
87	CFG_COMMAND,
88	CFG_REG_SIZE,
89	CFG_REG_ADDRESS,
90	CFG_REG_VALUE
91};
92
93enum imximage_version {
94	IMXIMAGE_VER_INVALID = -1,
95	IMXIMAGE_V1 = 1,
96	IMXIMAGE_V2,
97	IMXIMAGE_V3
98};
99
100typedef struct {
101	uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
102	uint32_t addr; /* Address to write to */
103	uint32_t value; /* Data to write */
104} dcd_type_addr_data_t;
105
106typedef struct {
107	uint32_t barker; /* Barker for sanity check */
108	uint32_t length; /* Device configuration length (without preamble) */
109} dcd_preamble_t;
110
111typedef struct {
112	dcd_preamble_t preamble;
113	dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
114} dcd_v1_t;
115
116typedef struct {
117	uint32_t app_code_jump_vector;
118	uint32_t app_code_barker;
119	uint32_t app_code_csf;
120	uint32_t dcd_ptr_ptr;
121	uint32_t super_root_key;
122	uint32_t dcd_ptr;
123	uint32_t app_dest_ptr;
124} flash_header_v1_t;
125
126typedef struct {
127	uint32_t length;	/* Length of data to be read from flash */
128} flash_cfg_parms_t;
129
130typedef struct {
131	flash_header_v1_t fhdr;
132	dcd_v1_t dcd_table;
133	flash_cfg_parms_t ext_header;
134} imx_header_v1_t;
135
136typedef struct {
137	uint32_t addr;
138	uint32_t value;
139} dcd_addr_data_t;
140
141typedef struct {
142	uint8_t tag;
143	uint16_t length;
144	uint8_t version;
145} __attribute__((packed)) ivt_header_t;
146
147typedef struct {
148	uint8_t tag;
149	uint16_t length;
150	uint8_t param;
151} __attribute__((packed)) write_dcd_command_t;
152
153struct dcd_v2_cmd {
154	write_dcd_command_t write_dcd_command;
155	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
156};
157
158typedef struct {
159	ivt_header_t header;
160	struct dcd_v2_cmd dcd_cmd;
161	uint32_t padding[1]; /* end up on an 8-byte boundary */
162} dcd_v2_t;
163
164typedef struct {
165	uint32_t start;
166	uint32_t size;
167	uint32_t plugin;
168} boot_data_t;
169
170typedef struct {
171	ivt_header_t header;
172	uint32_t entry;
173	uint32_t reserved1;
174	uint32_t dcd_ptr;
175	uint32_t boot_data_ptr;
176	uint32_t self;
177	uint32_t csf;
178	uint32_t reserved2;
179} flash_header_v2_t;
180
181typedef struct {
182	flash_header_v2_t fhdr;
183	boot_data_t boot_data;
184	union {
185		dcd_v2_t dcd_table;
186		char plugin_code[MAX_PLUGIN_CODE_SIZE];
187	} data;
188} imx_header_v2_t;
189
190typedef struct {
191	flash_header_v2_t fhdr;
192	boot_data_t boot_data;
193	uint32_t padding[5];
194} imx_header_v3_t;
195
196/* The header must be aligned to 4k on MX53 for NAND boot */
197struct imx_header {
198	union {
199		imx_header_v1_t hdr_v1;
200		imx_header_v2_t hdr_v2;
201	} header;
202};
203
204typedef struct {
205	uint8_t tag[4];
206	uint8_t version[4];
207	uint8_t reserved_1[4];
208	uint8_t read_sample;
209	uint8_t datahold;
210	uint8_t datasetup;
211	uint8_t coladdrwidth;
212	uint8_t devcfgenable;
213	uint8_t deviceModeType;
214	uint16_t waitTimeCfgCommands;
215	uint8_t devmodeseq[4];
216	uint32_t devmodearg;
217	uint8_t cmd_enable;
218	uint8_t configModeType[3];
219	uint8_t cmd_seq[16] ;
220	uint8_t cmd_arg[16];
221	uint32_t controllermisc;
222	uint8_t dev_type;
223	uint8_t sflash_pad;
224	uint8_t serial_clk;
225	uint8_t lut_custom;
226	uint8_t reserved_2[8];
227	uint32_t sflashA1;
228	uint32_t sflashA2;
229	uint32_t sflashB1;
230	uint32_t sflashB2;
231	uint32_t cspadover;
232	uint32_t sclkpadover;
233	uint32_t datapadover;
234	uint32_t dqspadover;
235	uint32_t timeout;
236	uint32_t commandInt;
237	uint16_t datavalid[2];
238	uint16_t busyoffset;
239	uint16_t busybitpolarity;
240	uint8_t lut[256];
241	uint8_t lutCustomSeq[48];
242	uint8_t reserved_3[16];
243
244} __attribute__((packed)) fspi_conf;
245
246typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
247					char *name, int lineno,
248					int fld, uint32_t value,
249					uint32_t off);
250
251typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
252					int32_t cmd);
253
254typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
255					uint32_t dcd_len,
256					char *name, int lineno);
257
258typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
259		uint32_t entry_point, uint32_t flash_offset);
260
261#endif /* __ASSEMBLY__ */
262#endif /* _IMXIMAGE_H_ */
263