1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 5 */ 6 7#ifndef __FSL_IFC_H 8#define __FSL_IFC_H 9 10#ifdef CONFIG_FSL_IFC 11#include <config.h> 12#include <part.h> 13#ifdef CONFIG_ARM 14#include <asm/arch/soc.h> 15#endif 16 17#define FSL_IFC_V1_1_0 0x01010000 18#define FSL_IFC_V2_0_0 0x02000000 19 20#ifdef CONFIG_SYS_FSL_IFC_LE 21#define ifc_in32(a) in_le32(a) 22#define ifc_out32(a, v) out_le32(a, v) 23#define ifc_in16(a) in_le16(a) 24#define ifc_out16(a, v) out_le16(a, v) 25#elif defined(CONFIG_SYS_FSL_IFC_BE) 26#define ifc_in32(a) in_be32(a) 27#define ifc_out32(a, v) out_be32(a, v) 28#define ifc_in16(a) in_be16(a) 29#define ifc_out16(a, v) out_be16(a, v) 30#else 31#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined 32#endif 33 34 35/* 36 * CSPR - Chip Select Property Register 37 */ 38#define CSPR_BA 0xFFFF0000 39#define CSPR_BA_SHIFT 16 40#define CSPR_PORT_SIZE 0x00000180 41#define CSPR_PORT_SIZE_SHIFT 7 42/* Port Size 8 bit */ 43#define CSPR_PORT_SIZE_8 0x00000080 44/* Port Size 16 bit */ 45#define CSPR_PORT_SIZE_16 0x00000100 46/* Port Size 32 bit */ 47#define CSPR_PORT_SIZE_32 0x00000180 48/* Write Protect */ 49#define CSPR_WP 0x00000040 50#define CSPR_WP_SHIFT 6 51/* Machine Select */ 52#define CSPR_MSEL 0x00000006 53#define CSPR_MSEL_SHIFT 1 54/* External Transceiver Enable */ 55#define CSPR_TE 0x00000010 56/* NOR */ 57#define CSPR_MSEL_NOR 0x00000000 58/* NAND */ 59#define CSPR_MSEL_NAND 0x00000002 60/* GPCM */ 61#define CSPR_MSEL_GPCM 0x00000004 62/* Bank Valid */ 63#define CSPR_V 0x00000001 64#define CSPR_V_SHIFT 0 65 66/* Convert an address into the right format for the CSPR Registers */ 67#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) 68 69/* 70 * Address Mask Register 71 */ 72#define IFC_AMASK_MASK 0xFFFF0000 73#define IFC_AMASK_SHIFT 16 74#define IFC_AMASK(n) (IFC_AMASK_MASK << \ 75 (LOG2(n) - IFC_AMASK_SHIFT)) 76 77/* 78 * Chip Select Option Register IFC_NAND Machine 79 */ 80/* Enable ECC Encoder */ 81#define CSOR_NAND_ECC_ENC_EN 0x80000000 82#define CSOR_NAND_ECC_MODE_MASK 0x30000000 83/* 4 bit correction per 520 Byte sector */ 84#define CSOR_NAND_ECC_MODE_4 0x00000000 85/* 8 bit correction per 528 Byte sector */ 86#define CSOR_NAND_ECC_MODE_8 0x10000000 87/* Enable ECC Decoder */ 88#define CSOR_NAND_ECC_DEC_EN 0x04000000 89/* Row Address Length */ 90#define CSOR_NAND_RAL_MASK 0x01800000 91#define CSOR_NAND_RAL_SHIFT 20 92#define CSOR_NAND_RAL_1 0x00000000 93#define CSOR_NAND_RAL_2 0x00800000 94#define CSOR_NAND_RAL_3 0x01000000 95#define CSOR_NAND_RAL_4 0x01800000 96/* Page Size 512b, 2k, 4k */ 97#define CSOR_NAND_PGS_MASK 0x00180000 98#define CSOR_NAND_PGS_SHIFT 16 99#define CSOR_NAND_PGS_512 0x00000000 100#define CSOR_NAND_PGS_2K 0x00080000 101#define CSOR_NAND_PGS_4K 0x00100000 102#define CSOR_NAND_PGS_8K 0x00180000 103/* Spare region Size */ 104#define CSOR_NAND_SPRZ_MASK 0x0000E000 105#define CSOR_NAND_SPRZ_SHIFT 13 106#define CSOR_NAND_SPRZ_16 0x00000000 107#define CSOR_NAND_SPRZ_64 0x00002000 108#define CSOR_NAND_SPRZ_128 0x00004000 109#define CSOR_NAND_SPRZ_210 0x00006000 110#define CSOR_NAND_SPRZ_218 0x00008000 111#define CSOR_NAND_SPRZ_224 0x0000A000 112#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 113/* Pages Per Block */ 114#define CSOR_NAND_PB_MASK 0x00000700 115#define CSOR_NAND_PB_SHIFT 8 116#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) 117/* Time for Read Enable High to Output High Impedance */ 118#define CSOR_NAND_TRHZ_MASK 0x0000001C 119#define CSOR_NAND_TRHZ_SHIFT 2 120#define CSOR_NAND_TRHZ_20 0x00000000 121#define CSOR_NAND_TRHZ_40 0x00000004 122#define CSOR_NAND_TRHZ_60 0x00000008 123#define CSOR_NAND_TRHZ_80 0x0000000C 124#define CSOR_NAND_TRHZ_100 0x00000010 125/* Buffer control disable */ 126#define CSOR_NAND_BCTLD 0x00000001 127 128/* 129 * Chip Select Option Register - NOR Flash Mode 130 */ 131/* Enable Address shift Mode */ 132#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 133/* Page Read Enable from NOR device */ 134#define CSOR_NOR_PGRD_EN 0x10000000 135/* AVD Toggle Enable during Burst Program */ 136#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 137/* Address Data Multiplexing Shift */ 138#define CSOR_NOR_ADM_MASK 0x0003E000 139#define CSOR_NOR_ADM_SHIFT_SHIFT 13 140#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 141/* Type of the NOR device hooked */ 142#define CSOR_NOR_NOR_MODE_ASYNC_NOR 0x00000000 143#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 144/* Time for Read Enable High to Output High Impedance */ 145#define CSOR_NOR_TRHZ_MASK 0x0000001C 146#define CSOR_NOR_TRHZ_SHIFT 2 147#define CSOR_NOR_TRHZ_20 0x00000000 148#define CSOR_NOR_TRHZ_40 0x00000004 149#define CSOR_NOR_TRHZ_60 0x00000008 150#define CSOR_NOR_TRHZ_80 0x0000000C 151#define CSOR_NOR_TRHZ_100 0x00000010 152/* Buffer control disable */ 153#define CSOR_NOR_BCTLD 0x00000001 154 155/* 156 * Chip Select Option Register - GPCM Mode 157 */ 158/* GPCM Mode - Normal */ 159#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 160/* GPCM Mode - GenericASIC */ 161#define CSOR_GPCM_GPMODE_ASIC 0x80000000 162/* Parity Mode odd/even */ 163#define CSOR_GPCM_PARITY_EVEN 0x40000000 164/* Parity Checking enable/disable */ 165#define CSOR_GPCM_PAR_EN 0x20000000 166/* GPCM Timeout Count */ 167#define CSOR_GPCM_GPTO_MASK 0x0F000000 168#define CSOR_GPCM_GPTO_SHIFT 24 169#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 170/* GPCM External Access Termination mode for read access */ 171#define CSOR_GPCM_RGETA_EXT 0x00080000 172/* GPCM External Access Termination mode for write access */ 173#define CSOR_GPCM_WGETA_EXT 0x00040000 174/* Address Data Multiplexing Shift */ 175#define CSOR_GPCM_ADM_MASK 0x0003E000 176#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 177#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 178/* Generic ASIC Parity error indication delay */ 179#define CSOR_GPCM_GAPERRD_MASK 0x00000180 180#define CSOR_GPCM_GAPERRD_SHIFT 7 181#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 182/* Time for Read Enable High to Output High Impedance */ 183#define CSOR_GPCM_TRHZ_MASK 0x0000001C 184#define CSOR_GPCM_TRHZ_20 0x00000000 185#define CSOR_GPCM_TRHZ_40 0x00000004 186#define CSOR_GPCM_TRHZ_60 0x00000008 187#define CSOR_GPCM_TRHZ_80 0x0000000C 188#define CSOR_GPCM_TRHZ_100 0x00000010 189/* Buffer control disable */ 190#define CSOR_GPCM_BCTLD 0x00000001 191 192/* 193 * Flash Timing Registers (FTIM0 - FTIM2_CSn) 194 */ 195/* 196 * FTIM0 - NAND Flash Mode 197 */ 198#define FTIM0_NAND 0x7EFF3F3F 199#define FTIM0_NAND_TCCST_SHIFT 25 200#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) 201#define FTIM0_NAND_TWP_SHIFT 16 202#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) 203#define FTIM0_NAND_TWCHT_SHIFT 8 204#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) 205#define FTIM0_NAND_TWH_SHIFT 0 206#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) 207/* 208 * FTIM1 - NAND Flash Mode 209 */ 210#define FTIM1_NAND 0xFFFF3FFF 211#define FTIM1_NAND_TADLE_SHIFT 24 212#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) 213#define FTIM1_NAND_TWBE_SHIFT 16 214#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) 215#define FTIM1_NAND_TRR_SHIFT 8 216#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) 217#define FTIM1_NAND_TRP_SHIFT 0 218#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) 219/* 220 * FTIM2 - NAND Flash Mode 221 */ 222#define FTIM2_NAND 0x1FE1F8FF 223#define FTIM2_NAND_TRAD_SHIFT 21 224#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) 225#define FTIM2_NAND_TREH_SHIFT 11 226#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) 227#define FTIM2_NAND_TWHRE_SHIFT 0 228#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) 229/* 230 * FTIM3 - NAND Flash Mode 231 */ 232#define FTIM3_NAND 0xFF000000 233#define FTIM3_NAND_TWW_SHIFT 24 234#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) 235 236/* 237 * FTIM0 - NOR Flash Mode 238 */ 239#define FTIM0_NOR 0xF03F3F3F 240#define FTIM0_NOR_TACSE_SHIFT 28 241#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) 242#define FTIM0_NOR_TEADC_SHIFT 16 243#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) 244#define FTIM0_NOR_TAVDS_SHIFT 8 245#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) 246#define FTIM0_NOR_TEAHC_SHIFT 0 247#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) 248/* 249 * FTIM1 - NOR Flash Mode 250 */ 251#define FTIM1_NOR 0xFF003F3F 252#define FTIM1_NOR_TACO_SHIFT 24 253#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) 254#define FTIM1_NOR_TRAD_NOR_SHIFT 8 255#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) 256#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 257#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) 258/* 259 * FTIM2 - NOR Flash Mode 260 */ 261#define FTIM2_NOR 0x0F3CFCFF 262#define FTIM2_NOR_TCS_SHIFT 24 263#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) 264#define FTIM2_NOR_TCH_SHIFT 18 265#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) 266#define FTIM2_NOR_TWPH_SHIFT 10 267#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) 268#define FTIM2_NOR_TWP_SHIFT 0 269#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) 270 271/* 272 * FTIM0 - Normal GPCM Mode 273 */ 274#define FTIM0_GPCM 0xF03F3F3F 275#define FTIM0_GPCM_TACSE_SHIFT 28 276#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) 277#define FTIM0_GPCM_TEADC_SHIFT 16 278#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) 279#define FTIM0_GPCM_TAVDS_SHIFT 8 280#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) 281#define FTIM0_GPCM_TEAHC_SHIFT 0 282#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) 283/* 284 * FTIM1 - Normal GPCM Mode 285 */ 286#define FTIM1_GPCM 0xFF003F00 287#define FTIM1_GPCM_TACO_SHIFT 24 288#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) 289#define FTIM1_GPCM_TRAD_SHIFT 8 290#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) 291/* 292 * FTIM2 - Normal GPCM Mode 293 */ 294#define FTIM2_GPCM 0x0F3C00FF 295#define FTIM2_GPCM_TCS_SHIFT 24 296#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) 297#define FTIM2_GPCM_TCH_SHIFT 18 298#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) 299#define FTIM2_GPCM_TWP_SHIFT 0 300#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) 301 302/* 303 * Ready Busy Status Register (RB_STAT) 304 */ 305/* CSn is READY */ 306#define IFC_RB_STAT_READY_CS0 0x80000000 307#define IFC_RB_STAT_READY_CS1 0x40000000 308#define IFC_RB_STAT_READY_CS2 0x20000000 309#define IFC_RB_STAT_READY_CS3 0x10000000 310 311/* 312 * General Control Register (GCR) 313 */ 314#define IFC_GCR_MASK 0x8000F800 315/* reset all IFC hardware */ 316#define IFC_GCR_SOFT_RST_ALL 0x80000000 317/* Turnaroud Time of external buffer */ 318#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 319#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 320 321/* 322 * Common Event and Error Status Register (CM_EVTER_STAT) 323 */ 324/* Chip select error */ 325#define IFC_CM_EVTER_STAT_CSER 0x80000000 326 327/* 328 * Common Event and Error Enable Register (CM_EVTER_EN) 329 */ 330/* Chip select error checking enable */ 331#define IFC_CM_EVTER_EN_CSEREN 0x80000000 332 333/* 334 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 335 */ 336/* Chip select error interrupt enable */ 337#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 338 339/* 340 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 341 */ 342/* transaction type of error Read/Write */ 343#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 344#define IFC_CM_ERATTR0_ERAID 0x0FF00000 345#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 346 347/* 348 * Clock Control Register (CCR) 349 */ 350#define IFC_CCR_MASK 0x0F0F8800 351/* Clock division ratio */ 352#define IFC_CCR_CLK_DIV_MASK 0x0F000000 353#define IFC_CCR_CLK_DIV_SHIFT 24 354#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 355/* IFC Clock Delay */ 356#define IFC_CCR_CLK_DLY_MASK 0x000F0000 357#define IFC_CCR_CLK_DLY_SHIFT 16 358#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 359/* Invert IFC clock before sending out */ 360#define IFC_CCR_INV_CLK_EN 0x00008000 361/* Fedback IFC Clock */ 362#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 363 364/* 365 * Clock Status Register (CSR) 366 */ 367/* Clk is stable */ 368#define IFC_CSR_CLK_STAT_STABLE 0x80000000 369 370/* 371 * IFC_NAND Machine Specific Registers 372 */ 373/* 374 * NAND Configuration Register (NCFGR) 375 */ 376/* Auto Boot Mode */ 377#define IFC_NAND_NCFGR_BOOT 0x80000000 378/* SRAM INIT EN */ 379#define IFC_NAND_SRAM_INIT_EN 0x20000000 380/* Addressing Mode-ROW0+n/COL0 */ 381#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 382/* Addressing Mode-ROW0+n/COL0+n */ 383#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 384/* Number of loop iterations of FIR sequences for multi page operations */ 385#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 386#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 387#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 388/* Number of wait cycles */ 389#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 390#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 391 392/* 393 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 394 */ 395/* General purpose FCM flash command bytes CMD0-CMD7 */ 396#define IFC_NAND_FCR0_CMD0 0xFF000000 397#define IFC_NAND_FCR0_CMD0_SHIFT 24 398#define IFC_NAND_FCR0_CMD1 0x00FF0000 399#define IFC_NAND_FCR0_CMD1_SHIFT 16 400#define IFC_NAND_FCR0_CMD2 0x0000FF00 401#define IFC_NAND_FCR0_CMD2_SHIFT 8 402#define IFC_NAND_FCR0_CMD3 0x000000FF 403#define IFC_NAND_FCR0_CMD3_SHIFT 0 404#define IFC_NAND_FCR1_CMD4 0xFF000000 405#define IFC_NAND_FCR1_CMD4_SHIFT 24 406#define IFC_NAND_FCR1_CMD5 0x00FF0000 407#define IFC_NAND_FCR1_CMD5_SHIFT 16 408#define IFC_NAND_FCR1_CMD6 0x0000FF00 409#define IFC_NAND_FCR1_CMD6_SHIFT 8 410#define IFC_NAND_FCR1_CMD7 0x000000FF 411#define IFC_NAND_FCR1_CMD7_SHIFT 0 412 413/* 414 * Flash ROW and COL Address Register (ROWn, COLn) 415 */ 416/* Main/spare region locator */ 417#define IFC_NAND_COL_MS 0x80000000 418/* Column Address */ 419#define IFC_NAND_COL_CA_MASK 0x00000FFF 420 421/* 422 * NAND Flash Byte Count Register (NAND_BC) 423 */ 424/* Byte Count for read/Write */ 425#define IFC_NAND_BC 0x000001FF 426 427/* 428 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 429 */ 430/* NAND Machine specific opcodes OP0-OP14*/ 431#define IFC_NAND_FIR0_OP0 0xFC000000 432#define IFC_NAND_FIR0_OP0_SHIFT 26 433#define IFC_NAND_FIR0_OP1 0x03F00000 434#define IFC_NAND_FIR0_OP1_SHIFT 20 435#define IFC_NAND_FIR0_OP2 0x000FC000 436#define IFC_NAND_FIR0_OP2_SHIFT 14 437#define IFC_NAND_FIR0_OP3 0x00003F00 438#define IFC_NAND_FIR0_OP3_SHIFT 8 439#define IFC_NAND_FIR0_OP4 0x000000FC 440#define IFC_NAND_FIR0_OP4_SHIFT 2 441#define IFC_NAND_FIR1_OP5 0xFC000000 442#define IFC_NAND_FIR1_OP5_SHIFT 26 443#define IFC_NAND_FIR1_OP6 0x03F00000 444#define IFC_NAND_FIR1_OP6_SHIFT 20 445#define IFC_NAND_FIR1_OP7 0x000FC000 446#define IFC_NAND_FIR1_OP7_SHIFT 14 447#define IFC_NAND_FIR1_OP8 0x00003F00 448#define IFC_NAND_FIR1_OP8_SHIFT 8 449#define IFC_NAND_FIR1_OP9 0x000000FC 450#define IFC_NAND_FIR1_OP9_SHIFT 2 451#define IFC_NAND_FIR2_OP10 0xFC000000 452#define IFC_NAND_FIR2_OP10_SHIFT 26 453#define IFC_NAND_FIR2_OP11 0x03F00000 454#define IFC_NAND_FIR2_OP11_SHIFT 20 455#define IFC_NAND_FIR2_OP12 0x000FC000 456#define IFC_NAND_FIR2_OP12_SHIFT 14 457#define IFC_NAND_FIR2_OP13 0x00003F00 458#define IFC_NAND_FIR2_OP13_SHIFT 8 459#define IFC_NAND_FIR2_OP14 0x000000FC 460#define IFC_NAND_FIR2_OP14_SHIFT 2 461 462/* 463 * Instruction opcodes to be programmed 464 * in FIR registers- 6bits 465 */ 466enum ifc_nand_fir_opcodes { 467 IFC_FIR_OP_NOP, 468 IFC_FIR_OP_CA0, 469 IFC_FIR_OP_CA1, 470 IFC_FIR_OP_CA2, 471 IFC_FIR_OP_CA3, 472 IFC_FIR_OP_RA0, 473 IFC_FIR_OP_RA1, 474 IFC_FIR_OP_RA2, 475 IFC_FIR_OP_RA3, 476 IFC_FIR_OP_CMD0, 477 IFC_FIR_OP_CMD1, 478 IFC_FIR_OP_CMD2, 479 IFC_FIR_OP_CMD3, 480 IFC_FIR_OP_CMD4, 481 IFC_FIR_OP_CMD5, 482 IFC_FIR_OP_CMD6, 483 IFC_FIR_OP_CMD7, 484 IFC_FIR_OP_CW0, 485 IFC_FIR_OP_CW1, 486 IFC_FIR_OP_CW2, 487 IFC_FIR_OP_CW3, 488 IFC_FIR_OP_CW4, 489 IFC_FIR_OP_CW5, 490 IFC_FIR_OP_CW6, 491 IFC_FIR_OP_CW7, 492 IFC_FIR_OP_WBCD, 493 IFC_FIR_OP_RBCD, 494 IFC_FIR_OP_BTRD, 495 IFC_FIR_OP_RDSTAT, 496 IFC_FIR_OP_NWAIT, 497 IFC_FIR_OP_WFR, 498 IFC_FIR_OP_SBRD, 499 IFC_FIR_OP_UA, 500 IFC_FIR_OP_RB, 501}; 502 503/* 504 * NAND Chip Select Register (NAND_CSEL) 505 */ 506#define IFC_NAND_CSEL 0x0C000000 507#define IFC_NAND_CSEL_SHIFT 26 508#define IFC_NAND_CSEL_CS0 0x00000000 509#define IFC_NAND_CSEL_CS1 0x04000000 510#define IFC_NAND_CSEL_CS2 0x08000000 511#define IFC_NAND_CSEL_CS3 0x0C000000 512 513/* 514 * NAND Operation Sequence Start (NANDSEQ_STRT) 515 */ 516/* NAND Flash Operation Start */ 517#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 518/* Automatic Erase */ 519#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 520/* Automatic Program */ 521#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 522/* Automatic Copyback */ 523#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 524/* Automatic Read Operation */ 525#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 526/* Automatic Status Read */ 527#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 528 529/* 530 * NAND Event and Error Status Register (NAND_EVTER_STAT) 531 */ 532/* Operation Complete */ 533#define IFC_NAND_EVTER_STAT_OPC 0x80000000 534/* Flash Timeout Error */ 535#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 536/* Write Protect Error */ 537#define IFC_NAND_EVTER_STAT_WPER 0x04000000 538/* ECC Error */ 539#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 540/* RCW Load Done */ 541#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 542/* Boot Loadr Done */ 543#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 544/* Bad Block Indicator search select */ 545#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 546 547/* 548 * NAND Flash Page Read Completion Event Status Register 549 * (PGRDCMPL_EVT_STAT) 550 */ 551#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 552/* Small Page 0-15 Done */ 553#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 554/* Large Page(2K) 0-3 Done */ 555#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 556/* Large Page(4K) 0-1 Done */ 557#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 558 559/* 560 * NAND Event and Error Enable Register (NAND_EVTER_EN) 561 */ 562/* Operation complete event enable */ 563#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 564/* Page read complete event enable */ 565#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 566/* Flash Timeout error enable */ 567#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 568/* Write Protect error enable */ 569#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 570/* ECC error logging enable */ 571#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 572 573/* 574 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 575 */ 576/* Enable interrupt for operation complete */ 577#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 578/* Enable interrupt for Page read complete */ 579#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 580/* Enable interrupt for Flash timeout error */ 581#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 582/* Enable interrupt for Write protect error */ 583#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 584/* Enable interrupt for ECC error*/ 585#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 586 587/* 588 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 589 */ 590#define IFC_NAND_ERATTR0_MASK 0x0C080000 591/* Error on CS0-3 for NAND */ 592#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 593#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 594#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 595#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 596/* Transaction type of error Read/Write */ 597#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 598 599/* 600 * NAND Flash Status Register (NAND_FSR) 601 */ 602/* First byte of data read from read status op */ 603#define IFC_NAND_NFSR_RS0 0xFF000000 604/* Second byte of data read from read status op */ 605#define IFC_NAND_NFSR_RS1 0x00FF0000 606 607/* 608 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 609 */ 610/* Number of ECC errors on sector n (n = 0-15) */ 611#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 612#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 613#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 614#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 615#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 616#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 617#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 618#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 619#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 620#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 621#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 622#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 623#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 624#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 625#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 626#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 627#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 628#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 629#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 630#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 631#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 632#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 633#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 634#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 635#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 636#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 637#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 638#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 639#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 640#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 641#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 642#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 643 644/* 645 * NAND Control Register (NANDCR) 646 */ 647#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 648#define IFC_NAND_NCR_FTOCNT_SHIFT 25 649#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 650 651/* 652 * NAND_AUTOBOOT_TRGR 653 */ 654/* Trigger RCW load */ 655#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 656/* Trigget Auto Boot */ 657#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 658 659/* 660 * NAND_MDR 661 */ 662/* 1st read data byte when opcode SBRD */ 663#define IFC_NAND_MDR_RDATA0 0xFF000000 664/* 2nd read data byte when opcode SBRD */ 665#define IFC_NAND_MDR_RDATA1 0x00FF0000 666 667/* 668 * NOR Machine Specific Registers 669 */ 670/* 671 * NOR Event and Error Status Register (NOR_EVTER_STAT) 672 */ 673/* NOR Command Sequence Operation Complete */ 674#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 675/* Write Protect Error */ 676#define IFC_NOR_EVTER_STAT_WPER 0x04000000 677/* Command Sequence Timeout Error */ 678#define IFC_NOR_EVTER_STAT_STOER 0x01000000 679 680/* 681 * NOR Event and Error Enable Register (NOR_EVTER_EN) 682 */ 683/* NOR Command Seq complete event enable */ 684#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 685/* Write Protect Error Checking Enable */ 686#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 687/* Timeout Error Enable */ 688#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 689 690/* 691 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 692 */ 693/* Enable interrupt for OPC complete */ 694#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 695/* Enable interrupt for write protect error */ 696#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 697/* Enable interrupt for timeout error */ 698#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 699 700/* 701 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 702 */ 703/* Source ID for error transaction */ 704#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 705/* AXI ID for error transation */ 706#define IFC_NOR_ERATTR0_ERAID 0x000FF000 707/* Chip select corresponds to NOR error */ 708#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 709#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 710#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 711#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 712/* Type of transaction read/write */ 713#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 714 715/* 716 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 717 */ 718#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 719#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 720 721/* 722 * NOR Control Register (NORCR) 723 */ 724#define IFC_NORCR_MASK 0x0F0F0000 725/* No. of Address/Data Phase */ 726#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 727#define IFC_NORCR_NUM_PHASE_SHIFT 24 728#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 729/* Sequence Timeout Count */ 730#define IFC_NORCR_STOCNT_MASK 0x000F0000 731#define IFC_NORCR_STOCNT_SHIFT 16 732#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 733 734/* 735 * GPCM Machine specific registers 736 */ 737/* 738 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 739 */ 740/* Timeout error */ 741#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 742/* Parity error */ 743#define IFC_GPCM_EVTER_STAT_PER 0x01000000 744 745/* 746 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 747 */ 748/* Timeout error enable */ 749#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 750/* Parity error enable */ 751#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 752 753/* 754 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 755 */ 756/* Enable Interrupt for timeout error */ 757#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 758/* Enable Interrupt for Parity error */ 759#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 760 761/* 762 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 763 */ 764/* Source ID for error transaction */ 765#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 766/* AXI ID for error transaction */ 767#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 768/* Chip select corresponds to GPCM error */ 769#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 770#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 771#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 772#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 773/* Type of transaction read/Write */ 774#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 775 776/* 777 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 778 */ 779/* On which beat of address/data parity error is observed */ 780#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 781/* Parity Error on byte */ 782#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 783/* Parity Error reported in addr or data phase */ 784#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 785 786/* 787 * GPCM Status Register (GPCM_STAT) 788 */ 789#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 790 791 792#ifndef __ASSEMBLY__ 793#include <asm/io.h> 794 795extern void print_ifc_regs(void); 796extern void init_early_memctl_regs(void); 797void init_final_memctl_regs(void); 798 799#define IFC_RREGS_4KOFFSET (4*1024) 800#define IFC_RREGS_64KOFFSET (64*1024) 801 802#define IFC_FCM_BASE_ADDR \ 803 ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR) 804 805#define get_ifc_cspr_ext(i) \ 806 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) 807#define get_ifc_cspr(i) \ 808 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr)) 809#define get_ifc_csor_ext(i) \ 810 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext)) 811#define get_ifc_csor(i) \ 812 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor)) 813#define get_ifc_amask(i) \ 814 (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask)) 815#define get_ifc_ftim(i, j) \ 816 (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j])) 817#define set_ifc_cspr_ext(i, v) \ 818 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) 819#define set_ifc_cspr(i, v) \ 820 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v)) 821#define set_ifc_csor_ext(i, v) \ 822 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v)) 823#define set_ifc_csor(i, v) \ 824 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v)) 825#define set_ifc_amask(i, v) \ 826 (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v)) 827#define set_ifc_ftim(i, j, v) \ 828 (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v)) 829 830enum ifc_chip_sel { 831 IFC_CS0, 832 IFC_CS1, 833 IFC_CS2, 834 IFC_CS3, 835 IFC_CS4, 836 IFC_CS5, 837 IFC_CS6, 838 IFC_CS7, 839}; 840 841enum ifc_ftims { 842 IFC_FTIM0, 843 IFC_FTIM1, 844 IFC_FTIM2, 845 IFC_FTIM3, 846}; 847 848/* 849 * IFC Controller NAND Machine registers 850 */ 851struct fsl_ifc_nand { 852 u32 ncfgr; 853 u32 res1[0x4]; 854 u32 nand_fcr0; 855 u32 nand_fcr1; 856 u32 res2[0x8]; 857 u32 row0; 858 u32 res3; 859 u32 col0; 860 u32 res4; 861 u32 row1; 862 u32 res5; 863 u32 col1; 864 u32 res6; 865 u32 row2; 866 u32 res7; 867 u32 col2; 868 u32 res8; 869 u32 row3; 870 u32 res9; 871 u32 col3; 872 u32 res10[0x24]; 873 u32 nand_fbcr; 874 u32 res11; 875 u32 nand_fir0; 876 u32 nand_fir1; 877 u32 nand_fir2; 878 u32 res12[0x10]; 879 u32 nand_csel; 880 u32 res13; 881 u32 nandseq_strt; 882 u32 res14; 883 u32 nand_evter_stat; 884 u32 res15; 885 u32 pgrdcmpl_evt_stat; 886 u32 res16[0x2]; 887 u32 nand_evter_en; 888 u32 res17[0x2]; 889 u32 nand_evter_intr_en; 890 u32 nand_vol_addr_stat; 891 u32 res18; 892 u32 nand_erattr0; 893 u32 nand_erattr1; 894 u32 res19[0x10]; 895 u32 nand_fsr; 896 u32 res20[0x1]; 897 u32 nand_eccstat[8]; 898 u32 res21[0x1c]; 899 u32 nanndcr; 900 u32 res22[0x2]; 901 u32 nand_autoboot_trgr; 902 u32 res23; 903 u32 nand_mdr; 904 u32 res24[0x1c]; 905 u32 nand_dll_lowcfg0; 906 u32 nand_dll_lowcfg1; 907 u32 res25; 908 u32 nand_dll_lowstat; 909 u32 res26[0x3C]; 910}; 911 912/* 913 * IFC controller NOR Machine registers 914 */ 915struct fsl_ifc_nor { 916 u32 nor_evter_stat; 917 u32 res1[0x2]; 918 u32 nor_evter_en; 919 u32 res2[0x2]; 920 u32 nor_evter_intr_en; 921 u32 res3[0x2]; 922 u32 nor_erattr0; 923 u32 nor_erattr1; 924 u32 nor_erattr2; 925 u32 res4[0x4]; 926 u32 norcr; 927 u32 res5[0xEF]; 928}; 929 930/* 931 * IFC controller GPCM Machine registers 932 */ 933struct fsl_ifc_gpcm { 934 u32 gpcm_evter_stat; 935 u32 res1[0x2]; 936 u32 gpcm_evter_en; 937 u32 res2[0x2]; 938 u32 gpcm_evter_intr_en; 939 u32 res3[0x2]; 940 u32 gpcm_erattr0; 941 u32 gpcm_erattr1; 942 u32 gpcm_erattr2; 943 u32 gpcm_stat; 944}; 945 946#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT 947#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) 948#define IFC_CSPR_REG_LEN 148 949#define IFC_AMASK_REG_LEN 144 950#define IFC_CSOR_REG_LEN 144 951#define IFC_FTIM_REG_LEN 576 952 953#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ 954 CONFIG_SYS_FSL_IFC_BANK_COUNT 955#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ 956 CONFIG_SYS_FSL_IFC_BANK_COUNT 957#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ 958 CONFIG_SYS_FSL_IFC_BANK_COUNT 959#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ 960 CONFIG_SYS_FSL_IFC_BANK_COUNT 961#else 962#error IFC BANK count not vaild 963#endif 964#else 965#error IFC BANK count not defined 966#endif 967 968struct fsl_ifc_cspr { 969 u32 cspr_ext; 970 u32 cspr; 971 u32 res; 972}; 973 974struct fsl_ifc_amask { 975 u32 amask; 976 u32 res[0x2]; 977}; 978 979struct fsl_ifc_csor { 980 u32 csor; 981 u32 csor_ext; 982 u32 res; 983}; 984 985struct fsl_ifc_ftim { 986 u32 ftim[4]; 987 u32 res[0x8]; 988}; 989 990/* 991 * IFC Controller Global Registers 992 * FCM - Flash control machine 993 */ 994 995struct fsl_ifc_fcm { 996 u32 ifc_rev; 997 u32 res1[0x2]; 998 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 999 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; 1000 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1001 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; 1002 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1003 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; 1004 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1005 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; 1006 u32 rb_stat; 1007 u32 rb_map; 1008 u32 wp_map; 1009 u32 ifc_gcr; 1010 u32 res7[0x2]; 1011 u32 cm_evter_stat; 1012 u32 res8[0x2]; 1013 u32 cm_evter_en; 1014 u32 res9[0x2]; 1015 u32 cm_evter_intr_en; 1016 u32 res10[0x2]; 1017 u32 cm_erattr0; 1018 u32 cm_erattr1; 1019 u32 res11[0x2]; 1020 u32 ifc_ccr; 1021 u32 ifc_csr; 1022 u32 ddr_ccr_low; 1023}; 1024 1025struct fsl_ifc_runtime { 1026 struct fsl_ifc_nand ifc_nand; 1027 struct fsl_ifc_nor ifc_nor; 1028 struct fsl_ifc_gpcm ifc_gpcm; 1029}; 1030 1031struct fsl_ifc { 1032 struct fsl_ifc_fcm *gregs; 1033 struct fsl_ifc_runtime *rregs; 1034}; 1035 1036struct ifc_regs { 1037 const char *name; 1038 u32 pr; 1039 u32 pr_ext; 1040 u32 amask; 1041 u32 or; 1042 u32 ftim[4]; 1043 u32 or_ext; 1044 u32 pr_final; 1045 u32 amask_final; 1046}; 1047 1048struct ifc_regs_info { 1049 struct ifc_regs *regs; 1050 u32 cs_size; 1051}; 1052 1053#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1054#undef CSPR_MSEL_NOR 1055#define CSPR_MSEL_NOR CSPR_MSEL_GPCM 1056#endif 1057#endif /* CONFIG_FSL_IFC */ 1058 1059#endif /* __ASSEMBLY__ */ 1060#endif /* __FSL_IFC_H */ 1061