1106266Sjulian/* SPDX-License-Identifier: GPL-2.0 */ 2106266Sjulian/* 3139823Simp * R9A06G032 sysctrl IDs 4139823Simp * 5139823Simp * Copyright (C) 2018 Renesas Electronics Europe Limited 6144674Sglebius * 7106266Sjulian * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> 8106266Sjulian */ 9106266Sjulian 10106266Sjulian#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ 11106266Sjulian#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ 12106319Sjulian 13106266Sjulian#define R9A06G032_CLK_PLL_USB 1 14106319Sjulian#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ 15106319Sjulian#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ 16106266Sjulian#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ 17106319Sjulian#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ 18106319Sjulian#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ 19106266Sjulian#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ 20106266Sjulian#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ 21106266Sjulian#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ 22106319Sjulian#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ 23106319Sjulian#define R9A06G032_CLK_25_PG4 26 24106319Sjulian#define R9A06G032_CLK_25_PG5 27 25106266Sjulian#define R9A06G032_CLK_25_PG6 28 26106266Sjulian#define R9A06G032_CLK_25_PG7 29 27106266Sjulian#define R9A06G032_CLK_25_PG8 30 28106266Sjulian#define R9A06G032_CLK_ADC 31 29106266Sjulian#define R9A06G032_CLK_ECAT100 32 30106319Sjulian#define R9A06G032_CLK_HSR100 33 31106266Sjulian#define R9A06G032_CLK_I2C0 34 32106266Sjulian#define R9A06G032_CLK_I2C1 35 33106266Sjulian#define R9A06G032_CLK_MII_REF 36 34106266Sjulian#define R9A06G032_CLK_NAND 37 35106266Sjulian#define R9A06G032_CLK_NOUSBP2_PG6 38 36106266Sjulian#define R9A06G032_CLK_P1_PG2 39 37106266Sjulian#define R9A06G032_CLK_P1_PG3 40 38209728Semaste#define R9A06G032_CLK_P1_PG4 41 39106266Sjulian#define R9A06G032_CLK_P4_PG3 42 40106266Sjulian#define R9A06G032_CLK_P4_PG4 43 41125077Sharti#define R9A06G032_CLK_P6_PG1 44 42125077Sharti#define R9A06G032_CLK_P6_PG2 45 43125077Sharti#define R9A06G032_CLK_P6_PG3 46 44106266Sjulian#define R9A06G032_CLK_P6_PG4 47 45106266Sjulian#define R9A06G032_CLK_PCI_USB 48 46143387Sbmilekic#define R9A06G032_CLK_QSPI0 49 47143387Sbmilekic#define R9A06G032_CLK_QSPI1 50 48143387Sbmilekic#define R9A06G032_CLK_RGMII_REF 51 49143387Sbmilekic#define R9A06G032_CLK_RMII_REF 52 50106266Sjulian#define R9A06G032_CLK_SDIO0 53 51106266Sjulian#define R9A06G032_CLK_SDIO1 54 52106266Sjulian#define R9A06G032_CLK_SERCOS100 55 53106266Sjulian#define R9A06G032_CLK_SLCD 56 54106266Sjulian#define R9A06G032_CLK_SPI0 57 55106266Sjulian#define R9A06G032_CLK_SPI1 58 56143387Sbmilekic#define R9A06G032_CLK_SPI2 59 57106266Sjulian#define R9A06G032_CLK_SPI3 60 58106266Sjulian#define R9A06G032_CLK_SPI4 61 59106266Sjulian#define R9A06G032_CLK_SPI5 62 60106266Sjulian#define R9A06G032_CLK_SWITCH 63 61106266Sjulian#define R9A06G032_HCLK_ECAT125 65 62106266Sjulian#define R9A06G032_HCLK_PINCONFIG 66 63106266Sjulian#define R9A06G032_HCLK_SERCOS 67 64106266Sjulian#define R9A06G032_HCLK_SGPIO2 68 65106266Sjulian#define R9A06G032_HCLK_SGPIO3 69 66106266Sjulian#define R9A06G032_HCLK_SGPIO4 70 67106266Sjulian#define R9A06G032_HCLK_TIMER0 71 68144674Sglebius#define R9A06G032_HCLK_TIMER1 72 69106266Sjulian#define R9A06G032_HCLK_USBF 73 70106266Sjulian#define R9A06G032_HCLK_USBH 74 71196019Srwatson#define R9A06G032_HCLK_USBPM 75 72106266Sjulian#define R9A06G032_CLK_48_PG_F 76 73106266Sjulian#define R9A06G032_CLK_48_PG4 77 74106266Sjulian#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ 75106266Sjulian#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ 76106266Sjulian#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ 77106266Sjulian#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ 78106266Sjulian#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ 79106266Sjulian#define R9A06G032_HCLK_CAN0 85 80106266Sjulian#define R9A06G032_HCLK_CAN1 86 81167156Semaste#define R9A06G032_HCLK_DELTASIGMA 87 82167156Semaste#define R9A06G032_HCLK_PWMPTO 88 83106266Sjulian#define R9A06G032_HCLK_RSV 89 84106266Sjulian#define R9A06G032_HCLK_SGPIO0 90 85106266Sjulian#define R9A06G032_HCLK_SGPIO1 91 86144674Sglebius#define R9A06G032_RTOS_MDC 92 87144674Sglebius#define R9A06G032_CLK_CM3 93 88106266Sjulian#define R9A06G032_CLK_DDRC 94 89106319Sjulian#define R9A06G032_CLK_ECAT25 95 90167160Semaste#define R9A06G032_CLK_HSR50 96 91106266Sjulian#define R9A06G032_CLK_HW_RTOS 97 92137138Sglebius#define R9A06G032_CLK_SERCOS50 98 93144674Sglebius#define R9A06G032_HCLK_ADC 99 94144674Sglebius#define R9A06G032_HCLK_CM3 100 95167156Semaste#define R9A06G032_HCLK_CRYPTO_EIP150 101 96167160Semaste#define R9A06G032_HCLK_CRYPTO_EIP93 102 97106266Sjulian#define R9A06G032_HCLK_DDRC 103 98106266Sjulian#define R9A06G032_HCLK_DMA0 104 99106266Sjulian#define R9A06G032_HCLK_DMA1 105 100106266Sjulian#define R9A06G032_HCLK_GMAC0 106 101106266Sjulian#define R9A06G032_HCLK_GMAC1 107 102106266Sjulian#define R9A06G032_HCLK_GPIO0 108 103106266Sjulian#define R9A06G032_HCLK_GPIO1 109 104106266Sjulian#define R9A06G032_HCLK_GPIO2 110 105106266Sjulian#define R9A06G032_HCLK_HSR 111 106106266Sjulian#define R9A06G032_HCLK_I2C0 112 107106266Sjulian#define R9A06G032_HCLK_I2C1 113 108144674Sglebius#define R9A06G032_HCLK_LCD 114 109106266Sjulian#define R9A06G032_HCLK_MSEBI_M 115 110106266Sjulian#define R9A06G032_HCLK_MSEBI_S 116 111106266Sjulian#define R9A06G032_HCLK_NAND 117 112106266Sjulian#define R9A06G032_HCLK_PG_I 118 113125243Sharti#define R9A06G032_HCLK_PG19 119 114106266Sjulian#define R9A06G032_HCLK_PG20 120 115144674Sglebius#define R9A06G032_HCLK_PG3 121 116106266Sjulian#define R9A06G032_HCLK_PG4 122 117106266Sjulian#define R9A06G032_HCLK_QSPI0 123 118144674Sglebius#define R9A06G032_HCLK_QSPI1 124 119167156Semaste#define R9A06G032_HCLK_ROM 125 120167156Semaste#define R9A06G032_HCLK_RTC 126 121167160Semaste#define R9A06G032_HCLK_SDIO0 127 122167160Semaste#define R9A06G032_HCLK_SDIO1 128 123167160Semaste#define R9A06G032_HCLK_SEMAP 129 124167156Semaste#define R9A06G032_HCLK_SPI0 130 125167156Semaste#define R9A06G032_HCLK_SPI1 131 126106266Sjulian#define R9A06G032_HCLK_SPI2 132 127106266Sjulian#define R9A06G032_HCLK_SPI3 133 128125077Sharti#define R9A06G032_HCLK_SPI4 134 129106266Sjulian#define R9A06G032_HCLK_SPI5 135 130106266Sjulian#define R9A06G032_HCLK_SWITCH 136 131106266Sjulian#define R9A06G032_HCLK_SWITCH_RG 137 132106266Sjulian#define R9A06G032_HCLK_UART0 138 133106266Sjulian#define R9A06G032_HCLK_UART1 139 134106266Sjulian#define R9A06G032_HCLK_UART2 140 135106266Sjulian#define R9A06G032_HCLK_UART3 141 136106266Sjulian#define R9A06G032_HCLK_UART4 142 137106266Sjulian#define R9A06G032_HCLK_UART5 143 138106266Sjulian#define R9A06G032_HCLK_UART6 144 139106266Sjulian#define R9A06G032_HCLK_UART7 145 140106266Sjulian#define R9A06G032_CLK_UART0 146 141106266Sjulian#define R9A06G032_CLK_UART1 147 142106266Sjulian#define R9A06G032_CLK_UART2 148 143106266Sjulian#define R9A06G032_CLK_UART3 149 144106266Sjulian#define R9A06G032_CLK_UART4 150 145106266Sjulian#define R9A06G032_CLK_UART5 151 146167156Semaste#define R9A06G032_CLK_UART6 152 147167156Semaste#define R9A06G032_CLK_UART7 153 148167156Semaste 149167156Semaste#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ 150167156Semaste