1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2013
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7#ifndef _TEGRA124_COMMON_H_
8#define _TEGRA124_COMMON_H_
9
10#include "tegra-common.h"
11
12/*
13 * NS16550 Configuration
14 */
15#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
16
17/*
18 * Miscellaneous configurable options
19 */
20#define CFG_STACKBASE	0x83800000	/* 56MB */
21
22/*-----------------------------------------------------------------------
23 * Physical Memory Map
24 */
25
26/*
27 * Memory layout for where various images get loaded by boot scripts:
28 *
29 * scriptaddr can be pretty much anywhere that doesn't conflict with something
30 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
31 *
32 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
33 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
34 *
35 * kernel_addr_r must be within the first 128M of RAM in order for the
36 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
37 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
38 *   should not overlap that area, or the kernel will have to copy itself
39 *   somewhere else before decompression. Similarly, the address of any other
40 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
41 *   this up to 32M allows for a sizable kernel to be decompressed below the
42 *   compressed load address.
43 *
44 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
45 *   the compressed kernel to be up to 32M too.
46 *
47 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
48 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
49 */
50#define MEM_LAYOUT_ENV_SETTINGS \
51	"scriptaddr=0x90000000\0" \
52	"pxefile_addr_r=0x90100000\0" \
53	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
54	"fdtfile=" FDTFILE "\0" \
55	"fdt_addr_r=0x83000000\0" \
56	"ramdisk_addr_r=0x83100000\0"
57
58/* Defines for SPL */
59
60#endif /* _TEGRA124_COMMON_H_ */
61