1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2010
4 * Ilko Iliev <iliev@ronetix.at>
5 * Asen Dimov <dimov@ronetix.at>
6 * Ronetix GmbH <www.ronetix.at>
7 *
8 * (C) Copyright 2007-2008
9 * Stelian Pop <stelian@popies.net>
10 * Lead Tech Design <www.leadtechdesign.com>
11 *
12 * Configuation settings for the PM9G45 board.
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/* ARM asynchronous clock */
19#define CFG_SYS_AT91_SLOW_CLOCK      32768
20#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
21
22/* SDRAM */
23#define CFG_SYS_SDRAM_BASE           0x70000000
24#define CFG_SYS_SDRAM_SIZE		0x08000000
25
26/* NAND flash */
27#ifdef CONFIG_CMD_NAND
28#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
29/* our ALE is AD21 */
30#define CFG_SYS_NAND_MASK_ALE		BIT(21)
31/* our CLE is AD22 */
32#define CFG_SYS_NAND_MASK_CLE		BIT(22)
33#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
34#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PD3
35#endif
36
37#ifdef CONFIG_NAND_BOOT
38/* bootstrap + u-boot + env in nandflash */
39#elif CONFIG_SD_BOOT
40/* bootstrap + u-boot + env + linux in mmc */
41#endif
42
43/* Defines for SPL */
44
45#ifdef CONFIG_SD_BOOT
46#elif CONFIG_NAND_BOOT
47#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
48
49#define CFG_SYS_NAND_ECCSIZE		256
50#define CFG_SYS_NAND_ECCBYTES	3
51#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
52					  48, 49, 50, 51, 52, 53, 54, 55, \
53					  56, 57, 58, 59, 60, 61, 62, 63, }
54#endif
55
56#define CFG_SYS_MASTER_CLOCK		132096000
57#define CFG_SYS_AT91_PLLA		0x20c73f03
58#define CFG_SYS_MCKR			0x1301
59#define CFG_SYS_MCKR_CSS		0x1302
60
61#endif
62