1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 */
6
7#ifndef __LS1012AQDS_H__
8#define __LS1012AQDS_H__
9
10#include "ls1012a_common.h"
11
12/* DDR */
13#define CFG_SYS_SDRAM_SIZE		0x40000000
14
15/*
16 * QIXIS Definitions
17 */
18
19#ifdef CONFIG_FSL_QIXIS
20#define CFG_SYS_I2C_FPGA_ADDR	0x66
21#define QIXIS_LBMAP_BRDCFG_REG		0x04
22#define QIXIS_LBMAP_SWITCH		6
23#define QIXIS_LBMAP_MASK		0x08
24#define QIXIS_LBMAP_SHIFT		0
25#define QIXIS_LBMAP_DFLTBANK		0x00
26#define QIXIS_LBMAP_ALTBANK		0x08
27#define QIXIS_RST_CTL_RESET		0x31
28#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
29#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
30#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
31#endif
32
33/*
34 * I2C bus multiplexer
35 */
36#define I2C_MUX_PCA_ADDR_PRI		0x77
37#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
38#define I2C_RETIMER_ADDR		0x18
39#define I2C_MUX_CH_DEFAULT		0x8
40#define I2C_MUX_CH_CH7301		0xC
41#define I2C_MUX_CH5			0xD
42#define I2C_MUX_CH7			0xF
43
44#define I2C_MUX_CH_VOL_MONITOR 0xa
45
46/*
47* RTC configuration
48*/
49#define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
50
51
52/* Voltage monitor on channel 2*/
53#define I2C_VOL_MONITOR_ADDR           0x40
54#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
55#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
56#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
57
58#undef CFG_EXTRA_ENV_SETTINGS
59#define CFG_EXTRA_ENV_SETTINGS		\
60	"verify=no\0"				\
61	"kernel_addr=0x01000000\0"		\
62	"kernelheader_addr=0x600000\0"		\
63	"scriptaddr=0x80000000\0"		\
64	"scripthdraddr=0x80080000\0"		\
65	"fdtheader_addr_r=0x80100000\0"		\
66	"kernelheader_addr_r=0x80200000\0"	\
67	"kernel_addr_r=0x96000000\0"		\
68	"fdt_addr_r=0x90000000\0"		\
69	"load_addr=0xa0000000\0"		\
70	"kernel_size=0x2800000\0"		\
71	"kernelheader_size=0x40000\0"		\
72	"console=ttyS0,115200\0"		\
73	BOOTENV					\
74	"boot_scripts=ls1012aqds_boot.scr\0"	\
75	"boot_script_hdr=hdr_ls1012aqds_bs.out\0"	\
76	"scan_dev_for_boot_part="		\
77	     "part list ${devtype} ${devnum} devplist; "	\
78	     "env exists devplist || setenv devplist 1; "	\
79	     "for distro_bootpart in ${devplist}; do "		\
80		  "if fstype ${devtype} "			\
81		      "${devnum}:${distro_bootpart} "		\
82		      "bootfstype; then "			\
83		      "run scan_dev_for_boot; "	\
84		  "fi; "			\
85	      "done\0"				\
86	"boot_a_script="				  \
87		"load ${devtype} ${devnum}:${distro_bootpart} "  \
88			"${scriptaddr} ${prefix}${script}; "    \
89		"env exists secureboot && load ${devtype} "     \
90			"${devnum}:${distro_bootpart} "		\
91			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
92			"env exists secureboot "	\
93			"&& esbc_validate ${scripthdraddr};"    \
94		"source ${scriptaddr}\0"	  \
95	"qspi_bootcmd=echo Trying load from qspi..;"	\
96		"sf probe 0:0 && sf read $load_addr "	\
97		"$kernel_addr $kernel_size; env exists secureboot "	\
98		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
99		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
100		"bootm $load_addr#$board\0"
101
102#ifdef CONFIG_TFABOOT
103#undef QSPI_NOR_BOOTCOMMAND
104#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
105			     "env exists secureboot && esbc_halt;"
106#endif
107
108#include <asm/fsl_secure_boot.h>
109#endif /* __LS1012AQDS_H__ */
110