1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Embest/Timll DevKit3250 board configuration file
4 *
5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
6 */
7
8#ifndef __CONFIG_DEVKIT3250_H__
9#define __CONFIG_DEVKIT3250_H__
10
11/* SoC and board defines */
12#include <linux/sizes.h>
13#include <asm/arch/cpu.h>
14
15/*
16 * Memory configurations
17 */
18#define CFG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
19#define CFG_SYS_SDRAM_SIZE		SZ_64M
20
21/*
22 * DMA
23 */
24
25/*
26 * GPIO
27 */
28
29/*
30 * NOR Flash
31 */
32#define CFG_SYS_FLASH_BASE		EMC_CS0_BASE
33#define CFG_SYS_FLASH_SIZE		SZ_4M
34
35/*
36 * NAND controller
37 */
38#define CFG_SYS_NAND_BASE		SLC_NAND_BASE
39#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
40
41/*
42 * NAND chip timings
43 */
44#define CFG_LPC32XX_NAND_SLC_WDR_CLKS	14
45#define CFG_LPC32XX_NAND_SLC_WWIDTH		66666666
46#define CFG_LPC32XX_NAND_SLC_WHOLD		200000000
47#define CFG_LPC32XX_NAND_SLC_WSETUP		50000000
48#define CFG_LPC32XX_NAND_SLC_RDR_CLKS	14
49#define CFG_LPC32XX_NAND_SLC_RWIDTH		66666666
50#define CFG_LPC32XX_NAND_SLC_RHOLD		200000000
51#define CFG_LPC32XX_NAND_SLC_RSETUP		50000000
52
53/*
54 * USB
55 */
56#define CFG_USB_ISP1301_I2C_ADDR		0x2d
57
58/*
59 * U-Boot General Configurations
60 */
61
62/*
63 * Pass open firmware flat tree
64 */
65
66/*
67 * Environment
68 */
69
70#define CFG_EXTRA_ENV_SETTINGS		\
71	"ethaddr=00:01:90:00:C0:81\0"		\
72	"dtbaddr=0x81000000\0"			\
73	"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"	\
74	"tftpdir=vladimir/oe/devkit3250\0"	\
75	"userargs=oops=panic\0"
76
77/*
78 * U-Boot Commands
79 */
80
81/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
82#define CFG_SYS_NAND_U_BOOT_SIZE	0x60000
83
84#define CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
85#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
86
87/* See common/spl/spl.c  spl_set_header_raw_uboot() */
88
89/*
90 * Include SoC specific configuration
91 */
92#include <asm/arch/config.h>
93
94#endif  /* __CONFIG_DEVKIT3250_H__*/
95