1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2019 Logic PD, Inc.
4
5/ {
6	keyboard {
7		compatible = "gpio-keys";
8
9		button-0 {
10			gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
11			label = "btn0";
12			linux,code = <KEY_WAKEUP>;
13			debounce-interval = <10>;
14			wakeup-source;
15		};
16
17		button-1 {
18			gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
19			label = "btn1";
20			linux,code = <KEY_WAKEUP>;
21			debounce-interval = <10>;
22			wakeup-source;
23		};
24
25		button-2 {
26			gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
27			label = "btn2";
28			linux,code = <KEY_WAKEUP>;
29			debounce-interval = <10>;
30			wakeup-source;
31		};
32
33		button-3 {
34			gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
35			label = "btn3";
36			linux,code = <KEY_WAKEUP>;
37			debounce-interval = <10>;
38			wakeup-source;
39		};
40
41	};
42
43	leds {
44		compatible = "gpio-leds";
45
46		gen-led0 {
47			label = "led0";
48			pinctrl-names = "default";
49			pinctrl-0 = <&pinctrl_led0>;
50			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
51			linux,default-trigger = "cpu0";
52		};
53
54		gen-led1 {
55			label = "led1";
56			gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
57		};
58
59		gen-led2 {
60			label = "led2";
61			gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
62			linux,default-trigger = "heartbeat";
63		};
64
65		gen-led3 {
66			label = "led3";
67			gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
68			linux,default-trigger = "default-on";
69		};
70	};
71
72	reg_usb_otg_vbus: regulator-otg-vbus {
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_reg_usb_otg>;
75		compatible = "regulator-fixed";
76		regulator-name = "usb_otg_vbus";
77		regulator-min-microvolt = <5000000>;
78		regulator-max-microvolt = <5000000>;
79		gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
80		enable-active-high;
81	};
82
83	reg_usb_h1_vbus: regulator-usb-h1-vbus {
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
86		compatible = "regulator-fixed";
87		regulator-name = "usb_h1_vbus";
88		regulator-min-microvolt = <5000000>;
89		regulator-max-microvolt = <5000000>;
90		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
91		startup-delay-us = <70000>;
92		enable-active-high;
93	};
94
95	reg_3v3: regulator-3v3 {
96		pinctrl-names = "default";
97		pinctrl-0 = <&pinctrl_reg_3v3>;
98		compatible = "regulator-fixed";
99		regulator-name = "reg_3v3";
100		regulator-min-microvolt = <3300000>;
101		regulator-max-microvolt = <3300000>;
102		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
103		startup-delay-us = <70000>;
104		enable-active-high;
105		regulator-always-on;
106	};
107
108	reg_enet: regulator-ethernet {
109		pinctrl-names = "default";
110		pinctrl-0 = <&pinctrl_reg_enet>;
111		compatible = "regulator-fixed";
112		regulator-name = "ethernet-supply";
113		regulator-min-microvolt = <3300000>;
114		regulator-max-microvolt = <3300000>;
115		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
116		startup-delay-us = <70000>;
117		enable-active-high;
118		vin-supply = <&sw4_reg>;
119	};
120
121	reg_audio: regulator-audio {
122		pinctrl-names = "default";
123		pinctrl-0 = <&pinctrl_reg_audio>;
124		compatible = "regulator-fixed";
125		regulator-name = "3v3_aud";
126		regulator-min-microvolt = <3300000>;
127		regulator-max-microvolt = <3300000>;
128		gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
129		enable-active-high;
130		vin-supply = <&reg_3v3>;
131	};
132
133	reg_hdmi: regulator-hdmi {
134		pinctrl-names = "default";
135		pinctrl-0 = <&pinctrl_reg_hdmi>;
136		compatible = "regulator-fixed";
137		regulator-name = "hdmi-supply";
138		regulator-min-microvolt = <3300000>;
139		regulator-max-microvolt = <3300000>;
140		gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
141		enable-active-high;
142		vin-supply = <&reg_3v3>;
143	};
144
145	reg_uart3: regulator-uart3 {
146		pinctrl-names = "default";
147		pinctrl-0 = <&pinctrl_reg_uart3>;
148		compatible = "regulator-fixed";
149		regulator-name = "uart3-supply";
150		gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
151		enable-active-high;
152		regulator-always-on;
153		vin-supply = <&reg_3v3>;
154	};
155
156	reg_1v8: regulator-1v8 {
157		pinctrl-names = "default";
158		pinctrl-0 = <&pinctrl_reg_1v8>;
159		compatible = "regulator-fixed";
160		regulator-name = "1v8-supply";
161		gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
162		enable-active-high;
163		regulator-always-on;
164		vin-supply = <&reg_3v3>;
165	};
166
167	reg_pcie: regulator-pcie {
168		compatible = "regulator-fixed";
169		pinctrl-names = "default";
170		pinctrl-0 = <&pinctrl_reg_pcie>;
171		regulator-name = "mpcie_3v3";
172		regulator-min-microvolt = <3300000>;
173		regulator-max-microvolt = <3300000>;
174		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
175		enable-active-high;
176	};
177
178	reg_mipi: regulator-mipi {
179		compatible = "regulator-fixed";
180		pinctrl-names = "default";
181		pinctrl-0 = <&pinctrl_reg_mipi>;
182		regulator-name = "mipi_pwr_en";
183		regulator-min-microvolt = <2800000>;
184		regulator-max-microvolt = <2800000>;
185		gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
186		enable-active-high;
187	};
188
189	sound {
190		compatible = "fsl,imx-audio-wm8962";
191		model = "wm8962-audio";
192		ssi-controller = <&ssi2>;
193		audio-codec = <&wm8962>;
194		audio-routing =
195			"Headphone Jack", "HPOUTL",
196			"Headphone Jack", "HPOUTR",
197			"Ext Spk", "SPKOUTL",
198			"Ext Spk", "SPKOUTR",
199			"AMIC", "MICBIAS",
200			"IN3R", "AMIC";
201		mux-int-port = <2>;
202		mux-ext-port = <4>;
203	};
204};
205
206&audmux {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_audmux>;
209	status = "okay";
210};
211
212&ecspi1 {
213	pinctrl-names = "default";
214	pinctrl-0 = <&pinctrl_ecspi1>;
215	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
216	status = "disabled";
217};
218
219&fec {
220	pinctrl-names = "default";
221	pinctrl-0 = <&pinctrl_enet>;
222	phy-mode = "rgmii-id";
223	phy-reset-duration = <10>;
224	phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
225	phy-supply = <&reg_enet>;
226	interrupt-parent = <&gpio1>;
227	interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
228	status = "okay";
229};
230
231&i2c1 {
232	pinctrl-names = "default";
233	pinctrl-0 = <&pinctrl_i2c1>;
234	clock-frequency = <400000>;
235	status = "okay";
236
237	wm8962: audio-codec@1a {
238		compatible = "wlf,wm8962";
239		reg = <0x1a>;
240		clocks = <&clks IMX6QDL_CLK_CKO>;
241		DCVDD-supply = <&reg_audio>;
242		DBVDD-supply = <&reg_audio>;
243		AVDD-supply = <&reg_audio>;
244		CPVDD-supply = <&reg_audio>;
245		MICVDD-supply = <&reg_audio>;
246		PLLVDD-supply = <&reg_audio>;
247		SPKVDD1-supply = <&reg_audio>;
248		SPKVDD2-supply = <&reg_audio>;
249		gpio-cfg = <
250			0x0000 /* 0:Default */
251			0x0000 /* 1:Default */
252			0x0000 /* 2:FN_DMICCLK */
253			0x0000 /* 3:Default */
254			0x0000 /* 4:FN_DMICCDAT */
255			0x0000 /* 5:Default */
256		>;
257	};
258};
259
260&i2c3 {
261	ov5640: camera@10 {
262		compatible = "ovti,ov5640";
263		pinctrl-names = "default";
264		pinctrl-0 = <&pinctrl_ov5640>;
265		reg = <0x10>;
266		clocks = <&clks IMX6QDL_CLK_CKO>;
267		clock-names = "xclk";
268		DOVDD-supply = <&reg_mipi>;
269		AVDD-supply = <&reg_mipi>;
270		DVDD-supply = <&reg_mipi>;
271		reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
272		powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
273
274		port {
275			ov5640_to_mipi_csi2: endpoint {
276				remote-endpoint = <&mipi_csi2_in>;
277				clock-lanes = <0>;
278				data-lanes = <1 2>;
279			};
280		};
281	};
282
283	pcf8575: gpio@20 {
284		pinctrl-names = "default";
285		pinctrl-0 = <&pinctrl_pcf8574>;
286		compatible = "nxp,pcf8575";
287		reg = <0x20>;
288		interrupt-parent = <&gpio6>;
289		interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
290		gpio-controller;
291		#gpio-cells = <2>;
292		interrupt-controller;
293		#interrupt-cells = <2>;
294		lines-initial-states = <0x0710>;
295		wakeup-source;
296	};
297};
298
299&ipu1_csi1_from_mipi_vc1 {
300	clock-lanes = <0>;
301	data-lanes = <1 2>;
302};
303
304&mipi_csi {
305	status = "okay";
306
307	port@0 {
308		reg = <0>;
309
310		mipi_csi2_in: endpoint {
311			remote-endpoint = <&ov5640_to_mipi_csi2>;
312			clock-lanes = <0>;
313			data-lanes = <1 2>;
314		};
315	};
316};
317
318&pcie {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_pcie>;
321	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
322	vpcie-supply = <&reg_pcie>;
323	status = "okay";
324};
325
326&pwm3 {
327	pinctrl-names = "default";
328	pinctrl-0 = <&pinctrl_pwm3>;
329};
330
331&snvs_pwrkey {
332	status = "okay";
333};
334
335&ssi2 {
336	status = "okay";
337};
338
339&uart3 {
340	pinctrl-names = "default";
341	pinctrl-0 = <&pinctrl_uart3>;
342	status = "okay";
343};
344
345&usbh1 {
346	vbus-supply = <&reg_usb_h1_vbus>;
347	status = "okay";
348};
349
350&usbotg {
351	vbus-supply = <&reg_usb_otg_vbus>;
352	pinctrl-names = "default";
353	pinctrl-0 = <&pinctrl_usbotg>;
354	disable-over-current;
355	dr_mode = "otg";
356	status = "okay";
357};
358
359&usdhc2 {
360	pinctrl-names = "default";
361	pinctrl-0 = <&pinctrl_usdhc2>;
362	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
363	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
364	vmmc-supply = <&reg_3v3>;
365	no-1-8-v;
366	keep-power-in-suspend;
367	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
368	status = "okay";
369};
370
371&iomuxc {
372	pinctrl_audmux: audmuxgrp {
373		fsl,pins = <
374			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
375			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
376			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
377			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
378		>;
379	};
380
381	pinctrl_ecspi1: ecspi1grp {
382		fsl,pins = <
383			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
384			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
385			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
386			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
387		>;
388	};
389
390	pinctrl_enet: enetgrp {
391		fsl,pins = <
392			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
393			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
394			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
395			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
396			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
397			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
398			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
399			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
400			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
401			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
402			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
403			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
404			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
405			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
406			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
407			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
408			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0	/* ENET_INT */
409			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24	0x1b0b0	/* ETHR_nRST */
410		>;
411	};
412
413	pinctrl_i2c1: i2c1grp {
414		fsl,pins = <
415			MX6QDL_PAD_EIM_D21__I2C1_SCL	0x4001b8b1
416			MX6QDL_PAD_EIM_D28__I2C1_SDA	0x4001b8b1
417		>;
418	};
419
420	pinctrl_led0: led0grp {
421	    fsl,pins = <
422		MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0
423	    >;
424	};
425
426	pinctrl_ov5640: ov5640grp {
427		fsl,pins = <
428			MX6QDL_PAD_EIM_D26__GPIO3_IO26	0x1b0b1
429			MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x1b0b1
430		>;
431	};
432
433	pinctrl_pcf8574: pcf8575grp {
434		fsl,pins = <
435			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
436		>;
437	};
438
439	pinctrl_pcie: pciegrp {
440		fsl,pins = <
441			MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
442			MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
443		>;
444	};
445
446	pinctrl_pwm3: pwm3grp {
447	    fsl,pins = <
448		MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
449	    >;
450	};
451
452	pinctrl_reg_1v8: reg1v8grp {
453	    fsl,pins = <
454		MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
455	    >;
456	};
457
458	pinctrl_reg_3v3: reg3v3grp {
459	    fsl,pins = <
460		MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b0
461	    >;
462	};
463
464	pinctrl_reg_audio: reg-audiogrp {
465		fsl,pins = <
466			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
467		>;
468	};
469
470	pinctrl_reg_enet: reg-enetgrp {
471		fsl,pins = <
472			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x1b0b0
473		>;
474	};
475
476	pinctrl_reg_hdmi: reg-hdmigrp {
477		fsl,pins = <
478			MX6QDL_PAD_EIM_D20__GPIO3_IO20	0x1b0b0
479		>;
480	};
481
482	pinctrl_reg_mipi: reg-mipigrp {
483		fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
484	};
485
486	pinctrl_reg_pcie: reg-pciegrp {
487		fsl,pins = <
488			MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x1b0b0
489			>;
490	};
491
492	pinctrl_reg_uart3: reguart3grp {
493	    fsl,pins = <
494		MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
495	    >;
496	};
497
498	pinctrl_reg_usb_h1_vbus: usbh1grp {
499		fsl,pins = <
500			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
501		>;
502	};
503
504	pinctrl_reg_usb_otg: reg-usb-otggrp {
505		fsl,pins = <
506			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
507		>;
508	};
509
510	pinctrl_uart3: uart3grp {
511		fsl,pins = <
512			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
513			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
514			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
515			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
516		>;
517	};
518
519	pinctrl_usbotg: usbotggrp {
520		fsl,pins = <
521			MX6QDL_PAD_GPIO_1__USB_OTG_ID	0xd17059
522		>;
523	};
524
525	pinctrl_usdhc2: usdhc2grp {
526		fsl,pins = <
527			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
528			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17069
529			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10069
530			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17069
531			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17069
532			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17069
533			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17069
534		>;
535	};
536
537	pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
538		fsl,pins = <
539			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
540			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170b9
541			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100b9
542			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
543			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
544			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
545			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
546		>;
547	};
548
549	pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
550		fsl,pins = <
551			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
552			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170f9
553			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100f9
554			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
555			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
556			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
557			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
558		>;
559	};
560
561};
562