1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com> 6 */ 7 8#ifndef _DT_BINDINGS_CLK_MT7988_H 9#define _DT_BINDINGS_CLK_MT7988_H 10 11/* APMIXEDSYS */ 12 13#define CLK_APMIXED_NETSYSPLL 0 14#define CLK_APMIXED_MPLL 1 15#define CLK_APMIXED_MMPLL 2 16#define CLK_APMIXED_APLL2 3 17#define CLK_APMIXED_NET1PLL 4 18#define CLK_APMIXED_NET2PLL 5 19#define CLK_APMIXED_WEDMCUPLL 6 20#define CLK_APMIXED_SGMPLL 7 21#define CLK_APMIXED_ARM_B 8 22#define CLK_APMIXED_CCIPLL2_B 9 23#define CLK_APMIXED_USXGMIIPLL 10 24#define CLK_APMIXED_MSDCPLL 11 25 26/* TOPCKGEN */ 27 28#define CLK_TOP_XTAL 0 29#define CLK_TOP_XTAL_D2 1 30#define CLK_TOP_RTC_32K 2 31#define CLK_TOP_RTC_32P7K 3 32#define CLK_TOP_MPLL_D2 4 33#define CLK_TOP_MPLL_D3_D2 5 34#define CLK_TOP_MPLL_D4 6 35#define CLK_TOP_MPLL_D8 7 36#define CLK_TOP_MPLL_D8_D2 8 37#define CLK_TOP_MMPLL_D2 9 38#define CLK_TOP_MMPLL_D3_D5 10 39#define CLK_TOP_MMPLL_D4 11 40#define CLK_TOP_MMPLL_D6_D2 12 41#define CLK_TOP_MMPLL_D8 13 42#define CLK_TOP_APLL2_D4 14 43#define CLK_TOP_NET1PLL_D4 15 44#define CLK_TOP_NET1PLL_D5 16 45#define CLK_TOP_NET1PLL_D5_D2 17 46#define CLK_TOP_NET1PLL_D5_D4 18 47#define CLK_TOP_NET1PLL_D8 19 48#define CLK_TOP_NET1PLL_D8_D2 20 49#define CLK_TOP_NET1PLL_D8_D4 21 50#define CLK_TOP_NET1PLL_D8_D8 22 51#define CLK_TOP_NET1PLL_D8_D16 23 52#define CLK_TOP_NET2PLL_D2 24 53#define CLK_TOP_NET2PLL_D4 25 54#define CLK_TOP_NET2PLL_D4_D4 26 55#define CLK_TOP_NET2PLL_D4_D8 27 56#define CLK_TOP_NET2PLL_D6 28 57#define CLK_TOP_NET2PLL_D8 29 58#define CLK_TOP_NETSYS_SEL 30 59#define CLK_TOP_NETSYS_500M_SEL 31 60#define CLK_TOP_NETSYS_2X_SEL 32 61#define CLK_TOP_NETSYS_GSW_SEL 33 62#define CLK_TOP_ETH_GMII_SEL 34 63#define CLK_TOP_NETSYS_MCU_SEL 35 64#define CLK_TOP_NETSYS_PAO_2X_SEL 36 65#define CLK_TOP_EIP197_SEL 37 66#define CLK_TOP_AXI_INFRA_SEL 38 67#define CLK_TOP_UART_SEL 39 68#define CLK_TOP_EMMC_250M_SEL 40 69#define CLK_TOP_EMMC_400M_SEL 41 70#define CLK_TOP_SPI_SEL 42 71#define CLK_TOP_SPIM_MST_SEL 43 72#define CLK_TOP_NFI1X_SEL 44 73#define CLK_TOP_SPINFI_SEL 45 74#define CLK_TOP_PWM_SEL 46 75#define CLK_TOP_I2C_SEL 47 76#define CLK_TOP_PCIE_MBIST_250M_SEL 48 77#define CLK_TOP_PEXTP_TL_SEL 49 78#define CLK_TOP_PEXTP_TL_P1_SEL 50 79#define CLK_TOP_PEXTP_TL_P2_SEL 51 80#define CLK_TOP_PEXTP_TL_P3_SEL 52 81#define CLK_TOP_USB_SYS_SEL 53 82#define CLK_TOP_USB_SYS_P1_SEL 54 83#define CLK_TOP_USB_XHCI_SEL 55 84#define CLK_TOP_USB_XHCI_P1_SEL 56 85#define CLK_TOP_USB_FRMCNT_SEL 57 86#define CLK_TOP_USB_FRMCNT_P1_SEL 58 87#define CLK_TOP_AUD_SEL 59 88#define CLK_TOP_A1SYS_SEL 60 89#define CLK_TOP_AUD_L_SEL 61 90#define CLK_TOP_A_TUNER_SEL 62 91#define CLK_TOP_SSPXTP_SEL 63 92#define CLK_TOP_USB_PHY_SEL 64 93#define CLK_TOP_USXGMII_SBUS_0_SEL 65 94#define CLK_TOP_USXGMII_SBUS_1_SEL 66 95#define CLK_TOP_SGM_0_SEL 67 96#define CLK_TOP_SGM_SBUS_0_SEL 68 97#define CLK_TOP_SGM_1_SEL 69 98#define CLK_TOP_SGM_SBUS_1_SEL 70 99#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 100#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 101#define CLK_TOP_SYSAXI_SEL 73 102#define CLK_TOP_SYSAPB_SEL 74 103#define CLK_TOP_ETH_REFCK_50M_SEL 75 104#define CLK_TOP_ETH_SYS_200M_SEL 76 105#define CLK_TOP_ETH_SYS_SEL 77 106#define CLK_TOP_ETH_XGMII_SEL 78 107#define CLK_TOP_BUS_TOPS_SEL 79 108#define CLK_TOP_NPU_TOPS_SEL 80 109#define CLK_TOP_DRAMC_SEL 81 110#define CLK_TOP_DRAMC_MD32_SEL 82 111#define CLK_TOP_INFRA_F26M_SEL 83 112#define CLK_TOP_PEXTP_P0_SEL 84 113#define CLK_TOP_PEXTP_P1_SEL 85 114#define CLK_TOP_PEXTP_P2_SEL 86 115#define CLK_TOP_PEXTP_P3_SEL 87 116#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 117#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 118#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 119#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 120#define CLK_TOP_CKM_SEL 92 121#define CLK_TOP_DA_SEL 93 122#define CLK_TOP_PEXTP_SEL 94 123#define CLK_TOP_TOPS_P2_26M_SEL 95 124#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 125#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 126#define CLK_TOP_MACSEC_SEL 98 127#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 128#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 129#define CLK_TOP_NETSYS_WARP_SEL 101 130#define CLK_TOP_ETH_MII_SEL 102 131#define CLK_TOP_NPU_SEL 103 132#define CLK_TOP_AUD_I2S_M 104 133 134/* MCUSYS */ 135 136#define CLK_MCU_BUS_DIV_SEL 0 137#define CLK_MCU_ARM_DIV_SEL 1 138 139/* INFRACFG_AO */ 140 141#define CLK_INFRA_MUX_UART0_SEL 0 142#define CLK_INFRA_MUX_UART1_SEL 1 143#define CLK_INFRA_MUX_UART2_SEL 2 144#define CLK_INFRA_MUX_SPI0_SEL 3 145#define CLK_INFRA_MUX_SPI1_SEL 4 146#define CLK_INFRA_MUX_SPI2_SEL 5 147#define CLK_INFRA_PWM_SEL 6 148#define CLK_INFRA_PWM_CK1_SEL 7 149#define CLK_INFRA_PWM_CK2_SEL 8 150#define CLK_INFRA_PWM_CK3_SEL 9 151#define CLK_INFRA_PWM_CK4_SEL 10 152#define CLK_INFRA_PWM_CK5_SEL 11 153#define CLK_INFRA_PWM_CK6_SEL 12 154#define CLK_INFRA_PWM_CK7_SEL 13 155#define CLK_INFRA_PWM_CK8_SEL 14 156#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 157#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 158#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 159#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 160 161/* INFRACFG */ 162 163#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 164#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 165#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 166#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 167#define CLK_INFRA_66M_GPT_BCK 23 168#define CLK_INFRA_66M_PWM_HCK 24 169#define CLK_INFRA_66M_PWM_BCK 25 170#define CLK_INFRA_66M_PWM_CK1 26 171#define CLK_INFRA_66M_PWM_CK2 27 172#define CLK_INFRA_66M_PWM_CK3 28 173#define CLK_INFRA_66M_PWM_CK4 29 174#define CLK_INFRA_66M_PWM_CK5 30 175#define CLK_INFRA_66M_PWM_CK6 31 176#define CLK_INFRA_66M_PWM_CK7 32 177#define CLK_INFRA_66M_PWM_CK8 33 178#define CLK_INFRA_133M_CQDMA_BCK 34 179#define CLK_INFRA_66M_AUD_SLV_BCK 35 180#define CLK_INFRA_AUD_26M 36 181#define CLK_INFRA_AUD_L 37 182#define CLK_INFRA_AUD_AUD 38 183#define CLK_INFRA_AUD_EG2 39 184#define CLK_INFRA_DRAMC_F26M 40 185#define CLK_INFRA_133M_DBG_ACKM 41 186#define CLK_INFRA_66M_AP_DMA_BCK 42 187#define CLK_INFRA_66M_SEJ_BCK 43 188#define CLK_INFRA_PRE_CK_SEJ_F13M 44 189#define CLK_INFRA_26M_THERM_SYSTEM 45 190#define CLK_INFRA_I2C_BCK 46 191#define CLK_INFRA_52M_UART0_CK 47 192#define CLK_INFRA_52M_UART1_CK 48 193#define CLK_INFRA_52M_UART2_CK 49 194#define CLK_INFRA_NFI 50 195#define CLK_INFRA_SPINFI 51 196#define CLK_INFRA_66M_NFI_HCK 52 197#define CLK_INFRA_104M_SPI0 53 198#define CLK_INFRA_104M_SPI1 54 199#define CLK_INFRA_104M_SPI2_BCK 55 200#define CLK_INFRA_66M_SPI0_HCK 56 201#define CLK_INFRA_66M_SPI1_HCK 57 202#define CLK_INFRA_66M_SPI2_HCK 58 203#define CLK_INFRA_66M_FLASHIF_AXI 59 204#define CLK_INFRA_RTC 60 205#define CLK_INFRA_26M_ADC_BCK 61 206#define CLK_INFRA_RC_ADC 62 207#define CLK_INFRA_MSDC400 63 208#define CLK_INFRA_MSDC2_HCK 64 209#define CLK_INFRA_133M_MSDC_0_HCK 65 210#define CLK_INFRA_66M_MSDC_0_HCK 66 211#define CLK_INFRA_133M_CPUM_BCK 67 212#define CLK_INFRA_BIST2FPC 68 213#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 214#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 215#define CLK_INFRA_133M_USB_HCK 71 216#define CLK_INFRA_133M_USB_HCK_CK_P1 72 217#define CLK_INFRA_66M_USB_HCK 73 218#define CLK_INFRA_66M_USB_HCK_CK_P1 74 219#define CLK_INFRA_USB_SYS 75 220#define CLK_INFRA_USB_SYS_CK_P1 76 221#define CLK_INFRA_USB_REF 77 222#define CLK_INFRA_USB_CK_P1 78 223#define CLK_INFRA_USB_FRMCNT 79 224#define CLK_INFRA_USB_FRMCNT_CK_P1 80 225#define CLK_INFRA_USB_PIPE 81 226#define CLK_INFRA_USB_PIPE_CK_P1 82 227#define CLK_INFRA_USB_UTMI 83 228#define CLK_INFRA_USB_UTMI_CK_P1 84 229#define CLK_INFRA_USB_XHCI 85 230#define CLK_INFRA_USB_XHCI_CK_P1 86 231#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 232#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 233#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 234#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 235#define CLK_INFRA_PCIE_PIPE_P0 91 236#define CLK_INFRA_PCIE_PIPE_P1 92 237#define CLK_INFRA_PCIE_PIPE_P2 93 238#define CLK_INFRA_PCIE_PIPE_P3 94 239#define CLK_INFRA_133M_PCIE_CK_P0 95 240#define CLK_INFRA_133M_PCIE_CK_P1 96 241#define CLK_INFRA_133M_PCIE_CK_P2 97 242#define CLK_INFRA_133M_PCIE_CK_P3 98 243 244/* ETHDMA */ 245 246#define CLK_ETHDMA_XGP1_EN 0 247#define CLK_ETHDMA_XGP2_EN 1 248#define CLK_ETHDMA_XGP3_EN 2 249#define CLK_ETHDMA_FE_EN 3 250#define CLK_ETHDMA_GP2_EN 4 251#define CLK_ETHDMA_GP1_EN 5 252#define CLK_ETHDMA_GP3_EN 6 253#define CLK_ETHDMA_ESW_EN 7 254#define CLK_ETHDMA_CRYPT0_EN 8 255#define CLK_ETHDMA_NR_CLK 9 256 257/* SGMIISYS_0 */ 258 259#define CLK_SGM0_TX_EN 0 260#define CLK_SGM0_RX_EN 1 261#define CLK_SGMII0_NR_CLK 2 262 263/* SGMIISYS_1 */ 264 265#define CLK_SGM1_TX_EN 0 266#define CLK_SGM1_RX_EN 1 267#define CLK_SGMII1_NR_CLK 2 268 269/* ETHWARP */ 270 271#define CLK_ETHWARP_WOCPU2_EN 0 272#define CLK_ETHWARP_WOCPU1_EN 1 273#define CLK_ETHWARP_WOCPU0_EN 2 274#define CLK_ETHWARP_NR_CLK 3 275 276/* XFIPLL */ 277#define CLK_XFIPLL_PLL 0 278#define CLK_XFIPLL_PLL_EN 1 279 280#endif /* _DT_BINDINGS_CLK_MT7988_H */ 281