1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ 4 * Nikhil M Jain, n-jain1@ti.com 5 * 6 * based on the linux tidss driver, which is 7 * 8 * (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ 9 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 10 */ 11 12#ifndef __TIDSS_DRV_H__ 13#define __TIDSS_DRV_H__ 14 15#include <media_bus_format.h> 16 17#define TIDSS_MAX_PORTS 4 18#define TIDSS_MAX_PLANES 4 19 20enum dss_vp_bus_type { 21 DSS_VP_DPI, /* DPI output */ 22 DSS_VP_OLDI, /* OLDI (LVDS) output */ 23 DSS_VP_INTERNAL, /* SoC internal routing */ 24 DSS_VP_MAX_BUS_TYPE, 25}; 26 27enum dss_oldi_modes { 28 OLDI_MODE_OFF, /* OLDI turned off / tied off in IP. */ 29 OLDI_SINGLE_LINK_SINGLE_MODE, /* Single Output over OLDI 0. */ 30 OLDI_SINGLE_LINK_DUPLICATE_MODE, /* Duplicate Output over OLDI 0 and 1. */ 31 OLDI_DUAL_LINK, /* Combined Output over OLDI 0 and 1. */ 32}; 33 34struct dss_features_scaling { 35 u32 in_width_max_5tap_rgb; 36 u32 in_width_max_3tap_rgb; 37 u32 in_width_max_5tap_yuv; 38 u32 in_width_max_3tap_yuv; 39 u32 upscale_limit; 40 u32 downscale_limit_5tap; 41 u32 downscale_limit_3tap; 42 u32 xinc_max; 43}; 44 45enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; 46 47/* choose specific DSS based on the board */ 48enum dss_subrevision { 49 DSS_K2G, 50 DSS_AM65X, 51 DSS_J721E, 52 DSS_AM625, 53}; 54 55struct tidss_vp_feat { 56 struct tidss_vp_color_feat { 57 u32 gamma_size; 58 enum tidss_gamma_type gamma_type; 59 bool has_ctm; 60 } color; 61}; 62 63struct dss_color_lut { 64 /* 65 * Data is U0.16 fixed point format. 66 */ 67 __u16 red; 68 __u16 green; 69 __u16 blue; 70 __u16 reserved; 71}; 72 73struct dss_vp_data { 74 u32 *gamma_table; 75}; 76 77struct dss_features { 78 int min_pclk_khz; 79 int max_pclk_khz[DSS_VP_MAX_BUS_TYPE]; 80 81 struct dss_features_scaling scaling; 82 83 enum dss_subrevision subrev; 84 85 const char *common; 86 const u16 *common_regs; 87 u32 num_vps; 88 const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ 89 const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ 90 const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ 91 const enum dss_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; 92 struct tidss_vp_feat vp_feat; 93 u32 num_planes; 94 const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ 95 bool vid_lite[TIDSS_MAX_PLANES]; 96 u32 vid_order[TIDSS_MAX_PLANES]; 97}; 98 99enum dss_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; 100 101struct dss_bus_format { 102 u32 bus_fmt; 103 u32 data_width; 104 bool is_oldi_fmt; 105 enum dss_oldi_mode_reg_val oldi_mode_reg_val; 106}; 107 108static struct dss_bus_format dss_bus_formats[] = { 109 { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, 110 { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, 111 { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, 112 { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, 113 { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, 114 { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, 115 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, 116 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, 117 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, 118}; 119 120struct tidss_drv_priv { 121 struct udevice *dev; 122 void __iomem *base_common; /* common register region of dss*/ 123 void __iomem *base_vid[TIDSS_MAX_PLANES]; /* plane register region of dss*/ 124 void __iomem *base_ovr[TIDSS_MAX_PORTS]; /* overlay register region of dss*/ 125 void __iomem *base_vp[TIDSS_MAX_PORTS]; /* video port register region of dss*/ 126 struct regmap *oldi_io_ctrl; 127 struct clk vp_clk[TIDSS_MAX_PORTS]; 128 const struct dss_features *feat; 129 struct clk fclk; 130 struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; 131 enum dss_oldi_modes oldi_mode; 132 struct dss_bus_format *bus_format; 133 u32 pixel_format; 134 u32 memory_bandwidth_limit; 135}; 136 137#endif 138