1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  (C) Copyright 2010
4 *  NVIDIA Corporation <www.nvidia.com>
5 */
6
7#ifndef _TEGRA_DC_H
8#define _TEGRA_DC_H
9
10#ifndef __ASSEMBLY__
11#include <linux/bitops.h>
12#endif
13
14/* arch-tegra/dc exists only because T124 uses it */
15#include <asm/arch-tegra/dc.h>
16
17#define TEGRA_DC_A		"dc@54200000"
18#define TEGRA_DC_B		"dc@54240000"
19#define TEGRA_DSI_A		"dsi@54300000"
20#define TEGRA_DSI_B		"dsi@54400000"
21
22struct tegra_dc_plat {
23	struct udevice *dev;		/* Display controller device */
24	struct dc_ctlr *dc;		/* Display controller regmap */
25	bool pipe;			/* DC number: 0 for A, 1 for B */
26	ulong scdiv;			/* Shift clock divider */
27};
28
29/* This holds information about a window which can be displayed */
30struct disp_ctl_win {
31	enum win_color_depth_id fmt;	/* Color depth/format */
32	unsigned int bpp;		/* Bits per pixel */
33	phys_addr_t phys_addr;		/* Physical address in memory */
34	unsigned int x;			/* Horizontal address offset (bytes) */
35	unsigned int y;			/* Veritical address offset (bytes) */
36	unsigned int w;			/* Width of source window */
37	unsigned int h;			/* Height of source window */
38	unsigned int stride;		/* Number of bytes per line */
39	unsigned int out_x;		/* Left edge of output window (col) */
40	unsigned int out_y;		/* Top edge of output window (row) */
41	unsigned int out_w;		/* Width of output window in pixels */
42	unsigned int out_h;		/* Height of output window in pixels */
43};
44
45#endif /* _TEGRA_DC_H */
46