1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Nexell Co., Ltd. 4 * 5 * Author: junghyun, kim <jhkim@nexell.co.kr> 6 */ 7 8#include <linux/types.h> 9#include <linux/io.h> 10 11#include "s5pxx18_soc_dpc.h" 12 13static struct { 14 struct nx_dpc_register_set *pregister; 15} __g_module_variables[NUMBER_OF_DPC_MODULE] = { { NULL,},}; 16 17int nx_dpc_initialize(void) 18{ 19 static int binit; 20 u32 i; 21 22 if (binit == 0) { 23 for (i = 0; i < NUMBER_OF_DPC_MODULE; i++) 24 __g_module_variables[i].pregister = NULL; 25 binit = 1; 26 } 27 return 1; 28} 29 30u32 nx_dpc_get_number_of_module(void) 31{ 32 return NUMBER_OF_DPC_MODULE; 33} 34 35u32 nx_dpc_get_physical_address(u32 module_index) 36{ 37 const u32 physical_addr[] = PHY_BASEADDR_DPC_LIST; 38 39 return physical_addr[module_index]; 40} 41 42void nx_dpc_set_base_address(u32 module_index, void *base_address) 43{ 44 __g_module_variables[module_index].pregister = 45 (struct nx_dpc_register_set *)base_address; 46} 47 48void *nx_dpc_get_base_address(u32 module_index) 49{ 50 return (void *)__g_module_variables[module_index].pregister; 51} 52 53void nx_dpc_set_interrupt_enable(u32 module_index, int32_t int_num, int enable) 54{ 55 const u32 intenb_pos = 11; 56 const u32 intenb_mask = 1ul << intenb_pos; 57 const u32 intpend_pos = 10; 58 const u32 intpend_mask = 1ul << intpend_pos; 59 60 register u32 regvalue; 61 register struct nx_dpc_register_set *pregister; 62 63 pregister = __g_module_variables[module_index].pregister; 64 regvalue = pregister->dpcctrl0; 65 regvalue &= ~(intenb_mask | intpend_mask); 66 regvalue |= (u32)enable << intenb_pos; 67 68 writel(regvalue, &pregister->dpcctrl0); 69} 70 71int nx_dpc_get_interrupt_enable(u32 module_index, int32_t int_num) 72{ 73 const u32 intenb_pos = 11; 74 const u32 intenb_mask = 1ul << intenb_pos; 75 76 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & 77 intenb_mask) >> intenb_pos); 78} 79 80void nx_dpc_set_interrupt_enable32(u32 module_index, u32 enable_flag) 81{ 82 const u32 intenb_pos = 11; 83 const u32 intenb_mask = 1 << intenb_pos; 84 const u32 intpend_pos = 10; 85 const u32 intpend_mask = 1 << intpend_pos; 86 87 register struct nx_dpc_register_set *pregister; 88 register u32 read_value; 89 90 pregister = __g_module_variables[module_index].pregister; 91 read_value = pregister->dpcctrl0 & ~(intpend_mask | intenb_mask); 92 93 writel((u32)(read_value | (enable_flag & 0x01) << intenb_pos), 94 &pregister->dpcctrl0); 95} 96 97u32 nx_dpc_get_interrupt_enable32(u32 module_index) 98{ 99 const u32 intenb_pos = 11; 100 const u32 intenb_mask = 1 << intenb_pos; 101 102 return (u32)((__g_module_variables[module_index].pregister->dpcctrl0 & 103 intenb_mask) >> intenb_pos); 104} 105 106int nx_dpc_get_interrupt_pending(u32 module_index, int32_t int_num) 107{ 108 const u32 intpend_pos = 10; 109 const u32 intpend_mask = 1ul << intpend_pos; 110 111 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & 112 intpend_mask) >> intpend_pos); 113} 114 115u32 nx_dpc_get_interrupt_pending32(u32 module_index) 116{ 117 const u32 intpend_pos = 10; 118 const u32 intpend_mask = 1 << intpend_pos; 119 120 return (u32)((__g_module_variables[module_index].pregister->dpcctrl0 & 121 intpend_mask) >> intpend_pos); 122} 123 124void nx_dpc_clear_interrupt_pending(u32 module_index, int32_t int_num) 125{ 126 const u32 intpend_pos = 10; 127 register struct nx_dpc_register_set *pregister; 128 register u32 regvalue; 129 130 pregister = __g_module_variables[module_index].pregister; 131 regvalue = pregister->dpcctrl0; 132 regvalue |= 1ul << intpend_pos; 133 134 writel(regvalue, &pregister->dpcctrl0); 135} 136 137void nx_dpc_clear_interrupt_pending32(u32 module_index, u32 pending_flag) 138{ 139 const u32 intpend_pos = 10; 140 const u32 intpend_mask = 1 << intpend_pos; 141 register struct nx_dpc_register_set *pregister; 142 register u32 read_value; 143 144 pregister = __g_module_variables[module_index].pregister; 145 read_value = pregister->dpcctrl0 & ~intpend_mask; 146 147 writel((u32)(read_value | ((pending_flag & 0x01) << intpend_pos)), 148 &pregister->dpcctrl0); 149} 150 151void nx_dpc_set_interrupt_enable_all(u32 module_index, int enable) 152{ 153 const u32 intenb_pos = 11; 154 const u32 intenb_mask = 1ul << intenb_pos; 155 const u32 intpend_pos = 10; 156 const u32 intpend_mask = 1ul << intpend_pos; 157 register u32 regvalue; 158 register struct nx_dpc_register_set *pregister; 159 160 pregister = __g_module_variables[module_index].pregister; 161 regvalue = pregister->dpcctrl0; 162 regvalue &= ~(intenb_mask | intpend_mask); 163 regvalue |= (u32)enable << intenb_pos; 164 165 writel(regvalue, &pregister->dpcctrl0); 166} 167 168int nx_dpc_get_interrupt_enable_all(u32 module_index) 169{ 170 const u32 intenb_pos = 11; 171 const u32 intenb_mask = 1ul << intenb_pos; 172 173 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & 174 intenb_mask) >> intenb_pos); 175} 176 177int nx_dpc_get_interrupt_pending_all(u32 module_index) 178{ 179 const u32 intpend_pos = 10; 180 const u32 intpend_mask = 1ul << intpend_pos; 181 182 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & 183 intpend_mask) >> intpend_pos); 184} 185 186void nx_dpc_clear_interrupt_pending_all(u32 module_index) 187{ 188 const u32 intpend_pos = 10; 189 register struct nx_dpc_register_set *pregister; 190 register u32 regvalue; 191 192 pregister = __g_module_variables[module_index].pregister; 193 regvalue = pregister->dpcctrl0; 194 regvalue |= 1ul << intpend_pos; 195 196 writel(regvalue, &pregister->dpcctrl0); 197} 198 199int32_t nx_dpc_get_interrupt_pending_number(u32 module_index) 200{ 201 const u32 intenb_pos = 11; 202 const u32 intpend_pos = 10; 203 register struct nx_dpc_register_set *pregister; 204 register u32 pend; 205 206 pregister = __g_module_variables[module_index].pregister; 207 pend = ((pregister->dpcctrl0 >> intenb_pos) && 208 (pregister->dpcctrl0 >> intpend_pos)); 209 210 if (pend & 0x01) 211 return 0; 212 213 return -1; 214} 215 216void nx_dpc_set_clock_pclk_mode(u32 module_index, enum nx_pclkmode mode) 217{ 218 const u32 pclkmode_pos = 3; 219 register u32 regvalue; 220 register struct nx_dpc_register_set *pregister; 221 u32 clkmode = 0; 222 223 pregister = __g_module_variables[module_index].pregister; 224 switch (mode) { 225 case nx_pclkmode_dynamic: 226 clkmode = 0; 227 break; 228 case nx_pclkmode_always: 229 clkmode = 1; 230 break; 231 default: 232 break; 233 } 234 regvalue = pregister->dpcclkenb; 235 regvalue &= ~(1ul << pclkmode_pos); 236 regvalue |= (clkmode & 0x01) << pclkmode_pos; 237 238 writel(regvalue, &pregister->dpcclkenb); 239} 240 241enum nx_pclkmode nx_dpc_get_clock_pclk_mode(u32 module_index) 242{ 243 const u32 pclkmode_pos = 3; 244 245 if (__g_module_variables[module_index].pregister->dpcclkenb & 246 (1ul << pclkmode_pos)) { 247 return nx_pclkmode_always; 248 } 249 return nx_pclkmode_dynamic; 250} 251 252void nx_dpc_set_clock_source(u32 module_index, u32 index, u32 clk_src) 253{ 254 const u32 clksrcsel_pos = 2; 255 const u32 clksrcsel_mask = 0x07 << clksrcsel_pos; 256 register struct nx_dpc_register_set *pregister; 257 register u32 read_value; 258 259 pregister = __g_module_variables[module_index].pregister; 260 read_value = pregister->dpcclkgen[index][0]; 261 read_value &= ~clksrcsel_mask; 262 read_value |= clk_src << clksrcsel_pos; 263 264 writel(read_value, &pregister->dpcclkgen[index][0]); 265} 266 267u32 nx_dpc_get_clock_source(u32 module_index, u32 index) 268{ 269 const u32 clksrcsel_pos = 2; 270 const u32 clksrcsel_mask = 0x07 << clksrcsel_pos; 271 272 return (__g_module_variables[module_index] 273 .pregister->dpcclkgen[index][0] & 274 clksrcsel_mask) >> clksrcsel_pos; 275} 276 277void nx_dpc_set_clock_divisor(u32 module_index, u32 index, u32 divisor) 278{ 279 const u32 clkdiv_pos = 5; 280 const u32 clkdiv_mask = ((1 << 8) - 1) << clkdiv_pos; 281 register struct nx_dpc_register_set *pregister; 282 register u32 read_value; 283 284 pregister = __g_module_variables[module_index].pregister; 285 read_value = pregister->dpcclkgen[index][0]; 286 read_value &= ~clkdiv_mask; 287 read_value |= (divisor - 1) << clkdiv_pos; 288 289 writel(read_value, &pregister->dpcclkgen[index][0]); 290} 291 292u32 nx_dpc_get_clock_divisor(u32 module_index, u32 index) 293{ 294 const u32 clkdiv_pos = 5; 295 const u32 clkdiv_mask = ((1 << 8) - 1) << clkdiv_pos; 296 297 return ((__g_module_variables[module_index] 298 .pregister->dpcclkgen[index][0] & 299 clkdiv_mask) >> clkdiv_pos) + 1; 300} 301 302void nx_dpc_set_clock_out_inv(u32 module_index, u32 index, int out_clk_inv) 303{ 304 const u32 outclkinv_pos = 1; 305 const u32 outclkinv_mask = 1ul << outclkinv_pos; 306 register struct nx_dpc_register_set *pregister; 307 register u32 read_value; 308 309 pregister = __g_module_variables[module_index].pregister; 310 read_value = pregister->dpcclkgen[index][0]; 311 read_value &= ~outclkinv_mask; 312 read_value |= out_clk_inv << outclkinv_pos; 313 314 writel(read_value, &pregister->dpcclkgen[index][0]); 315} 316 317int nx_dpc_get_clock_out_inv(u32 module_index, u32 index) 318{ 319 const u32 outclkinv_pos = 1; 320 const u32 outclkinv_mask = 1ul << outclkinv_pos; 321 322 return (int)((__g_module_variables[module_index] 323 .pregister->dpcclkgen[index][0] & 324 outclkinv_mask) >> outclkinv_pos); 325} 326 327void nx_dpc_set_clock_out_select(u32 module_index, u32 index, int bbypass) 328{ 329 const u32 outclksel_pos = 0; 330 const u32 outclksel_mask = 1ul << outclksel_pos; 331 register struct nx_dpc_register_set *pregister; 332 register u32 read_value; 333 334 pregister = __g_module_variables[module_index].pregister; 335 read_value = pregister->dpcclkgen[index][0]; 336 read_value &= ~outclksel_mask; 337 if (bbypass == 0) 338 read_value |= outclksel_mask; 339 340 writel(read_value, &pregister->dpcclkgen[index][0]); 341} 342 343int nx_dpc_get_clock_out_select(u32 module_index, u32 index) 344{ 345 const u32 outclksel_pos = 0; 346 const u32 outclksel_mask = 1ul << outclksel_pos; 347 348 if (__g_module_variables[module_index].pregister->dpcclkgen[index][0] & 349 outclksel_mask) { 350 return 0; 351 } else { 352 return 1; 353 } 354} 355 356void nx_dpc_set_clock_polarity(u32 module_index, int bpolarity) 357{ 358 const u32 clkpol_pos = 2; 359 const u32 clkpol_mask = 1ul << clkpol_pos; 360 register struct nx_dpc_register_set *pregister; 361 register u32 read_value; 362 363 pregister = __g_module_variables[module_index].pregister; 364 read_value = pregister->dpcctrl1; 365 read_value &= ~clkpol_mask; 366 if (bpolarity == 1) 367 read_value |= clkpol_mask; 368 369 writel(read_value, &pregister->dpcctrl1); 370} 371 372int nx_dpc_get_clock_polarity(u32 module_index) 373{ 374 const u32 clkpol_pos = 2; 375 const u32 clkpol_mask = 1ul << clkpol_pos; 376 377 if (__g_module_variables[module_index].pregister->dpcctrl1 & 378 clkpol_mask) { 379 return 1; 380 } else { 381 return 0; 382 } 383} 384 385void nx_dpc_set_clock_out_enb(u32 module_index, u32 index, int out_clk_enb) 386{ 387 const u32 outclkenb_pos = 15; 388 const u32 outclkenb_mask = 1ul << outclkenb_pos; 389 register struct nx_dpc_register_set *pregister; 390 register u32 read_value; 391 392 pregister = __g_module_variables[module_index].pregister; 393 read_value = pregister->dpcclkgen[index][0]; 394 read_value &= ~outclkenb_mask; 395 396 if (out_clk_enb == 1) 397 read_value |= outclkenb_mask; 398 399 writel(read_value, &pregister->dpcclkgen[index][0]); 400} 401 402int nx_dpc_get_clock_out_enb(u32 module_index, u32 index) 403{ 404 const u32 outclkenb_pos = 15; 405 const u32 outclkenb_mask = 1ul << outclkenb_pos; 406 407 if (__g_module_variables[module_index].pregister->dpcclkgen[index][0] & 408 outclkenb_mask) { 409 return 1; 410 } else { 411 return 0; 412 } 413} 414 415void nx_dpc_set_clock_out_delay(u32 module_index, u32 index, u32 delay) 416{ 417 const u32 outclkdelay_pos = 0; 418 const u32 outclkdelay_mask = 0x1f << outclkdelay_pos; 419 register struct nx_dpc_register_set *pregister; 420 register u32 read_value; 421 422 pregister = __g_module_variables[module_index].pregister; 423 read_value = pregister->dpcclkgen[index][1]; 424 read_value &= ~outclkdelay_mask; 425 read_value |= (u32)delay << outclkdelay_pos; 426 427 writel(read_value, &pregister->dpcclkgen[index][1]); 428} 429 430u32 nx_dpc_get_clock_out_delay(u32 module_index, u32 index) 431{ 432 register struct nx_dpc_register_set *pregister; 433 const u32 outclkdelay_pos = 0; 434 const u32 outclkdelay_mask = 0x1f << outclkdelay_pos; 435 436 pregister = __g_module_variables[module_index].pregister; 437 438 return (u32)((pregister->dpcclkgen[index][1] & outclkdelay_mask) >> 439 outclkdelay_pos); 440} 441 442void nx_dpc_set_clock_divisor_enable(u32 module_index, int enable) 443{ 444 const u32 clkgenenb_pos = 2; 445 const u32 clkgenenb_mask = 1ul << clkgenenb_pos; 446 register struct nx_dpc_register_set *pregister; 447 register u32 read_value; 448 449 pregister = __g_module_variables[module_index].pregister; 450 read_value = pregister->dpcclkenb; 451 read_value &= ~clkgenenb_mask; 452 read_value |= (u32)enable << clkgenenb_pos; 453 454 writel(read_value, &pregister->dpcclkenb); 455} 456 457int nx_dpc_get_clock_divisor_enable(u32 module_index) 458{ 459 const u32 clkgenenb_pos = 2; 460 const u32 clkgenenb_mask = 1ul << clkgenenb_pos; 461 462 return (int)((__g_module_variables[module_index].pregister->dpcclkenb & 463 clkgenenb_mask) >> clkgenenb_pos); 464} 465 466void nx_dpc_set_dpc_enable(u32 module_index, int benb) 467{ 468 const u32 intpend_pos = 10; 469 const u32 intpend_mask = 1ul << intpend_pos; 470 const u32 dpcenb_pos = 15; 471 const u32 dpcenb_mask = 1ul << dpcenb_pos; 472 register struct nx_dpc_register_set *pregister; 473 register u32 read_value; 474 475 pregister = __g_module_variables[module_index].pregister; 476 read_value = pregister->dpcctrl0; 477 read_value &= ~(intpend_mask | dpcenb_mask); 478 read_value |= (u32)benb << dpcenb_pos; 479 480 writel(read_value, &pregister->dpcctrl0); 481} 482 483int nx_dpc_get_dpc_enable(u32 module_index) 484{ 485 const u32 dpcenb_pos = 15; 486 const u32 dpcenb_mask = 1ul << dpcenb_pos; 487 488 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & 489 dpcenb_mask) >> dpcenb_pos); 490} 491 492void nx_dpc_set_delay(u32 module_index, u32 delay_rgb_pvd, u32 delay_hs_cp1, 493 u32 delay_vs_fram, u32 delay_de_cp2) 494{ 495 const u32 intpend_mask = 1u << 10; 496 const u32 delayrgb_pos = 4; 497 const u32 delayrgb_mask = 0xfu << delayrgb_pos; 498 register u32 temp; 499 const u32 delayde_pos = 0; 500 const u32 delayvs_pos = 8; 501 const u32 delayhs_pos = 0; 502 register struct nx_dpc_register_set *pregister; 503 504 pregister = __g_module_variables[module_index].pregister; 505 temp = pregister->dpcctrl0; 506 temp &= (u32)~(intpend_mask | delayrgb_mask); 507 temp = (u32)(temp | (delay_rgb_pvd << delayrgb_pos)); 508 509 writel(temp, &pregister->dpcctrl0); 510 511 writel((u32)((delay_vs_fram << delayvs_pos) | 512 (delay_hs_cp1 << delayhs_pos)), &pregister->dpcdelay0); 513 514 writel((u32)(delay_de_cp2 << delayde_pos), &pregister->dpcdelay1); 515} 516 517void nx_dpc_get_delay(u32 module_index, u32 *pdelayrgb_pvd, u32 *pdelayhs_cp1, 518 u32 *pdelayvs_fram, u32 *pdelayde_cp2) 519{ 520 const u32 delayrgb_pos = 4; 521 const u32 delayrgb_mask = 0xfu << delayrgb_pos; 522 const u32 delayde_pos = 0; 523 const u32 delayde_mask = 0x3fu << delayde_pos; 524 const u32 delayvs_pos = 8; 525 const u32 delayvs_mask = 0x3fu << delayvs_pos; 526 const u32 delayhs_pos = 0; 527 const u32 delayhs_mask = 0x3fu << delayhs_pos; 528 register u32 temp; 529 530 temp = __g_module_variables[module_index].pregister->dpcctrl0; 531 if (pdelayrgb_pvd) 532 *pdelayrgb_pvd = (u32)((temp & delayrgb_mask) >> delayrgb_pos); 533 temp = __g_module_variables[module_index].pregister->dpcdelay0; 534 if (pdelayhs_cp1) 535 *pdelayhs_cp1 = (u32)((temp & delayhs_mask) >> delayhs_pos); 536 if (pdelayvs_fram) 537 *pdelayvs_fram = (u32)((temp & delayvs_mask) >> delayvs_pos); 538 temp = __g_module_variables[module_index].pregister->dpcdelay1; 539 if (pdelayde_cp2) 540 *pdelayde_cp2 = (u32)((temp & delayde_mask) >> delayde_pos); 541} 542 543void nx_dpc_set_dither(u32 module_index, enum nx_dpc_dither dither_r, 544 enum nx_dpc_dither dither_g, enum nx_dpc_dither dither_b) 545{ 546 const u32 dither_mask = 0x3fu; 547 const u32 rdither_pos = 0; 548 const u32 gdither_pos = 2; 549 const u32 bdither_pos = 4; 550 register u32 temp; 551 register struct nx_dpc_register_set *pregister; 552 553 pregister = __g_module_variables[module_index].pregister; 554 temp = pregister->dpcctrl1; 555 temp &= (u32)~dither_mask; 556 temp = (u32)(temp | 557 ((dither_b << bdither_pos) | (dither_g << gdither_pos) | 558 (dither_r << rdither_pos))); 559 560 writel(temp, &pregister->dpcctrl1); 561} 562 563void nx_dpc_get_dither(u32 module_index, enum nx_dpc_dither *pditherr, 564 enum nx_dpc_dither *pditherg, 565 enum nx_dpc_dither *pditherb) 566{ 567 const u32 rdither_pos = 0; 568 const u32 rdither_mask = 0x3u << rdither_pos; 569 const u32 gdither_pos = 2; 570 const u32 gdither_mask = 0x3u << gdither_pos; 571 const u32 bdither_pos = 4; 572 const u32 bdither_mask = 0x3u << bdither_pos; 573 register u32 temp; 574 575 temp = __g_module_variables[module_index].pregister->dpcctrl1; 576 if (pditherr) 577 *pditherr = 578 (enum nx_dpc_dither)((temp & rdither_mask) >> rdither_pos); 579 if (pditherg) 580 *pditherg = 581 (enum nx_dpc_dither)((temp & gdither_mask) >> gdither_pos); 582 if (pditherb) 583 *pditherb = 584 (enum nx_dpc_dither)((temp & bdither_mask) >> bdither_pos); 585} 586 587void nx_dpc_set_mode(u32 module_index, enum nx_dpc_format format, 588 int binterlace, int binvertfield, int brgbmode, 589 int bswaprb, enum nx_dpc_ycorder ycorder, int bclipyc, 590 int bembeddedsync, enum nx_dpc_padclk clock, 591 int binvertclock, int bdualview) 592{ 593 const u32 polfield_pos = 2; 594 const u32 seavenb_pos = 8; 595 const u32 scanmode_pos = 9; 596 const u32 intpend_pos = 10; 597 const u32 rgbmode_pos = 12; 598 599 const u32 dither_mask = 0x3f; 600 const u32 ycorder_pos = 6; 601 const u32 format_pos = 8; 602 const u32 ycrange_pos = 13; 603 const u32 swaprb_pos = 15; 604 605 const u32 padclksel_pos = 0; 606 const u32 padclksel_mask = 3u << padclksel_pos; 607 const u32 lcdtype_pos = 7; 608 const u32 lcdtype_mask = 3u << lcdtype_pos; 609 register struct nx_dpc_register_set *pregister; 610 register u32 temp; 611 612 pregister = __g_module_variables[module_index].pregister; 613 temp = pregister->dpcctrl0; 614 temp &= (u32)~(1u << intpend_pos); 615 if (binterlace) 616 temp |= (u32)(1u << scanmode_pos); 617 else 618 temp &= (u32)~(1u << scanmode_pos); 619 if (binvertfield) 620 temp |= (u32)(1u << polfield_pos); 621 else 622 temp &= (u32)~(1u << polfield_pos); 623 if (brgbmode) 624 temp |= (u32)(1u << rgbmode_pos); 625 else 626 temp &= (u32)~(1u << rgbmode_pos); 627 if (bembeddedsync) 628 temp |= (u32)(1u << seavenb_pos); 629 else 630 temp &= (u32)~(1u << seavenb_pos); 631 632 writel(temp, &pregister->dpcctrl0); 633 temp = pregister->dpcctrl1; 634 temp &= (u32)dither_mask; 635 temp = (u32)(temp | (ycorder << ycorder_pos)); 636 if (format >= 16) { 637 register u32 temp1; 638 639 temp1 = pregister->dpcctrl2; 640 temp1 = temp1 | (1 << 4); 641 writel(temp1, &pregister->dpcctrl2); 642 } else { 643 register u32 temp1; 644 645 temp1 = pregister->dpcctrl2; 646 temp1 = temp1 & ~(1 << 4); 647 writel(temp1, &pregister->dpcctrl2); 648 } 649 temp = (u32)(temp | ((format & 0xf) << format_pos)); 650 if (!bclipyc) 651 temp |= (u32)(1u << ycrange_pos); 652 if (bswaprb) 653 temp |= (u32)(1u << swaprb_pos); 654 655 writel(temp, &pregister->dpcctrl1); 656 temp = pregister->dpcctrl2; 657 temp &= (u32)~(padclksel_mask | lcdtype_mask); 658 temp = (u32)(temp | (clock << padclksel_pos)); 659 660 writel(temp, &pregister->dpcctrl2); 661 662 nx_dpc_set_clock_out_inv(module_index, 0, binvertclock); 663 nx_dpc_set_clock_out_inv(module_index, 1, binvertclock); 664} 665 666void nx_dpc_get_mode(u32 module_index, enum nx_dpc_format *pformat, 667 int *pbinterlace, int *pbinvertfield, int *pbrgbmode, 668 int *pbswaprb, enum nx_dpc_ycorder *pycorder, 669 int *pbclipyc, int *pbembeddedsync, 670 enum nx_dpc_padclk *pclock, int *pbinvertclock, 671 int *pbdualview) 672{ 673 const u32 polfield = 1u << 2; 674 const u32 seavenb = 1u << 8; 675 const u32 scanmode = 1u << 9; 676 const u32 rgbmode = 1u << 12; 677 678 const u32 ycorder_pos = 6; 679 const u32 ycorder_mask = 0x3u << ycorder_pos; 680 const u32 format_pos = 8; 681 const u32 format_mask = 0xfu << format_pos; 682 const u32 ycrange = 1u << 13; 683 const u32 swaprb = 1u << 15; 684 685 const u32 padclksel_pos = 0; 686 const u32 padclksel_mask = 3u << padclksel_pos; 687 const u32 lcdtype_pos = 7; 688 const u32 lcdtype_mask = 3u << lcdtype_pos; 689 register u32 temp; 690 691 temp = __g_module_variables[module_index].pregister->dpcctrl0; 692 if (pbinterlace) 693 *pbinterlace = (temp & scanmode) ? 1 : 0; 694 695 if (pbinvertfield) 696 *pbinvertfield = (temp & polfield) ? 1 : 0; 697 698 if (pbrgbmode) 699 *pbrgbmode = (temp & rgbmode) ? 1 : 0; 700 701 if (pbembeddedsync) 702 *pbembeddedsync = (temp & seavenb) ? 1 : 0; 703 704 temp = __g_module_variables[module_index].pregister->dpcctrl1; 705 706 if (pycorder) 707 *pycorder = 708 (enum nx_dpc_ycorder)((temp & ycorder_mask) >> ycorder_pos); 709 710 if (pformat) 711 *pformat = 712 (enum nx_dpc_format)((temp & format_mask) >> format_pos); 713 if (pbclipyc) 714 *pbclipyc = (temp & ycrange) ? 0 : 1; 715 if (pbswaprb) 716 *pbswaprb = (temp & swaprb) ? 1 : 0; 717 718 temp = __g_module_variables[module_index].pregister->dpcctrl2; 719 720 if (pclock) 721 *pclock = 722 (enum nx_dpc_padclk)((temp & padclksel_mask) >> 723 padclksel_pos); 724 725 if (pbdualview) 726 *pbdualview = (2 == ((temp & lcdtype_mask) >> lcdtype_pos)) 727 ? 1 : 0; 728 729 if (pbinvertclock) 730 *pbinvertclock = nx_dpc_get_clock_out_inv(module_index, 1); 731} 732 733void nx_dpc_set_hsync(u32 module_index, u32 avwidth, u32 hsw, u32 hfp, u32 hbp, 734 int binvhsync) 735{ 736 const u32 intpend = 1u << 10; 737 const u32 polhsync = 1u << 0; 738 register u32 temp; 739 register struct nx_dpc_register_set *pregister; 740 741 pregister = __g_module_variables[module_index].pregister; 742 743 writel((u32)(hsw + hbp + avwidth + hfp - 1), &pregister->dpchtotal); 744 745 writel((u32)(hsw - 1), &pregister->dpchswidth); 746 747 writel((u32)(hsw + hbp - 1), &pregister->dpchastart); 748 749 writel((u32)(hsw + hbp + avwidth - 1), &pregister->dpchaend); 750 temp = pregister->dpcctrl0; 751 temp &= ~intpend; 752 if (binvhsync) 753 temp |= (u32)polhsync; 754 else 755 temp &= (u32)~polhsync; 756 757 writel(temp, &pregister->dpcctrl0); 758} 759 760void nx_dpc_get_hsync(u32 module_index, u32 *pavwidth, u32 *phsw, u32 *phfp, 761 u32 *phbp, int *pbinvhsync) 762{ 763 const u32 polhsync = 1u << 0; 764 u32 htotal, hsw, hab, hae; 765 u32 avw, hfp, hbp; 766 register struct nx_dpc_register_set *pregister; 767 768 pregister = __g_module_variables[module_index].pregister; 769 htotal = (u32)pregister->dpchtotal + 1; 770 hsw = (u32)pregister->dpchswidth + 1; 771 hab = (u32)pregister->dpchastart + 1; 772 hae = (u32)pregister->dpchaend + 1; 773 hbp = hab - hsw; 774 avw = hae - hab; 775 hfp = htotal - hae; 776 if (pavwidth) 777 *pavwidth = avw; 778 if (phsw) 779 *phsw = hsw; 780 if (phfp) 781 *phfp = hfp; 782 if (phbp) 783 *phbp = hbp; 784 if (pbinvhsync) 785 *pbinvhsync = (pregister->dpcctrl0 & polhsync) ? 1 : 0; 786} 787 788void nx_dpc_set_vsync(u32 module_index, u32 avheight, u32 vsw, u32 vfp, u32 vbp, 789 int binvvsync, u32 eavheight, u32 evsw, u32 evfp, 790 u32 evbp) 791{ 792 const u32 intpend = 1u << 10; 793 const u32 polvsync = 1u << 1; 794 register u32 temp; 795 register struct nx_dpc_register_set *pregister; 796 797 pregister = __g_module_variables[module_index].pregister; 798 799 writel((u32)(vsw + vbp + avheight + vfp - 1), &pregister->dpcvtotal); 800 801 writel((u32)(vsw - 1), &pregister->dpcvswidth); 802 803 writel((u32)(vsw + vbp - 1), &pregister->dpcvastart); 804 805 writel((u32)(vsw + vbp + avheight - 1), &pregister->dpcvaend); 806 807 writel((u32)(evsw + evbp + eavheight + evfp - 1), 808 &pregister->dpcevtotal); 809 810 writel((u32)(evsw - 1), &pregister->dpcevswidth); 811 812 writel((u32)(evsw + evbp - 1), &pregister->dpcevastart); 813 814 writel((u32)(evsw + evbp + eavheight - 1), &pregister->dpcevaend); 815 temp = pregister->dpcctrl0; 816 temp &= ~intpend; 817 if (binvvsync) 818 temp |= (u32)polvsync; 819 else 820 temp &= (u32)~polvsync; 821 822 writel(temp, &pregister->dpcctrl0); 823} 824 825void nx_dpc_get_vsync(u32 module_index, u32 *pavheight, u32 *pvsw, u32 *pvfp, 826 u32 *pvbp, int *pbinvvsync, u32 *peavheight, 827 u32 *pevsw, u32 *pevfp, u32 *pevbp) 828{ 829 const u32 polvsync = 1u << 1; 830 u32 vtotal, vsw, vab, vae; 831 u32 avh, vfp, vbp; 832 register struct nx_dpc_register_set *pregister; 833 834 pregister = __g_module_variables[module_index].pregister; 835 vtotal = (u32)pregister->dpcvtotal + 1; 836 vsw = (u32)pregister->dpcvswidth + 1; 837 vab = (u32)pregister->dpcvastart + 1; 838 vae = (u32)pregister->dpcvaend + 1; 839 vbp = vab - vsw; 840 avh = vae - vab; 841 vfp = vtotal - vae; 842 if (pavheight) 843 *pavheight = avh; 844 if (pvsw) 845 *pvsw = vsw; 846 if (pvfp) 847 *pvfp = vfp; 848 if (pvbp) 849 *pvbp = vbp; 850 vtotal = (u32)pregister->dpcevtotal + 1; 851 vsw = (u32)pregister->dpcevswidth + 1; 852 vab = (u32)pregister->dpcevastart + 1; 853 vae = (u32)pregister->dpcevaend + 1; 854 vbp = vab - vsw; 855 avh = vae - vab; 856 vfp = vtotal - vae; 857 if (peavheight) 858 *peavheight = avh; 859 if (pevsw) 860 *pevsw = vsw; 861 if (pevfp) 862 *pevfp = vfp; 863 if (pevbp) 864 *pevbp = vbp; 865 if (pbinvvsync) 866 *pbinvvsync = (pregister->dpcctrl0 & polvsync) ? 1 : 0; 867} 868 869void nx_dpc_set_vsync_offset(u32 module_index, u32 vssoffset, u32 vseoffset, 870 u32 evssoffset, u32 evseoffset) 871{ 872 register struct nx_dpc_register_set *pregister; 873 874 pregister = __g_module_variables[module_index].pregister; 875 876 writel((u32)vseoffset, &pregister->dpcvseoffset); 877 878 writel((u32)vssoffset, &pregister->dpcvssoffset); 879 880 writel((u32)evseoffset, &pregister->dpcevseoffset); 881 882 writel((u32)evssoffset, &pregister->dpcevssoffset); 883} 884 885void nx_dpc_get_vsync_offset(u32 module_index, u32 *pvssoffset, 886 u32 *pvseoffset, u32 *pevssoffset, 887 u32 *pevseoffset) 888{ 889 register struct nx_dpc_register_set *pregister; 890 891 pregister = __g_module_variables[module_index].pregister; 892 893 if (pvseoffset) 894 *pvseoffset = (u32)pregister->dpcvseoffset; 895 896 if (pvssoffset) 897 *pvssoffset = (u32)pregister->dpcvssoffset; 898 899 if (pevseoffset) 900 *pevseoffset = (u32)pregister->dpcevseoffset; 901 902 if (pevssoffset) 903 *pevssoffset = (u32)pregister->dpcevssoffset; 904} 905 906void nx_dpc_set_horizontal_up_scaler(u32 module_index, int benb, 907 u32 sourcewidth, u32 destwidth) 908{ 909 const u32 upscalel_pos = 8; 910 const u32 upscaleh_pos = 0; 911 const u32 upscaleh_mask = ((1 << 15) - 1) << upscaleh_pos; 912 const u32 upscalerenb_pos = 0; 913 register struct nx_dpc_register_set *pregister; 914 register u32 regvalue; 915 register u32 up_scale; 916 917 pregister = __g_module_variables[module_index].pregister; 918 up_scale = ((sourcewidth - 1) * (1 << 11)) / (destwidth - 1); 919 regvalue = 0; 920 regvalue |= (((u32)benb << upscalerenb_pos) | 921 (up_scale & 0xff) << upscalel_pos); 922 923 writel(regvalue, &pregister->dpcupscalecon0); 924 925 writel((up_scale >> 0x08) & upscaleh_mask, &pregister->dpcupscalecon1); 926 927 writel(sourcewidth - 1, &pregister->dpcupscalecon2); 928} 929 930void nx_dpc_get_horizontal_up_scaler(u32 module_index, int *pbenb, 931 u32 *psourcewidth, u32 *pdestwidth) 932{ 933 const u32 upscalerenb_pos = 0; 934 const u32 upscalerenb_mask = 1u << upscalerenb_pos; 935 register struct nx_dpc_register_set *pregister; 936 937 u32 up_scale; 938 u32 destwidth, srcwidth; 939 940 pregister = __g_module_variables[module_index].pregister; 941 up_scale = ((u32)(pregister->dpcupscalecon1 & 0x7fff) << 8) | 942 ((u32)(pregister->dpcupscalecon0 >> 8) & 0xff); 943 srcwidth = pregister->dpcupscalecon2; 944 destwidth = (srcwidth * (1 << 11)) / up_scale; 945 if (pbenb) 946 *pbenb = (pregister->dpcupscalecon0 & upscalerenb_mask); 947 if (psourcewidth) 948 *psourcewidth = srcwidth + 1; 949 if (pdestwidth) 950 *pdestwidth = destwidth + 1; 951} 952 953void nx_dpc_set_sync(u32 module_index, enum syncgenmode sync_gen_mode, 954 u32 avwidth, u32 avheight, u32 hsw, u32 hfp, u32 hbp, 955 u32 vsw, u32 vfp, u32 vbp, enum polarity field_polarity, 956 enum polarity hsyncpolarity, enum polarity vsyncpolarity, 957 u32 even_vsw, u32 even_vfp, u32 even_vbp, u32 vsetpixel, 958 u32 vsclrpixel, u32 evenvsetpixel, u32 evenvsclrpixel) 959{ 960 register struct nx_dpc_register_set *pregister; 961 u32 regvalue = 0; 962 963 pregister = __g_module_variables[module_index].pregister; 964 965 writel((u32)(hfp + hsw + hbp + avwidth - 1), &pregister->dpchtotal); 966 writel((u32)(hsw - 1), &pregister->dpchswidth); 967 writel((u32)(hsw + hbp - 1), &pregister->dpchastart); 968 writel((u32)(hsw + hbp + avwidth - 1), &pregister->dpchaend); 969 writel((u32)(vfp + vsw + vbp + avheight - 1), &pregister->dpcvtotal); 970 writel((u32)(vsw - 1), &pregister->dpcvswidth); 971 writel((u32)(vsw + vbp - 1), &pregister->dpcvastart); 972 writel((u32)(vsw + vbp + avheight - 1), &pregister->dpcvaend); 973 writel((u32)vsetpixel, &pregister->dpcvseoffset); 974 writel((u32)(hfp + hsw + hbp + avwidth - vsclrpixel - 1), 975 &pregister->dpcvssoffset); 976 writel((u32)evenvsetpixel, &pregister->dpcevseoffset); 977 writel((u32)(hfp + hsw + hbp + avwidth - evenvsclrpixel - 1), 978 &pregister->dpcevssoffset); 979 if (sync_gen_mode == 1) { 980 writel((u32)(even_vfp + even_vsw + even_vbp + avheight - 1), 981 &pregister->dpcevtotal); 982 writel((u32)(even_vsw - 1), &pregister->dpcevswidth); 983 writel((u32)(even_vsw + even_vbp - 1), 984 &pregister->dpcevastart); 985 writel((u32)(even_vsw + even_vbp + avheight - 1), 986 &pregister->dpcevaend); 987 } 988 regvalue = readl(&pregister->dpcctrl0) & 0xfff0ul; 989 regvalue |= (((u32)field_polarity << 2) | ((u32)vsyncpolarity << 1) | 990 ((u32)hsyncpolarity << 0)); 991 writel((u32)regvalue, &pregister->dpcctrl0); 992} 993 994void nx_dpc_set_output_format(u32 module_index, enum outputformat output_format, 995 u8 output_video_config) 996{ 997 const u32 format_table[] = { 998 (0 << 0), (1 << 0), (2 << 0), (3 << 0), (4 << 0), (5 << 0), 999 (6 << 0), (7 << 0), (8 << 0), (9 << 0), (0 << 0) | (1 << 7), 1000 (1 << 0) | (1 << 7), (2 << 0) | (1 << 7), (3 << 0) | (1 << 7), 1001 (4 << 0) | (1 << 7), (5 << 0) | (1 << 7), (6 << 0) | (1 << 7), 1002 (7 << 0) | (1 << 7), (8 << 0) | (1 << 7), (9 << 0) | (1 << 7), 1003 (10 << 0), (11 << 0), (12 << 0), (13 << 0), (14 << 0), (15 << 0) 1004 }; 1005 u32 regvalue; 1006 u32 regvalue0; 1007 register struct nx_dpc_register_set *pregister; 1008 1009 pregister = __g_module_variables[module_index].pregister; 1010 regvalue = readl(&pregister->dpcctrl1) & 0x30fful; 1011 1012 regvalue |= (format_table[output_format] << 8); 1013 writel((u32)regvalue, &pregister->dpcctrl1); 1014 regvalue0 = (u32)(readl(&pregister->dpcctrl1) & 0xff3f); 1015 regvalue0 = (u32)((output_video_config << 6) | regvalue0); 1016 writel((u32)regvalue0, &pregister->dpcctrl1); 1017} 1018 1019void nx_dpc_set_quantization_mode(u32 module_index, enum qmode rgb2yc, 1020 enum qmode yc2rgb) 1021{ 1022 register struct nx_dpc_register_set *pregister; 1023 u32 regvalue; 1024 1025 pregister = __g_module_variables[module_index].pregister; 1026 regvalue = readl(&pregister->dpcctrl1) & 0x8ffful; 1027 regvalue |= ((u32)rgb2yc << 13) | ((u32)yc2rgb << 12); 1028 writel((u32)regvalue, &pregister->dpcctrl1); 1029} 1030 1031void nx_dpc_set_enable(u32 module_index, int enable, int rgbmode, 1032 int use_ntscsync, int use_analog_output, int seavenable) 1033{ 1034 u32 regvalue; 1035 register struct nx_dpc_register_set *pregister; 1036 1037 pregister = __g_module_variables[module_index].pregister; 1038 regvalue = readl(&pregister->dpcctrl0) & 0x0efful; 1039 regvalue |= ((u32)enable << 15) | ((u32)use_ntscsync << 14) | 1040 ((u32)seavenable << 8) | ((u32)use_analog_output << 13) | 1041 ((u32)rgbmode << 12); 1042 writel((u32)regvalue, &pregister->dpcctrl0); 1043} 1044 1045void nx_dpc_set_out_video_clk_select(u32 module_index, 1046 enum outpadclksel out_pad_vclk_sel) 1047{ 1048 register struct nx_dpc_register_set *pregister; 1049 1050 pregister = __g_module_variables[module_index].pregister; 1051 1052 writel((u32)((readl(&pregister->dpcctrl2)) | (out_pad_vclk_sel & 0x3)), 1053 &pregister->dpcctrl2); 1054} 1055 1056void nx_dpc_set_reg_flush(u32 module_index) 1057{ 1058 u32 reg; 1059 register struct nx_dpc_register_set *pregister; 1060 1061 pregister = __g_module_variables[module_index].pregister; 1062 reg = readl(&pregister->dpcdataflush); 1063 writel((u32)(reg | (1ul << 4)), &pregister->dpcdataflush); 1064} 1065 1066void nx_dpc_set_sramon(u32 module_index) 1067{ 1068 u32 reg; 1069 register struct nx_dpc_register_set *pregister; 1070 1071 pregister = __g_module_variables[module_index].pregister; 1072 reg = (u32)(readl(&pregister->dpcctrl2) & 0xf3ff); 1073 writel((u32)(reg | (1ul << 10)), &pregister->dpcctrl2); 1074 reg = (u32)(readl(&pregister->dpcctrl2) & 0xf7ff); 1075 writel((u32)(reg | (1ul << 11)), &pregister->dpcctrl2); 1076} 1077 1078void nx_dpc_set_sync_lcdtype(u32 module_index, int stnlcd, int dual_view_enb, 1079 int bit_widh, u8 cpcycle) 1080{ 1081 u32 reg; 1082 register struct nx_dpc_register_set *pregister; 1083 1084 pregister = __g_module_variables[module_index].pregister; 1085 1086 reg = (u32)(readl(&pregister->dpcctrl2) & 0xc0f); 1087 writel((u32)(reg | (cpcycle << 12) | (bit_widh << 9) | 1088 (dual_view_enb << 8) | (stnlcd << 7)), 1089 &pregister->dpcctrl2); 1090} 1091 1092void nx_dpc_set_up_scale_control(u32 module_index, int up_scale_enb, 1093 int filter_enb, u32 hscale, u16 source_width) 1094{ 1095 register struct nx_dpc_register_set *pregister; 1096 1097 pregister = __g_module_variables[module_index].pregister; 1098 writel((u32)((hscale << 8) | ((u32)filter_enb << 1) | (up_scale_enb)), 1099 &pregister->dpcupscalecon0); 1100 writel((u32)(hscale >> 8), &pregister->dpcupscalecon1); 1101 writel(source_width, &pregister->dpcupscalecon2); 1102} 1103 1104void nx_dpc_set_mputime(u32 module_index, u8 setup, u8 hold, u8 acc) 1105{ 1106 register struct nx_dpc_register_set *pregister; 1107 1108 pregister = __g_module_variables[module_index].pregister; 1109 writel((u32)((setup << 8) | (hold & 0xff)), &pregister->dpcmputime0); 1110 writel((u32)(acc), &pregister->dpcmputime1); 1111} 1112 1113void nx_dpc_set_index(u32 module_index, u32 index) 1114{ 1115 u32 regvalue; 1116 register struct nx_dpc_register_set *pregister; 1117 1118 pregister = __g_module_variables[module_index].pregister; 1119 writel((u32)(index & 0xffff), &pregister->dpcmpuwrdatal); 1120 writel((u32)((index >> 16) & 0xff), &pregister->dpcmpuindex); 1121 if (index == 0x22) { 1122 regvalue = readl(&pregister->dpcctrl2); 1123 writel((regvalue | 0x10), &pregister->dpcctrl2); 1124 } 1125} 1126 1127void nx_dpc_set_data(u32 module_index, u32 data) 1128{ 1129 register struct nx_dpc_register_set *pregister; 1130 1131 pregister = __g_module_variables[module_index].pregister; 1132 writel((u32)(data & 0xffff), &pregister->dpcmpuwrdatal); 1133 writel((u32)((data >> 16) & 0xff), &pregister->dpcmpudatah); 1134} 1135 1136void nx_dpc_set_cmd_buffer_flush(u32 module_index) 1137{ 1138 u32 reg; 1139 register struct nx_dpc_register_set *pregister; 1140 1141 pregister = __g_module_variables[module_index].pregister; 1142 reg = readl(&pregister->dpcdataflush); 1143 writel((u32)(reg | (1 << 1)), &pregister->dpcdataflush); 1144} 1145 1146void nx_dpc_set_cmd_buffer_clear(u32 module_index) 1147{ 1148 u32 reg; 1149 register struct nx_dpc_register_set *pregister; 1150 1151 pregister = __g_module_variables[module_index].pregister; 1152 reg = readl(&pregister->dpcdataflush); 1153 writel((u32)(reg | (1 << 0)), &pregister->dpcdataflush); 1154} 1155 1156void nx_dpc_set_cmd_buffer_write(u32 module_index, u32 cmd_data) 1157{ 1158 register struct nx_dpc_register_set *pregister; 1159 1160 pregister = __g_module_variables[module_index].pregister; 1161 writel((u32)(cmd_data & 0xffff), &pregister->dpccmdbufferdatal); 1162 writel((u32)(cmd_data >> 16), &pregister->dpccmdbufferdatah); 1163} 1164 1165void nx_dpc_set(u32 module_index) 1166{ 1167 u32 reg; 1168 register struct nx_dpc_register_set *pregister; 1169 1170 pregister = __g_module_variables[module_index].pregister; 1171 reg = readl(&pregister->dpcpolctrl); 1172 writel((u32)(reg | 0x1), &pregister->dpcpolctrl); 1173} 1174 1175u32 nx_dpc_get_data(u32 module_index) 1176{ 1177 u32 reg = 0; 1178 register struct nx_dpc_register_set *pregister; 1179 1180 pregister = __g_module_variables[module_index].pregister; 1181 reg = readl(&pregister->dpcmpudatah); 1182 reg = (reg << 16) | readl(&pregister->dpcmpurdatal); 1183 return reg; 1184} 1185 1186u32 nx_dpc_get_status(u32 module_index) 1187{ 1188 u32 reg = 0; 1189 register struct nx_dpc_register_set *pregister; 1190 1191 pregister = __g_module_variables[module_index].pregister; 1192 reg = readl(&pregister->dpcmpustatus); 1193 reg = (reg << 16) | readl(&pregister->dpcmpurdatal); 1194 return reg; 1195} 1196 1197void nx_dpc_rgbmask(u32 module_index, u32 rgbmask) 1198{ 1199 register struct nx_dpc_register_set *pregister; 1200 1201 pregister = __g_module_variables[module_index].pregister; 1202 writel((rgbmask >> 0) & 0xffff, &pregister->dpcrgbmask[0]); 1203 writel((rgbmask >> 16) & 0x00ff, &pregister->dpcrgbmask[1]); 1204} 1205 1206void nx_dpc_set_pad_location(u32 module_index, u32 index, u32 regvalue) 1207{ 1208 register struct nx_dpc_register_set *pregister; 1209 1210 pregister = __g_module_variables[module_index].pregister; 1211 writel(regvalue, &pregister->dpcpadposition[index]); 1212} 1213 1214u32 nx_dpc_get_field_flag(u32 module_index) 1215{ 1216 register struct nx_dpc_register_set *pregister; 1217 u32 regvalue; 1218 1219 pregister = __g_module_variables[module_index].pregister; 1220 regvalue = readl(&pregister->dpcrgbshift); 1221 1222 return (u32)((regvalue >> 5) & 0x01); 1223} 1224 1225void nx_dpc_set_enable_with_interlace(u32 module_index, int enable, int rgbmode, 1226 int use_ntscsync, int use_analog_output, 1227 int seavenable) 1228{ 1229 u32 regvalue; 1230 register struct nx_dpc_register_set *pregister; 1231 1232 pregister = __g_module_variables[module_index].pregister; 1233 regvalue = readl(&pregister->dpcctrl0) & 0x0eff; 1234 regvalue = readl(&pregister->dpcctrl0) & 0x0eff; 1235 regvalue |= ((u32)enable << 15) | ((u32)use_ntscsync << 14) | 1236 ((u32)seavenable << 8) | ((u32)use_analog_output << 13) | 1237 ((u32)rgbmode << 12); 1238 1239 regvalue |= (1 << 9); 1240 writel((u16)regvalue, &pregister->dpcctrl0); 1241} 1242 1243void nx_dpc_set_encoder_control_reg(u32 module_index, u32 param_a, u32 param_b, 1244 u32 param_c) 1245{ 1246 register struct nx_dpc_register_set *pregister; 1247 1248 pregister = __g_module_variables[module_index].pregister; 1249 writel(param_a, &pregister->ntsc_ecmda); 1250 writel(param_b, &pregister->ntsc_ecmdb); 1251 writel(param_c, &pregister->ntsc_ecmdc); 1252} 1253 1254void nx_dpc_set_encoder_shcphase_control(u32 module_index, u32 chroma_param) 1255{ 1256 register struct nx_dpc_register_set *pregister; 1257 1258 pregister = __g_module_variables[module_index].pregister; 1259 writel(chroma_param, &pregister->ntsc_sch); 1260} 1261 1262void nx_dpc_set_encoder_timing_config_reg(u32 module_index, u32 icntl) 1263{ 1264 register struct nx_dpc_register_set *pregister; 1265 1266 pregister = __g_module_variables[module_index].pregister; 1267 writel(icntl, &pregister->ntsc_icntl); 1268} 1269 1270void nx_dpc_set_encoder_dacoutput_select(u32 module_index, u8 dacsel0, 1271 u8 dacsel1, u8 dacsel2, u8 dacsel3, 1272 u8 dacsel4, u8 dacsel5) 1273{ 1274 register struct nx_dpc_register_set *pregister; 1275 1276 pregister = __g_module_variables[module_index].pregister; 1277 writel(((dacsel1 & 0xf) << 4) | (dacsel0 & 0xf), 1278 &pregister->ntsc_dacsel10); 1279 writel(((dacsel3 & 0xf) << 4) | (dacsel2 & 0xf), 1280 &pregister->ntsc_dacsel32); 1281 writel(((dacsel5 & 0xf) << 4) | (dacsel4 & 0xf), 1282 &pregister->ntsc_dacsel54); 1283} 1284 1285void nx_dpc_set_encoder_sync_location(u32 module_index, u16 hsoe, u16 hsob, 1286 u16 vsob, u16 vsoe, u8 vsost, int novrst) 1287{ 1288 register struct nx_dpc_register_set *pregister; 1289 1290 pregister = __g_module_variables[module_index].pregister; 1291 writel((u16)((((vsob & 0x100) >> 2) | ((hsob & 0x700) >> 5) | 1292 (hsoe & 0x700) >> 8)), &pregister->ntsc_hsvso); 1293 writel((u16)(hsoe & 0xff), &pregister->ntsc_hsoe); 1294 writel((u16)(hsob & 0xff), &pregister->ntsc_hsob); 1295 writel((u16)(vsob & 0xff), &pregister->ntsc_vsob); 1296 writel((u16)(((vsost & 0x3) << 6) | (novrst << 5) | (vsoe & 0x1f)), 1297 &pregister->ntsc_vsoe); 1298} 1299 1300void nx_dpc_set_encoder_dacpower_enable(u32 module_index, u8 dacpd) 1301{ 1302 register struct nx_dpc_register_set *pregister; 1303 1304 pregister = __g_module_variables[module_index].pregister; 1305 writel(dacpd, &pregister->ntsc_dacpd); 1306} 1307 1308void nx_dpc_set_ycorder(u32 module_index, enum nx_dpc_ycorder ycorder) 1309{ 1310 const u16 ycorder_pos = 6; 1311 register struct nx_dpc_register_set *pregister; 1312 u32 temp; 1313 1314 pregister = __g_module_variables[module_index].pregister; 1315 temp = pregister->dpcctrl1 & (~(0xf << ycorder_pos)); 1316 temp = (u16)(temp | (ycorder << ycorder_pos)); 1317 writel(temp, &pregister->dpcctrl1); 1318} 1319 1320void nx_dpc_set_luma_gain(u32 module_index, u32 luma_gain) 1321{ 1322 register struct nx_dpc_register_set *pregister; 1323 1324 pregister = __g_module_variables[module_index].pregister; 1325 writel(luma_gain, &pregister->ntsc_cont); 1326} 1327 1328void nx_dpc_set_encenable(u32 module_index, int benb) 1329{ 1330 const u16 encmode = 1u << 14; 1331 const u16 encrst = 1u << 13; 1332 const u16 intpend = 1u << 10; 1333 register struct nx_dpc_register_set *pregister; 1334 register u16 temp; 1335 1336 pregister = __g_module_variables[module_index].pregister; 1337 temp = readl(&pregister->dpcctrl0); 1338 temp &= (u16)~intpend; 1339 if (benb) 1340 temp |= (u16)encrst; 1341 else 1342 temp &= (u16)~encrst; 1343 writel((temp | encmode), &pregister->dpcctrl0); 1344 writel(7, &pregister->ntsc_icntl); 1345} 1346 1347int nx_dpc_get_encenable(u32 module_index) 1348{ 1349 const u16 encrst = 1u << 13; 1350 register struct nx_dpc_register_set *pregister; 1351 1352 pregister = __g_module_variables[module_index].pregister; 1353 return (readl(&pregister->dpcctrl0) & encrst) ? 1 : 0; 1354} 1355 1356void nx_dpc_set_video_encoder_power_down(u32 module_index, int benb) 1357{ 1358 const u16 pwdenc = 1u << 7; 1359 register struct nx_dpc_register_set *pregister; 1360 1361 pregister = __g_module_variables[module_index].pregister; 1362 if (benb) { 1363 writel(readl(&pregister->ntsc_ecmda) | (u16)pwdenc, 1364 &pregister->ntsc_ecmda); 1365 writel(0, &pregister->ntsc_dacsel10); 1366 } else { 1367 writel(1, &pregister->ntsc_dacsel10); 1368 writel(readl(&pregister->ntsc_ecmda) & (u16)~pwdenc, 1369 &pregister->ntsc_ecmda); 1370 } 1371} 1372 1373int nx_dpc_get_video_encoder_power_down(u32 module_index) 1374{ 1375 const u16 pwdenc = 1u << 7; 1376 register struct nx_dpc_register_set *pregister; 1377 1378 pregister = __g_module_variables[module_index].pregister; 1379 return (readl(&pregister->ntsc_ecmda) & pwdenc) ? 1 : 0; 1380} 1381 1382void nx_dpc_set_video_encoder_mode(u32 module_index, enum nx_dpc_vbs vbs, 1383 int bpedestal) 1384{ 1385 register struct nx_dpc_register_set *pregister; 1386 1387#define phalt (1u << 0) 1388#define ifmt (1u << 1) 1389#define ped (1u << 3) 1390#define fscsel_ntsc (0u << 4) 1391#define fscsel_pal (1u << 4) 1392#define fscsel_palm (2u << 4) 1393#define fscsel_paln (3u << 4) 1394#define fdrst (1u << 6) 1395#define pwdenc (1u << 7) 1396 register u16 temp; 1397 static const u8 ntsc_ecmda_table[] = { 1398 (u8)(fscsel_ntsc | fdrst), (u8)(ifmt | fscsel_ntsc), 1399 (u8)(fscsel_pal), (u8)(fscsel_palm | phalt), 1400 (u8)(ifmt | fscsel_paln | phalt), 1401 (u8)(ifmt | fscsel_pal | phalt | fdrst), 1402 (u8)(fscsel_pal | phalt), 1403 (u8)(ifmt | fscsel_ntsc) 1404 }; 1405 pregister = __g_module_variables[module_index].pregister; 1406 temp = readl(&pregister->ntsc_ecmda); 1407 temp &= (u16)pwdenc; 1408 temp = (u16)(temp | (u16)ntsc_ecmda_table[vbs]); 1409 if (bpedestal) 1410 temp |= (u16)ped; 1411 writel(temp, &pregister->ntsc_ecmda); 1412#undef phalt 1413#undef ifmt 1414#undef ped 1415#undef fscsel_ntsc 1416#undef fscsel_pal 1417#undef fscsel_palm 1418#undef fscsel_paln 1419#undef fdrst 1420#undef pwdenc 1421} 1422 1423void nx_dpc_set_video_encoder_schlock_control(u32 module_index, int bfreerun) 1424{ 1425 const u16 fdrst = 1u << 6; 1426 register struct nx_dpc_register_set *pregister; 1427 register u16 temp; 1428 1429 pregister = __g_module_variables[module_index].pregister; 1430 temp = readl(&pregister->ntsc_ecmda); 1431 if (bfreerun) 1432 temp |= (u16)fdrst; 1433 else 1434 temp &= (u16)~fdrst; 1435 writel(temp, &pregister->ntsc_ecmda); 1436} 1437 1438int nx_dpc_get_video_encoder_schlock_control(u32 module_index) 1439{ 1440 const u16 fdrst = 1u << 6; 1441 register struct nx_dpc_register_set *pregister; 1442 1443 pregister = __g_module_variables[module_index].pregister; 1444 return (readl(&pregister->ntsc_ecmda) & fdrst) ? 1 : 0; 1445} 1446 1447void nx_dpc_set_video_encoder_bandwidth(u32 module_index, 1448 enum nx_dpc_bandwidth luma, 1449 enum nx_dpc_bandwidth chroma) 1450{ 1451 const u16 ybw_pos = 0; 1452 const u16 cbw_pos = 2; 1453 register struct nx_dpc_register_set *pregister; 1454 1455 pregister = __g_module_variables[module_index].pregister; 1456 writel((u16)((chroma << cbw_pos) | (luma << ybw_pos)), 1457 &pregister->ntsc_ecmdb); 1458} 1459 1460void nx_dpc_get_video_encoder_bandwidth(u32 module_index, 1461 enum nx_dpc_bandwidth *pluma, 1462 enum nx_dpc_bandwidth *pchroma) 1463{ 1464 const u16 ybw_pos = 0; 1465 const u16 ybw_mask = 3u << ybw_pos; 1466 const u16 cbw_pos = 2; 1467 const u16 cbw_mask = 3u << cbw_pos; 1468 register struct nx_dpc_register_set *pregister; 1469 register u16 temp; 1470 1471 pregister = __g_module_variables[module_index].pregister; 1472 temp = readl(&pregister->ntsc_ecmdb); 1473 if (pluma) 1474 *pluma = (enum nx_dpc_bandwidth)((temp & ybw_mask) >> ybw_pos); 1475 if (pchroma) 1476 *pchroma = 1477 (enum nx_dpc_bandwidth)((temp & cbw_mask) >> cbw_pos); 1478} 1479 1480void nx_dpc_set_video_encoder_color_control(u32 module_index, s8 sch, 1481 s8 hue, s8 sat, s8 crt, 1482 s8 brt) 1483{ 1484 register struct nx_dpc_register_set *pregister; 1485 1486 pregister = __g_module_variables[module_index].pregister; 1487 writel((u16)sch, &pregister->ntsc_sch); 1488 writel((u16)hue, &pregister->ntsc_hue); 1489 writel((u16)sat, &pregister->ntsc_sat); 1490 writel((u16)crt, &pregister->ntsc_cont); 1491 writel((u16)brt, &pregister->ntsc_bright); 1492} 1493 1494void nx_dpc_get_video_encoder_color_control(u32 module_index, s8 *psch, 1495 s8 *phue, s8 *psat, 1496 s8 *pcrt, s8 *pbrt) 1497{ 1498 register struct nx_dpc_register_set *pregister; 1499 1500 pregister = __g_module_variables[module_index].pregister; 1501 if (psch) 1502 *psch = (s8)readl(&pregister->ntsc_sch); 1503 if (phue) 1504 *phue = (s8)readl(&pregister->ntsc_hue); 1505 if (psat) 1506 *psat = (s8)readl(&pregister->ntsc_sat); 1507 if (pcrt) 1508 *pcrt = (s8)readl(&pregister->ntsc_cont); 1509 if (pbrt) 1510 *pbrt = (s8)readl(&pregister->ntsc_bright); 1511} 1512 1513void nx_dpc_set_video_encoder_fscadjust(u32 module_index, int16_t adjust) 1514{ 1515 register struct nx_dpc_register_set *pregister; 1516 1517 pregister = __g_module_variables[module_index].pregister; 1518 writel((u16)(adjust >> 8), &pregister->ntsc_fsc_adjh); 1519 writel((u16)(adjust & 0xff), &pregister->ntsc_fsc_adjl); 1520} 1521 1522u16 nx_dpc_get_video_encoder_fscadjust(u32 module_index) 1523{ 1524 register u32 temp; 1525 register struct nx_dpc_register_set *pregister; 1526 1527 pregister = __g_module_variables[module_index].pregister; 1528 temp = (u32)readl(&pregister->ntsc_fsc_adjh); 1529 temp <<= 8; 1530 temp |= (((u32)readl(&pregister->ntsc_fsc_adjl)) & 0xff); 1531 return (u16)temp; 1532} 1533 1534void nx_dpc_set_video_encoder_timing(u32 module_index, u32 hsos, u32 hsoe, 1535 u32 vsos, u32 vsoe) 1536{ 1537 register struct nx_dpc_register_set *pregister; 1538 1539 pregister = __g_module_variables[module_index].pregister; 1540 hsos -= 1; 1541 hsoe -= 1; 1542 writel((u16)((((vsos >> 8) & 1u) << 6) | (((hsos >> 8) & 7u) << 3) | 1543 (((hsoe >> 8) & 7u) << 0)), &pregister->ntsc_hsvso); 1544 writel((u16)(hsos & 0xffu), &pregister->ntsc_hsob); 1545 writel((u16)(hsoe & 0xffu), &pregister->ntsc_hsoe); 1546 writel((u16)(vsos & 0xffu), &pregister->ntsc_vsob); 1547 writel((u16)(vsoe & 0x1fu), &pregister->ntsc_vsoe); 1548} 1549 1550void nx_dpc_get_video_encoder_timing(u32 module_index, u32 *phsos, u32 *phsoe, 1551 u32 *pvsos, u32 *pvsoe) 1552{ 1553 register u16 hsvso; 1554 register struct nx_dpc_register_set *pregister; 1555 1556 pregister = __g_module_variables[module_index].pregister; 1557 hsvso = readl(&pregister->ntsc_hsvso); 1558 if (phsos) 1559 *phsos = (u32)((((hsvso >> 3) & 7u) << 8) | 1560 (readl(&pregister->ntsc_hsob) & 0xffu)) + 1; 1561 if (phsoe) 1562 *phsoe = (u32)((((hsvso >> 0) & 7u) << 8) | 1563 (readl(&pregister->ntsc_hsoe) & 0xffu)) + 1; 1564 if (pvsos) 1565 *pvsos = (u32)((((hsvso >> 6) & 1u) << 8) | 1566 (readl(&pregister->ntsc_vsob) & 0xffu)); 1567 if (pvsoe) 1568 *pvsoe = (u32)(readl(&pregister->ntsc_vsoe) & 0x1fu); 1569} 1570