1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Video driver for Marvell Armada XP SoC 4 * 5 * Initialization of LCD interface and setup of SPLASH screen image 6 */ 7 8#include <dm.h> 9#include <part.h> 10#include <video.h> 11#include <asm/cache.h> 12#include <dm/device_compat.h> 13#include <linux/delay.h> 14#include <linux/mbus.h> 15#include <asm/io.h> 16#include <asm/arch/cpu.h> 17#include <asm/arch/soc.h> 18 19#define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4)) 20#define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4)) 21#define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4)) 22 23#define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc 24#define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc 25 26#define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4 27#define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8 28#define MVEBU_LCD_CFG_GRA_PITCH 0x00fc 29#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100 30#define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104 31#define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108 32#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c 33#define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110 34#define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114 35#define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118 36#define MVEBU_LCD_SPU_H_PORCH 0x011c 37#define MVEBU_LCD_SPU_V_PORCH 0x0120 38#define MVEBU_LCD_SPU_BLANKCOLOR 0x0124 39#define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128 40#define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c 41#define MVEBU_LCD_SPU_COLORKEY_Y 0x0130 42#define MVEBU_LCD_SPU_COLORKEY_U 0x0134 43#define MVEBU_LCD_SPU_COLORKEY_V 0x0138 44#define MVEBU_LCD_CFG_RDREG4F 0x013c 45#define MVEBU_LCD_SPU_SPI_RXDATA 0x0140 46#define MVEBU_LCD_SPU_ISA_RXDATA 0x0144 47#define MVEBU_LCD_SPU_DBG_ISA 0x0148 48 49#define MVEBU_LCD_SPU_HWC_RDDAT 0x0158 50#define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c 51#define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160 52#define MVEBU_LCD_SPU_IOPAD_IN 0x0178 53#define MVEBU_LCD_FRAME_COUNT 0x017c 54#define MVEBU_LCD_SPU_DMA_CTRL0 0x0190 55#define MVEBU_LCD_SPU_DMA_CTRL1 0x0194 56#define MVEBU_LCD_SPU_SRAM_CTRL 0x0198 57#define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c 58#define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0 59#define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4 60#define MVEBU_LCD_CFG_SCLK_DIV 0x01a8 61#define MVEBU_LCD_SPU_CONTRAST 0x01ac 62#define MVEBU_LCD_SPU_SATURATION 0x01b0 63#define MVEBU_LCD_SPU_CBSH_HUE 0x01b4 64#define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8 65#define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc 66#define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8 67#define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc 68#define MVEBU_LCD_SPU_IRQ_ENA 0x01c0 69#define MVEBU_LCD_SPU_IRQ_ISR 0x01c4 70#define MVEBU_LCD_ADLL_CTRL 0x01c8 71#define MVEBU_LCD_CLK_DIS 0x01cc 72#define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4 73#define MVEBU_LCD_CLK_CFG_0 0xf0a0 74#define MVEBU_LCD_CLK_CFG_1 0xf0a4 75#define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac 76 77#define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0) 78 79enum { 80 /* Maximum LCD size we support */ 81 LCD_MAX_WIDTH = 640, 82 LCD_MAX_HEIGHT = 480, 83 LCD_MAX_LOG2_BPP = VIDEO_BPP16, 84}; 85 86struct mvebu_lcd_info { 87 u32 fb_base; 88 int x_res; 89 int y_res; 90 int x_fp; 91 int y_fp; 92 int x_bp; 93 int y_bp; 94}; 95 96struct mvebu_video_priv { 97 uintptr_t regs; 98}; 99 100/* Setup Mbus Bridge Windows for LCD */ 101static void mvebu_lcd_conf_mbus_registers(uintptr_t regs) 102{ 103 const struct mbus_dram_target_info *dram; 104 int i; 105 106 dram = mvebu_mbus_dram_info(); 107 108 /* Disable windows, set size/base/remap to 0 */ 109 for (i = 0; i < 6; i++) { 110 writel(0, regs + MVEBU_LCD_WIN_CONTROL(i)); 111 writel(0, regs + MVEBU_LCD_WIN_BASE(i)); 112 writel(0, regs + MVEBU_LCD_WIN_REMAP(i)); 113 } 114 115 /* Write LCD bridge window registers */ 116 for (i = 0; i < dram->num_cs; i++) { 117 const struct mbus_dram_window *cs = dram->cs + i; 118 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | 119 (dram->mbus_dram_target_id << 4) | 1, 120 regs + MVEBU_LCD_WIN_CONTROL(i)); 121 122 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i)); 123 } 124} 125 126/* Initialize LCD registers */ 127static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info, 128 uintptr_t regs) 129{ 130 /* Local variable for easier handling */ 131 int x = lcd_info->x_res; 132 int y = lcd_info->y_res; 133 u32 val; 134 135 /* Setup Mbus Bridge Windows */ 136 mvebu_lcd_conf_mbus_registers(regs); 137 138 /* 139 * Set LVDS Pads Control Register 140 * wr 0 182F0 FFE00000 141 */ 142 clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16); 143 144 /* 145 * Set the LCD_CFG_GRA_START_ADDR0/1 Registers 146 * This is supposed to point to the "physical" memory at memory 147 * end (currently 1GB-64MB but also may be 2GB-64MB). 148 * See also the Window 0 settings! 149 */ 150 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0); 151 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1); 152 153 /* 154 * Set the LCD_CFG_GRA_PITCH Register 155 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting) 156 * Bits 25-16: Backlight divider from 32kHz Clock 157 * (here 16=0x10 for 1kHz) 158 * Bits 15-00: Line Length in Bytes 159 * 240*2 (for RGB1555)=480=0x1E0 160 */ 161 writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH); 162 163 /* 164 * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register 165 * Bits 31-16: Vertical start of graphical overlay on screen 166 * Bits 15-00: Horizontal start of graphical overlay on screen 167 */ 168 writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN); 169 170 /* 171 * Set the LCD_SPU_GRA_HPXL_VLN Register 172 * Bits 31-16: Vertical size of graphical overlay 320=0x140 173 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 174 * Values before zooming 175 */ 176 writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN); 177 178 /* 179 * Set the LCD_SPU_GZM_HPXL_VLN Register 180 * Bits 31-16: Vertical size of graphical overlay 320=0x140 181 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 182 * Values after zooming 183 */ 184 writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN); 185 186 /* 187 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register 188 * Bits 31-16: Vertical position of HW Cursor 320=0x140 189 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0 190 */ 191 writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN); 192 193 /* 194 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register 195 * Bits 31-16: Vertical size of HW Cursor 196 * Bits 15-00: Horizontal size of HW Cursor 197 */ 198 writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN); 199 200 /* 201 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register 202 * Bits 31-16: Screen total vertical lines: 203 * VSYNC = 1 204 * Vertical Front Porch = 2 205 * Vertical Lines = 320 206 * Vertical Back Porch = 2 207 * SUM = 325 = 0x0145 208 * Bits 15-00: Screen total horizontal pixels: 209 * HSYNC = 1 210 * Horizontal Front Porch = 44 211 * Horizontal Lines = 240 212 * Horizontal Back Porch = 2 213 * SUM = 287 = 0x011F 214 * Note: For the display the backporch is between SYNC and 215 * the start of the pixels. 216 * This is not certain for the Marvell (!?) 217 */ 218 val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) | 219 (x + lcd_info->x_fp + lcd_info->x_bp + 1); 220 writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL); 221 222 /* 223 * Set the LCD_SPU_V_H_ACTIVE Register 224 * Bits 31-16: Screen active vertical lines 320=0x140 225 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0 226 */ 227 writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE); 228 229 /* 230 * Set the LCD_SPU_H_PORCH Register 231 * Bits 31-16: Screen horizontal backporch 44=0x2c 232 * Bits 15-00: Screen horizontal frontporch 2=0x02 233 * Note: The terms "front" and "back" for the Marvell seem to be 234 * exactly opposite to the display. 235 */ 236 writel((lcd_info->x_fp << 16) | lcd_info->x_bp, 237 regs + MVEBU_LCD_SPU_H_PORCH); 238 239 /* 240 * Set the LCD_SPU_V_PORCH Register 241 * Bits 31-16: Screen vertical backporch 2=0x02 242 * Bits 15-00: Screen vertical frontporch 2=0x02 243 * Note: The terms "front" and "back" for the Marvell seem to be exactly 244 * opposite to the display. 245 */ 246 writel((lcd_info->y_fp << 16) | lcd_info->y_bp, 247 regs + MVEBU_LCD_SPU_V_PORCH); 248 249 /* 250 * Set the LCD_SPU_BLANKCOLOR Register 251 * This should be black = 0 252 * For tests this is magenta=00FF00FF 253 */ 254 writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR); 255 256 /* 257 * Registers in the range of 0x0128 to 0x012C are colors for the cursor 258 * Registers in the range of 0x0130 to 0x0138 are colors for video 259 * color keying 260 */ 261 262 /* 263 * Set the LCD_SPU_RDREG4F Register 264 * Bits 31-12: Reservd 265 * Bit 11: SRAM Wait 266 * Bit 10: Smart display fast TX (must be 1) 267 * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved 268 * Bit 8: FIFO watermark for DMA: 0=disable 269 * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80 270 */ 271 writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F); 272 273 /* 274 * Set the LCD_SPU_DMACTRL 0 Register 275 * Bit 31: Disable overlay blending 1=disable 276 * Bit 30: Gamma correction enable, 0=disable 277 * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable 278 * Bit 28: Color palette enable, 0=disable 279 * Bit 27: DMA AXI Arbiter, 1=default 280 * Bit 26: HW Cursor 1-bit mode 281 * Bit 25: HW Cursor or 1- or 2-bit mode 282 * Bit 24: HW Cursor enabled, 0=disable 283 * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555 284 * Bits 19-16: Video Memory Color Format: 0x1=RGB1555 285 * Bit 15: Memory Toggle between frame 0 and 1: 0=disable 286 * Bit 14: Graphics horizontal scaling enable: 0=disable 287 * Bit 13: Graphics test mode: 0=disable 288 * Bit 12: Graphics SWAP R and B: 0=disable 289 * Bit 11: Graphics SWAP U and V: 0=disable 290 * Bit 10: Graphics SWAP Y and U/V: 0=disable 291 * Bit 09: Graphic YUV to RGB Conversion: 0=disable 292 * Bit 08: Graphic Transfer: 1=enable 293 * Bit 07: Memory Toggle: 0=disable 294 * Bit 06: Video horizontal scaling enable: 0=disable 295 * Bit 05: Video test mode: 0=disable 296 * Bit 04: Video SWAP R and B: 0=disable 297 * Bit 03: Video SWAP U and V: 0=disable 298 * Bit 02: Video SWAP Y and U/V: 0=disable 299 * Bit 01: Video YUV to RGB Conversion: 0=disable 300 * Bit 00: Video Transfer: 0=disable 301 */ 302 writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0); 303 304 /* 305 * Set the LCD_SPU_DMA_CTRL1 Register 306 * Bit 31: Manual DMA Trigger = 0 307 * Bits 30-28: DMA Trigger Source: 0x2 VSYNC 308 * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge 309 * Bits 26-24: Color Key Mode: 0=disable 310 * Bit 23: Fill low bits: 0=fill with zeroes 311 * Bit 22: Reserved 312 * Bit 21: Gated Clock: 0=disable 313 * Bit 20: Power Save enable: 0=disable 314 * Bits 19-18: Reserved 315 * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha. 316 * Bits 15-08: Configure Alpha: 0x00. 317 * Bits 07-00: Reserved. 318 */ 319 writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1); 320 321 /* 322 * Set the LCD_SPU_SRAM_CTRL Register 323 * Reset to default = 0000C000 324 * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2 325 * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb, 326 * 3=palette, 15=cursor 327 */ 328 writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL); 329 330 /* 331 * LCD_SPU_SRAM_WRDAT register: 019C 332 * LCD_SPU_SRAM_PARA0 register: 01A0 333 * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings 334 */ 335 writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1); 336 337 338 /* Clock settings in the at 01A8 and in the range F0A0 see below */ 339 340 /* 341 * Set LCD_SPU_CONTRAST 342 * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0 343 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0 344 */ 345 writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST); 346 347 /* 348 * Set LCD_SPU_SATURATION 349 * Bits 31-16: Multiplier signed 4.12 fixed point value 350 * Bits 15-00: Saturation signed 4.12 fixed point value 351 */ 352 writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION); 353 354 /* 355 * Set LCD_SPU_HUE 356 * Bits 31-16: Sine signed 2.14 fixed point value 357 * Bits 15-00: Cosine signed 2.14 fixed point value 358 */ 359 writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE); 360 361 /* 362 * Set LCD_SPU_DUMB_CTRL 363 * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888 364 * Bits 27-12: Reserved 365 * Bit 11: LCD DMA Pipeline Enable: 1=Enable 366 * Bits 10-09: Reserved 367 * Bit 8: LCD GPIO pin (??) 368 * Bit 7: Reverse RGB 369 * Bit 6: Invert composite blank signal DE/EN (??) 370 * Bit 5: Invert composite sync signal 371 * Bit 4: Invert Pixel Valid Enable DE/EN (??) 372 * Bit 3: Invert VSYNC 373 * Bit 2: Invert HSYNC 374 * Bit 1: Invert Pixel Clock 375 * Bit 0: Enable LCD Panel: 1=Enable 376 * Question: Do we have to disable Smart and Dumb LCD 377 * and separately enable LVDS? 378 */ 379 writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL); 380 381 /* 382 * Set LCD_SPU_IOPAD_CTRL 383 * Bits 31-20: Reserved 384 * Bits 19-18: Vertical Interpolation: 0=Disable 385 * Bits 17-16: Reserved 386 * Bit 15: Graphics Vertical Mirror enable: 0=disable 387 * Bit 14: Reserved 388 * Bit 13: Video Vertical Mirror enable: 0=disable 389 * Bit 12: Reserved 390 * Bit 11: Command Vertical Mirror enable: 0=disable 391 * Bit 10: Reserved 392 * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used) 393 * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary, 394 * 128 Bytes burst 395 * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ?? 396 */ 397 writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL); 398 399 /* 400 * Set SUP_IRQ_ENA_2: Disable all interrupts 401 */ 402 writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2); 403 404 /* 405 * Set SUP_IRQ_ENA: Disable all interrupts. 406 */ 407 writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA); 408 409 /* 410 * Set up ADDL Control Register 411 * Bits 31-29: 0x0 = Fastest Delay Line (default) 412 * 0x3 = Slowest Delay Line (default) 413 * Bit 28: Calibration done status. 414 * Bit 27: Reserved 415 * Bit 26: Set Pixel Clock to ADDL output 416 * Bit 25: Reduce CAL Enable 417 * Bits 24-22: Manual calibration value. 418 * Bit 21: Manual calibration enable. 419 * Bit 20: Restart Auto Cal 420 * Bits 19-16: Calibration Threshold voltage, default= 0x2 421 * Bite 15-14: Reserved 422 * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16 423 * Bit 10: Power Down ADDL module, default = 1! 424 * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z 425 * Bit 07: Reset ADDL 426 * Bit 06: Invert ADLL Clock 427 * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay 428 * Note: ADLL is used for a VGA interface with DAC - not used here 429 */ 430 writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL); 431 432 /* 433 * Set the LCD_CLK_DIS Register: 434 * Bits 3 and 4 must be 1 435 */ 436 writel(0x00000018, regs + MVEBU_LCD_CLK_DIS); 437 438 /* 439 * Set the LCD_VGA_HSYNC/VSYNC Delay Register: 440 * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals 441 */ 442 writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY); 443 444 /* 445 * Clock registers 446 * See page 475 in the functional spec. 447 */ 448 449 /* Step 1 and 2: Disable the PLL */ 450 451 /* 452 * Disable PLL, see "LCD Clock Configuration 1 Register" below 453 */ 454 writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1); 455 456 /* 457 * Powerdown, see "LCD Clock Configuration 0 Register" below 458 */ 459 writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0); 460 461 /* 462 * Set the LCD_CFG_SCLK_DIV Register 463 * This is set fix to 0x40000001 for the LVDS output: 464 * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0 465 * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001 466 * See page 475 in section 28.5. 467 */ 468 writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV); 469 470 /* 471 * Set the LCD Clock Configuration 0 Register: 472 * Bit 31: Powerdown: 0=Power up 473 * Bits 30-29: Reserved 474 * Bits 28-26: PLL_KDIV: This encodes K 475 * K=16 => 0x5 476 * Bits 25-17: PLL_MDIV: This is M-1: 477 * M=1 => 0x0 478 * Bits 16-13: VCO band: 0x1 for 700-920MHz 479 * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL! 480 * N=28=0x1C => 0x1B 481 * Bits 03-00: R1_CTRL (for N=28 => 0x4) 482 */ 483 writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0); 484 485 /* 486 * Set the LCD Clock Configuration 1 Register: 487 * Bits 31-19: Reserved 488 * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL 489 * Bit 17: Clock Output Enable: 0=disable, 1=enable 490 * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External 491 * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev 492 * Bits 14-13: Reserved 493 * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider 494 * M' for LVDS=7!] 495 */ 496 writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1); 497 498 /* 499 * Set the LVDS Clock Configuration Register: 500 * Bit 31: Clock Gating for the input clock to the LVDS 501 * Bit 30: LVDS Serializer enable: 1=Enabled 502 * Bits 29-11: Reserved 503 * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7 504 * Bits 07-02: Reserved 505 * Bit 01: 24bbp Option: 0=Option_1,1=Option2 506 * Bit 00: 1=24bbp Panel: 0=18bpp Panel 507 * Note: Bits 0 and must be verified with the help of the 508 * Interface/display 509 */ 510 writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG); 511 512 /* 513 * Power up PLL (Clock Config 0) 514 */ 515 writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0); 516 517 /* wait 10 ms */ 518 mdelay(10); 519 520 /* 521 * Enable PLL (Clock Config 1) 522 */ 523 writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1); 524} 525 526static int mvebu_video_probe(struct udevice *dev) 527{ 528 struct video_uc_plat *plat = dev_get_uclass_plat(dev); 529 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 530 struct mvebu_video_priv *priv = dev_get_priv(dev); 531 struct mvebu_lcd_info lcd_info; 532 struct display_timing timings; 533 u32 fb_start, fb_end; 534 int ret; 535 536 priv->regs = dev_read_addr(dev); 537 if (priv->regs == FDT_ADDR_T_NONE) { 538 dev_err(dev, "failed to get LCD address\n"); 539 return -ENXIO; 540 } 541 542 ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); 543 if (ret) { 544 dev_err(dev, "failed to get any display timings\n"); 545 return -EINVAL; 546 } 547 548 /* Use DT timing (resolution) in internal info struct */ 549 lcd_info.fb_base = plat->base; 550 lcd_info.x_res = timings.hactive.typ; 551 lcd_info.x_fp = timings.hfront_porch.typ; 552 lcd_info.x_bp = timings.hback_porch.typ; 553 lcd_info.y_res = timings.vactive.typ; 554 lcd_info.y_fp = timings.vfront_porch.typ; 555 lcd_info.y_bp = timings.vback_porch.typ; 556 557 /* Initialize the LCD controller */ 558 mvebu_lcd_register_init(&lcd_info, priv->regs); 559 560 /* Enable dcache for the frame buffer */ 561 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); 562 fb_end = plat->base + plat->size; 563 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); 564 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, 565 DCACHE_WRITEBACK); 566 video_set_flush_dcache(dev, true); 567 568 uc_priv->xsize = lcd_info.x_res; 569 uc_priv->ysize = lcd_info.y_res; 570 uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */ 571 572 return 0; 573} 574 575static int mvebu_video_bind(struct udevice *dev) 576{ 577 struct video_uc_plat *plat = dev_get_uclass_plat(dev); 578 579 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * 580 (1 << LCD_MAX_LOG2_BPP) / 8; 581 582 return 0; 583} 584 585static const struct udevice_id mvebu_video_ids[] = { 586 { .compatible = "marvell,armada-xp-lcd" }, 587 { } 588}; 589 590U_BOOT_DRIVER(mvebu_video) = { 591 .name = "mvebu_video", 592 .id = UCLASS_VIDEO, 593 .of_match = mvebu_video_ids, 594 .bind = mvebu_video_bind, 595 .probe = mvebu_video_probe, 596 .priv_auto = sizeof(struct mvebu_video_priv), 597}; 598