1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2024 Jonas Schw��bel <jonasschwoebel@yahoo.de> 4 * Copyright (C) 2024 Svyatoslav Ryhel <clamor95@gmail.com> 5 */ 6 7#include <dm.h> 8#include <i2c.h> 9#include <log.h> 10#include <backlight.h> 11#include <panel.h> 12#include <linux/delay.h> 13#include <linux/err.h> 14#include <power/regulator.h> 15 16#include <asm/gpio.h> 17 18/* TOP */ 19#define TOPCFG0 0x00 20#define ROMI2C_PRESCALE 0x01 21#define HDCPI2C_PRESCALE 0x02 22#define GPIO 0x03 23#define GPIO_OUT_ENB 0x04 24#define TESTI2C_CTL 0x05 25#define I2CMTIMEOUT 0x06 26#define TOPCFG1 0x07 27#define TOPCFG2 0x08 28#define TOPCFG3 0x09 29#define TOPCFG4 0x0A 30#define CLKSWRST 0x0B 31#define CADETB_CTL 0x0C 32 33/* Video Attribute */ 34#define HTOTAL_L 0x10 35#define HTOTAL_H 0x11 36#define HSTART_L 0x12 37#define HSTART_H 0x13 38#define HWIDTH_L 0x14 39#define HWIDTH_H 0x15 40#define VTOTAL_L 0x16 41#define VTOTAL_H 0x17 42#define VSTART_L 0x18 43#define VSTART_H 0x19 44#define VHEIGHT_L 0x1A 45#define VHEIGHT_H 0x1B 46#define HSPHSW_L 0x1C 47#define HSPHSW_H 0x1D 48#define VSPVSW_L 0x1E 49#define VSPVSW_H 0x1F 50#define MISC0 0x20 51#define MISC1 0x21 52 53/* Video Capture */ 54#define VCAPCTRL0 0x24 55#define VCAPCTRL1 0x25 56#define VCAPCTRL2 0x26 57#define VCAPCTRL3 0x27 58#define VCAPCTRL4 0x28 59#define VCAP_MEASURE 0x29 60 61/* Main Link Control */ 62#define NVID_L 0x2C 63#define NVID_M 0x2D 64#define NVID_H 0x2E 65#define LINK_CTRL0 0x2F 66#define LINK_CTRL1 0x30 67#define LINK_DEBUG 0x31 68#define ERR_POS 0x32 69#define ERR_PAT 0x33 70#define LINK_DEB_SEL 0x34 71#define IDLE_PATTERN 0x35 72#define TU_SIZE 0x36 73#define CRC_CTRL 0x37 74#define CRC_OUT 0x38 75 76/* AVI-2 InfoFrame */ 77#define SD_CTRL0 0x3A 78#define SD_CTRL1 0x3B 79#define SD_HB0 0x3C 80#define SD_HB1 0x3D 81#define SD_HB2 0x3E 82#define SD_HB3 0x3F 83#define SD_DB0 0x40 84#define SD_DB1 0x41 85#define SD_DB2 0x42 86#define SD_DB3 0x43 87#define SD_DB4 0x44 88#define SD_DB5 0x45 89#define SD_DB6 0x46 90#define SD_DB7 0x47 91#define SD_DB8 0x48 92#define SD_DB9 0x49 93#define SD_DB10 0x4A 94#define SD_DB11 0x4B 95#define SD_DB12 0x4C 96#define SD_DB13 0x4D 97#define SD_DB14 0x4E 98#define SD_DB15 0x4F 99 100/* Aux Channel and PCS */ 101#define DPCD_REV 0X50 102#define MAX_LINK_RATE 0x51 103#define MAX_LANE_COUNT 0x52 104#define MAX_DOWNSPREAD 0x53 105#define NORP 0x54 106#define DOWNSTRMPORT_PRE 0x55 107#define MLINK_CH_CODING 0x56 108#define RCV_P0_CAP0 0x58 109#define RCV_P0_CAP1 0x59 110#define RCV_P1_CAP0 0x5A 111#define RCV_P1_CAP1 0x5B 112#define DOWNSPREAD_CTL 0x5C 113#define LINK_BW 0x5D 114#define LANE_CNT 0x5E 115#define TRAINING_CTL 0x5F 116#define QUALTEST_CTL 0x60 117#define SINK_COUNT 0x61 118#define DEV_SERVICE_IRQ 0x62 119#define LANE01_STATUS 0x63 120#define LANE23_STATUS 0x64 121#define LANE_STATUS_UPDATE 0x65 122#define SINK_STATUS 0x66 123#define AUX_NOISE 0x67 124#define TEST_MODE 0x69 125#define TEST_PATTERN0 0x6A 126#define TEST_PATTERN1 0x6B 127#define TEST_PATTERN2 0x6C 128#define SIGNATURE 0x6D 129#define PCSCFG 0x6E 130#define AUXCTRL0 0x6f 131#define AUXCTRL2 0x70 132#define AUXCTRL1 0x71 133#define HPDCTL0 0x72 134#define HPDCTL1 0x73 135#define LINK_STATE_CTRL 0x74 136#define SWRST 0x75 137#define LINK_IRQ 0x76 138#define AUXIRQ_CTRL 0x77 139#define HPD2_IRQ_CTRL 0x78 140#define SW_TRAIN_CTRL 0x79 141#define SW_DRV_SET 0x7A 142#define SW_PRE_SET 0x7B 143#define DPCD_ADDR_L 0x7D 144#define DPCD_ADDR_M 0x7E 145#define DPCD_ADDR_H 0x7F 146#define DPCD_LENGTH 0x80 147#define DPCD_WDATA 0x81 148#define DPCD_RDATA 0x82 149#define DPCD_CTL 0x83 150#define DPCD_STATUS 0x84 151#define AUX_STATUS 0x85 152#define I2CTOAUX_RELENGTH 0x86 153#define AUX_RETRY_CTRL 0x87 154#define TIMEOUT_CTRL 0x88 155#define I2CCMD_OPT1 0x89 156#define AUXCMD_ERR_IRQ 0x8A 157#define AUXCMD_OPT2 0x8B 158#define HDCP_Reserved 0x8C 159 160/* Audio InfoFrame */ 161#define TX_MVID0 0x90 162#define TX_MVID1 0x91 163#define TX_MVID2 0x92 164#define TX_MVID_OFF 0x93 165#define TX_MAUD0 0x94 166#define TX_MAUD1 0x95 167#define TX_MAUD2 0x96 168#define TX_MAUD_OFF 0x97 169#define MN_CTRL 0x98 170#define MOUT0 0x99 171#define MOUT1 0x9A 172#define MOUT2 0x9B 173 174/* Audio Control */ 175#define NAUD_L 0x9F 176#define NAUD_M 0xA0 177#define NAUD_H 0xA1 178#define AUD_CTRL0 0xA2 179#define AUD_CTRL1 0xA3 180#define LANE_POL 0xAA 181#define LANE_EN 0xAB 182#define LANE_MAP 0xAC 183#define SCR_POLY0 0xAD 184#define SCR_POLY1 0xAE 185#define PRBS7_POLY 0xAF 186 187/* Video Pre-process */ 188#define MISC_SHDOW 0xB0 189#define VCAPCPCTL0 0xB1 190#define VCAPCPCTL1 0xB2 191#define VCAPCPCTL2 0xB3 192#define CSCPAR 0xB4 193#define I2CTODPCDSTATUS2 0xBA 194#define AUXCTL_REG 0xBB 195 196/* Page 2 */ 197#define SEL_PIO1 0x24 198#define SEL_PIO2 0x25 199#define SEL_PIO3 0x26 200#define CHIP_VER_L 0x82 201 202struct dp501_priv { 203 struct udevice *panel; 204 struct display_timing timing; 205 206 struct udevice *chip2; 207 208 struct udevice *vdd; 209 struct gpio_desc reset_gpio; 210 struct gpio_desc enable_gpio; 211}; 212 213static int dp501_sw_init(struct udevice *dev) 214{ 215 struct dp501_priv *priv = dev_get_priv(dev); 216 int i; 217 u8 val; 218 219 dm_i2c_reg_write(dev, TOPCFG4, 0x30); 220 udelay(200); 221 dm_i2c_reg_write(dev, TOPCFG4, 0x0c); 222 dm_i2c_reg_write(dev, 0x8f, 0x02); 223 224 /* check for connected panel during 1 msec */ 225 for (i = 0; i < 5; i++) { 226 val = dm_i2c_reg_read(dev, 0x8d); 227 val &= BIT(2); 228 if (val) 229 break; 230 231 udelay(200); 232 } 233 234 if (!val) { 235 log_debug("%s: panel is not connected!\n", __func__); 236 return -ENODEV; 237 } 238 239 dm_i2c_reg_write(priv->chip2, SEL_PIO1, 0x02); 240 dm_i2c_reg_write(priv->chip2, SEL_PIO2, 0x04); 241 dm_i2c_reg_write(priv->chip2, SEL_PIO3, 0x10); 242 243 dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0xa0); 244 dm_i2c_reg_write(dev, 0x8f, 0x02); 245 dm_i2c_reg_write(dev, TOPCFG1, 0x16); 246 dm_i2c_reg_write(dev, TOPCFG0, 0x24); 247 dm_i2c_reg_write(dev, HPD2_IRQ_CTRL, 0x30); 248 dm_i2c_reg_write(dev, AUXIRQ_CTRL, 0xff); 249 dm_i2c_reg_write(dev, LINK_IRQ, 0xff); 250 251 /* auto detect DVO timing */ 252 dm_i2c_reg_write(dev, VCAPCTRL3, 0x30); 253 254 /* reset tpfifo at v blank */ 255 dm_i2c_reg_write(dev, LINK_CTRL0, 0x82); 256 257 dm_i2c_reg_write(dev, VCAPCTRL4, 0x07); 258 dm_i2c_reg_write(dev, AUX_RETRY_CTRL, 0x7f); 259 dm_i2c_reg_write(dev, TIMEOUT_CTRL, 0x1e); 260 dm_i2c_reg_write(dev, AUXCTL_REG, 0x06); 261 262 /* DPCD readable */ 263 dm_i2c_reg_write(dev, HPDCTL0, 0xa9); 264 265 /* Scramble on */ 266 dm_i2c_reg_write(dev, QUALTEST_CTL, 0x00); 267 268 dm_i2c_reg_write(dev, 0x8f, 0x02); 269 270 dm_i2c_reg_write(dev, VCAPCTRL0, 0xc4); 271 272 /* set color depth 8bit (0x00: 6bit; 0x20: 8bit; 0x40: 10bit) */ 273 dm_i2c_reg_write(dev, MISC0, 0x20); 274 275 dm_i2c_reg_write(dev, VCAPCPCTL2, 0x01); 276 277 /* check if bridge returns ready status */ 278 for (i = 0; i < 5; i++) { 279 val = dm_i2c_reg_read(dev, LINK_IRQ); 280 val &= BIT(0); 281 if (val) 282 break; 283 284 udelay(200); 285 } 286 287 if (!val) { 288 log_debug("%s: bridge is not ready\n", __func__); 289 return -ENODEV; 290 } 291 292 return 0; 293} 294 295static void dpcd_configure(struct udevice *dev, u32 config, bool write) 296{ 297 dm_i2c_reg_write(dev, DPCD_ADDR_L, (u8)(config >> 8)); 298 dm_i2c_reg_write(dev, DPCD_ADDR_M, (u8)(config >> 16)); 299 dm_i2c_reg_write(dev, DPCD_ADDR_H, (u8)((config >> 24) | BIT(7))); 300 dm_i2c_reg_write(dev, DPCD_LENGTH, 0x00); 301 dm_i2c_reg_write(dev, LINK_IRQ, 0x20); 302 303 if (write) 304 dm_i2c_reg_write(dev, DPCD_WDATA, (u8)(config & 0xff)); 305 306 dm_i2c_reg_write(dev, DPCD_CTL, 0x01); 307 308 udelay(10); 309} 310 311static int dump_dpcd_data(struct udevice *dev, u32 config, u8 *data) 312{ 313 int i; 314 u8 value; 315 316 dpcd_configure(dev, config, false); 317 318 value = dm_i2c_reg_read(dev, DPCD_CTL); 319 if (value) 320 return -ENODATA; 321 322 for (i = 0; i < 5; i++) { 323 value = dm_i2c_reg_read(dev, LINK_IRQ); 324 value &= BIT(5); 325 if (value) 326 break; 327 328 udelay(100); 329 } 330 331 if (!value) 332 return -ENODATA; 333 334 value = dm_i2c_reg_read(dev, DPCD_STATUS); 335 if (!(value & 0xe0)) 336 *data = dm_i2c_reg_read(dev, DPCD_RDATA); 337 else 338 return -ENODATA; 339 340 return 0; 341} 342 343static int dp501_dpcd_dump(struct udevice *dev, u32 config, u8 *data) 344{ 345 int i, ret; 346 347 for (i = 0; i < 5; i++) { 348 ret = dump_dpcd_data(dev, config, data); 349 if (!ret) 350 break; 351 352 udelay(100); 353 } 354 355 return ret; 356} 357 358static int dp501_reset_link(struct udevice *dev) 359{ 360 dm_i2c_reg_write(dev, TRAINING_CTL, 0x00); 361 dm_i2c_reg_write(dev, SWRST, 0xf8); 362 dm_i2c_reg_write(dev, SWRST, 0x00); 363 364 return -ENODEV; 365} 366 367static int dp501_link_training(struct udevice *dev) 368{ 369 int i, ret; 370 u8 lane, link, link_out; 371 u8 lane_cnt, lane01, lane23; 372 373 dpcd_configure(dev, 0x030000, true); 374 dpcd_configure(dev, 0x03011c, true); 375 dpcd_configure(dev, 0x0301f8, true); 376 377 ret = dp501_dpcd_dump(dev, 0x90000100, &link); 378 if (ret) { 379 log_debug("%s: link dump failed %d\n", __func__, ret); 380 return dp501_reset_link(dev); 381 } 382 383 ret = dp501_dpcd_dump(dev, 0x90000200, &lane); 384 if (ret) { 385 log_debug("%s: lane dump failed %d\n", __func__, ret); 386 return dp501_reset_link(dev); 387 } 388 389 /* Software trainig */ 390 for (i = 10; i > 0; i--) { 391 dm_i2c_reg_write(dev, LINK_BW, link); 392 dm_i2c_reg_write(dev, LANE_CNT, lane | BIT(7)); 393 394 link_out = dm_i2c_reg_read(dev, LINK_BW); 395 lane_cnt = dm_i2c_reg_read(dev, LANE_CNT); 396 397 if (link_out == link && 398 (lane_cnt == (lane | BIT(7)))) 399 break; 400 401 udelay(500); 402 } 403 404 if (!i) 405 return dp501_reset_link(dev); 406 407 dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0x00); 408 dm_i2c_reg_write(dev, TRAINING_CTL, 0x0d); 409 410 /* check if bridge returns link ready status */ 411 for (i = 0; i < 100; i++) { 412 link_out = dm_i2c_reg_read(dev, LINK_IRQ); 413 link_out &= BIT(1); 414 if (link_out) { 415 dm_i2c_reg_write(dev, LINK_IRQ, 0xff); 416 break; 417 } 418 419 udelay(100); 420 } 421 422 if (!link_out) { 423 log_debug("%s: link prepare failed %d\n", 424 __func__, link_out); 425 return dp501_reset_link(dev); 426 } 427 428 lane01 = dm_i2c_reg_read(dev, LANE01_STATUS); 429 lane23 = dm_i2c_reg_read(dev, LANE23_STATUS); 430 431 switch (lane_cnt & 0xf) { 432 case 4: 433 if (lane01 == 0x77 && 434 lane23 == 0x77) 435 return 0; 436 break; 437 438 case 2: 439 if (lane01 == 0x77) 440 return 0; 441 break; 442 443 default: 444 if ((lane01 & 7) == 7) 445 return 0; 446 break; 447 } 448 449 return dp501_reset_link(dev); 450} 451 452static int dp501_attach(struct udevice *dev) 453{ 454 struct dp501_priv *priv = dev_get_priv(dev); 455 int ret; 456 457 ret = dp501_sw_init(dev); 458 if (ret) 459 return ret; 460 461 mdelay(90); 462 463 ret = dp501_link_training(dev); 464 if (ret) 465 return ret; 466 467 /* Perform panel HW setup */ 468 return panel_enable_backlight(priv->panel); 469} 470 471static int dp501_set_backlight(struct udevice *dev, int percent) 472{ 473 struct dp501_priv *priv = dev_get_priv(dev); 474 475 return panel_set_backlight(priv->panel, percent); 476} 477 478static int dp501_panel_timings(struct udevice *dev, 479 struct display_timing *timing) 480{ 481 struct dp501_priv *priv = dev_get_priv(dev); 482 483 memcpy(timing, &priv->timing, sizeof(*timing)); 484 return 0; 485} 486 487static void dp501_hw_init(struct dp501_priv *priv) 488{ 489 dm_gpio_set_value(&priv->reset_gpio, 1); 490 491 regulator_set_enable_if_allowed(priv->vdd, 1); 492 dm_gpio_set_value(&priv->enable_gpio, 1); 493 494 udelay(100); 495 496 dm_gpio_set_value(&priv->reset_gpio, 0); 497 mdelay(80); 498} 499 500static int dp501_setup(struct udevice *dev) 501{ 502 struct dm_i2c_chip *chip = dev_get_parent_plat(dev); 503 struct dp501_priv *priv = dev_get_priv(dev); 504 struct udevice *bus = dev_get_parent(dev); 505 int ret; 506 507 /* get panel */ 508 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, 509 "panel", &priv->panel); 510 if (ret) { 511 log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret); 512 return log_ret(ret); 513 } 514 515 /* get regulators */ 516 ret = device_get_supply_regulator(dev, "power-supply", &priv->vdd); 517 if (ret) { 518 log_debug("%s: vddc regulator error: %d\n", __func__, ret); 519 if (ret != -ENOENT) 520 return log_ret(ret); 521 } 522 523 /* get gpios */ 524 ret = gpio_request_by_name(dev, "reset-gpios", 0, 525 &priv->reset_gpio, GPIOD_IS_OUT); 526 if (ret) { 527 log_debug("%s: Could not decode reset-gpios (%d)\n", 528 __func__, ret); 529 return ret; 530 } 531 532 ret = gpio_request_by_name(dev, "enable-gpios", 0, 533 &priv->enable_gpio, GPIOD_IS_OUT); 534 if (ret) { 535 log_debug("%s: Could not decode enable-gpios (%d)\n", 536 __func__, ret); 537 return ret; 538 } 539 540 ret = i2c_get_chip(bus, chip->chip_addr + 2, 1, &priv->chip2); 541 if (ret) { 542 log_debug("%s: cannot get second PMIC I2C chip (err %d)\n", 543 __func__, ret); 544 return ret; 545 } 546 547 dp501_hw_init(priv); 548 549 /* get EDID */ 550 return panel_get_display_timing(priv->panel, &priv->timing); 551} 552 553static int dp501_probe(struct udevice *dev) 554{ 555 if (device_get_uclass_id(dev->parent) != UCLASS_I2C) 556 return -EPROTONOSUPPORT; 557 558 return dp501_setup(dev); 559} 560 561struct panel_ops dp501_ops = { 562 .enable_backlight = dp501_attach, 563 .set_backlight = dp501_set_backlight, 564 .get_display_timing = dp501_panel_timings, 565}; 566 567static const struct udevice_id dp501_ids[] = { 568 { .compatible = "parade,dp501" }, 569 { } 570}; 571 572U_BOOT_DRIVER(dp501) = { 573 .name = "dp501", 574 .id = UCLASS_PANEL, 575 .of_match = dp501_ids, 576 .ops = &dp501_ops, 577 .probe = dp501_probe, 578 .priv_auto = sizeof(struct dp501_priv), 579}; 580