1/* SPDX-License-Identifier: GPL-2.0 */
2/******************************************************************
3 * Copyright 2008 Mentor Graphics Corporation
4 * Copyright (C) 2008 by Texas Instruments
5 *
6 * This file is part of the Inventra Controller Driver for Linux.
7 ******************************************************************/
8
9#ifndef __MUSB_HDRC_DEFS_H__
10#define __MUSB_HDRC_DEFS_H__
11
12#include <usb_defs.h>
13#include <asm/io.h>
14
15#define MUSB_EP0_FIFOSIZE	64	/* This is non-configurable */
16
17/* EP0 */
18struct musb_ep0_regs {
19	u16	reserved4;
20	u16	csr0;
21	u16	reserved5;
22	u16	reserved6;
23	u16	count0;
24	u8	host_type0;
25	u8	host_naklimit0;
26	u8	reserved7;
27	u8	reserved8;
28	u8	reserved9;
29	u8	configdata;
30};
31
32/* EP 1-15 */
33struct musb_epN_regs {
34	u16	txmaxp;
35	u16	txcsr;
36	u16	rxmaxp;
37	u16	rxcsr;
38	u16	rxcount;
39	u8	txtype;
40	u8	txinterval;
41	u8	rxtype;
42	u8	rxinterval;
43	u8	reserved0;
44	u8	fifosize;
45};
46
47/* Mentor USB core register overlay structure */
48#ifndef musb_regs
49struct musb_regs {
50	/* common registers */
51	u8	faddr;
52	u8	power;
53	u16	intrtx;
54	u16	intrrx;
55	u16	intrtxe;
56	u16	intrrxe;
57	u8	intrusb;
58	u8	intrusbe;
59	u16	frame;
60	u8	index;
61	u8	testmode;
62	/* indexed registers */
63	u16	txmaxp;
64	u16	txcsr;
65	u16	rxmaxp;
66	u16	rxcsr;
67	u16	rxcount;
68	u8	txtype;
69	u8	txinterval;
70	u8	rxtype;
71	u8	rxinterval;
72	u8	reserved0;
73	u8	fifosize;
74	/* fifo */
75	u32	fifox[16];
76	/* OTG, dynamic FIFO, version & vendor registers */
77	u8	devctl;
78	u8	reserved1;
79	u8	txfifosz;
80	u8	rxfifosz;
81	u16	txfifoadd;
82	u16	rxfifoadd;
83	u32	vcontrol;
84	u16	hwvers;
85	u16	reserved2a[1];
86	u8	ulpi_busctl;
87	u8	reserved2b[1];
88	u16	reserved2[3];
89	u8	epinfo;
90	u8	raminfo;
91	u8	linkinfo;
92	u8	vplen;
93	u8	hseof1;
94	u8	fseof1;
95	u8	lseof1;
96	u8	reserved3;
97	/* target address registers */
98	struct musb_tar_regs {
99		u8	txfuncaddr;
100		u8	reserved0;
101		u8	txhubaddr;
102		u8	txhubport;
103		u8	rxfuncaddr;
104		u8	reserved1;
105		u8	rxhubaddr;
106		u8	rxhubport;
107	} tar[16];
108	/*
109	 * endpoint registers
110	 * ep0 elements are valid when array index is 0
111	 * otherwise epN is valid
112	 */
113	union musb_ep_regs {
114		struct musb_ep0_regs ep0;
115		struct musb_epN_regs epN;
116	} ep[16];
117
118} __attribute__((packed));
119#endif
120
121/*
122 * MUSB Register bits
123 */
124
125/* POWER */
126#define MUSB_POWER_ISOUPDATE	0x80
127#define MUSB_POWER_SOFTCONN	0x40
128#define MUSB_POWER_HSENAB	0x20
129#define MUSB_POWER_HSMODE	0x10
130#define MUSB_POWER_RESET	0x08
131#define MUSB_POWER_RESUME	0x04
132#define MUSB_POWER_SUSPENDM	0x02
133#define MUSB_POWER_ENSUSPEND	0x01
134#define MUSB_POWER_HSMODE_SHIFT	4
135
136/* INTRUSB */
137#define MUSB_INTR_SUSPEND	0x01
138#define MUSB_INTR_RESUME	0x02
139#define MUSB_INTR_RESET		0x04
140#define MUSB_INTR_BABBLE	0x04
141#define MUSB_INTR_SOF		0x08
142#define MUSB_INTR_CONNECT	0x10
143#define MUSB_INTR_DISCONNECT	0x20
144#define MUSB_INTR_SESSREQ	0x40
145#define MUSB_INTR_VBUSERROR	0x80	/* For SESSION end */
146
147/* DEVCTL */
148#define MUSB_DEVCTL_BDEVICE	0x80
149#define MUSB_DEVCTL_FSDEV	0x40
150#define MUSB_DEVCTL_LSDEV	0x20
151#define MUSB_DEVCTL_VBUS	0x18
152#define MUSB_DEVCTL_VBUS_SHIFT	3
153#define MUSB_DEVCTL_HM		0x04
154#define MUSB_DEVCTL_HR		0x02
155#define MUSB_DEVCTL_SESSION	0x01
156
157/* ULPI VBUSCONTROL */
158#define ULPI_USE_EXTVBUS	0x01
159#define ULPI_USE_EXTVBUSIND	0x02
160
161/* TESTMODE */
162#define MUSB_TEST_FORCE_HOST	0x80
163#define MUSB_TEST_FIFO_ACCESS	0x40
164#define MUSB_TEST_FORCE_FS	0x20
165#define MUSB_TEST_FORCE_HS	0x10
166#define MUSB_TEST_PACKET	0x08
167#define MUSB_TEST_K		0x04
168#define MUSB_TEST_J		0x02
169#define MUSB_TEST_SE0_NAK	0x01
170
171/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
172#define MUSB_FIFOSZ_DPB		0x10
173/* Allocation size (8, 16, 32, ... 4096) */
174#define MUSB_FIFOSZ_SIZE	0x0f
175
176/* CSR0 */
177#define MUSB_CSR0_FLUSHFIFO	0x0100
178#define MUSB_CSR0_TXPKTRDY	0x0002
179#define MUSB_CSR0_RXPKTRDY	0x0001
180
181/* CSR0 in Peripheral mode */
182#define MUSB_CSR0_P_SVDSETUPEND	0x0080
183#define MUSB_CSR0_P_SVDRXPKTRDY	0x0040
184#define MUSB_CSR0_P_SENDSTALL	0x0020
185#define MUSB_CSR0_P_SETUPEND	0x0010
186#define MUSB_CSR0_P_DATAEND	0x0008
187#define MUSB_CSR0_P_SENTSTALL	0x0004
188
189/* CSR0 in Host mode */
190#define MUSB_CSR0_H_DIS_PING		0x0800
191#define MUSB_CSR0_H_WR_DATATOGGLE	0x0400	/* Set to allow setting: */
192#define MUSB_CSR0_H_DATATOGGLE		0x0200	/* Data toggle control */
193#define MUSB_CSR0_H_NAKTIMEOUT		0x0080
194#define MUSB_CSR0_H_STATUSPKT		0x0040
195#define MUSB_CSR0_H_REQPKT		0x0020
196#define MUSB_CSR0_H_ERROR		0x0010
197#define MUSB_CSR0_H_SETUPPKT		0x0008
198#define MUSB_CSR0_H_RXSTALL		0x0004
199
200/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
201#define MUSB_CSR0_P_WZC_BITS	\
202	(MUSB_CSR0_P_SENTSTALL)
203#define MUSB_CSR0_H_WZC_BITS	\
204	(MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
205	| MUSB_CSR0_RXPKTRDY)
206
207/* TxType/RxType */
208#define MUSB_TYPE_SPEED		0xc0
209#define MUSB_TYPE_SPEED_SHIFT	6
210#define MUSB_TYPE_SPEED_HIGH	1
211#define MUSB_TYPE_SPEED_FULL	2
212#define MUSB_TYPE_SPEED_LOW	3
213#define MUSB_TYPE_PROTO		0x30	/* Implicitly zero for ep0 */
214#define MUSB_TYPE_PROTO_SHIFT	4
215#define MUSB_TYPE_REMOTE_END	0xf	/* Implicitly zero for ep0 */
216#define MUSB_TYPE_PROTO_BULK	2
217#define MUSB_TYPE_PROTO_INTR	3
218
219/* CONFIGDATA */
220#define MUSB_CONFIGDATA_MPRXE		0x80	/* Auto bulk pkt combining */
221#define MUSB_CONFIGDATA_MPTXE		0x40	/* Auto bulk pkt splitting */
222#define MUSB_CONFIGDATA_BIGENDIAN	0x20
223#define MUSB_CONFIGDATA_HBRXE		0x10	/* HB-ISO for RX */
224#define MUSB_CONFIGDATA_HBTXE		0x08	/* HB-ISO for TX */
225#define MUSB_CONFIGDATA_DYNFIFO		0x04	/* Dynamic FIFO sizing */
226#define MUSB_CONFIGDATA_SOFTCONE	0x02	/* SoftConnect */
227#define MUSB_CONFIGDATA_UTMIDW		0x01	/* Data width 0/1 => 8/16bits */
228
229/* TXCSR in Peripheral and Host mode */
230#define MUSB_TXCSR_AUTOSET		0x8000
231#define MUSB_TXCSR_MODE			0x2000
232#define MUSB_TXCSR_DMAENAB		0x1000
233#define MUSB_TXCSR_FRCDATATOG		0x0800
234#define MUSB_TXCSR_DMAMODE		0x0400
235#define MUSB_TXCSR_CLRDATATOG		0x0040
236#define MUSB_TXCSR_FLUSHFIFO		0x0008
237#define MUSB_TXCSR_FIFONOTEMPTY		0x0002
238#define MUSB_TXCSR_TXPKTRDY		0x0001
239
240/* TXCSR in Peripheral mode */
241#define MUSB_TXCSR_P_ISO		0x4000
242#define MUSB_TXCSR_P_INCOMPTX		0x0080
243#define MUSB_TXCSR_P_SENTSTALL		0x0020
244#define MUSB_TXCSR_P_SENDSTALL		0x0010
245#define MUSB_TXCSR_P_UNDERRUN		0x0004
246
247/* TXCSR in Host mode */
248#define MUSB_TXCSR_H_WR_DATATOGGLE	0x0200
249#define MUSB_TXCSR_H_DATATOGGLE		0x0100
250#define MUSB_TXCSR_H_NAKTIMEOUT		0x0080
251#define MUSB_TXCSR_H_RXSTALL		0x0020
252#define MUSB_TXCSR_H_ERROR		0x0004
253#define MUSB_TXCSR_H_DATATOGGLE_SHIFT	8
254
255/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
256#define MUSB_TXCSR_P_WZC_BITS	\
257	(MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
258	| MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
259#define MUSB_TXCSR_H_WZC_BITS	\
260	(MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
261	| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
262
263/* RXCSR in Peripheral and Host mode */
264#define MUSB_RXCSR_AUTOCLEAR		0x8000
265#define MUSB_RXCSR_DMAENAB		0x2000
266#define MUSB_RXCSR_DISNYET		0x1000
267#define MUSB_RXCSR_PID_ERR		0x1000
268#define MUSB_RXCSR_DMAMODE		0x0800
269#define MUSB_RXCSR_INCOMPRX		0x0100
270#define MUSB_RXCSR_CLRDATATOG		0x0080
271#define MUSB_RXCSR_FLUSHFIFO		0x0010
272#define MUSB_RXCSR_DATAERROR		0x0008
273#define MUSB_RXCSR_FIFOFULL		0x0002
274#define MUSB_RXCSR_RXPKTRDY		0x0001
275
276/* RXCSR in Peripheral mode */
277#define MUSB_RXCSR_P_ISO		0x4000
278#define MUSB_RXCSR_P_SENTSTALL		0x0040
279#define MUSB_RXCSR_P_SENDSTALL		0x0020
280#define MUSB_RXCSR_P_OVERRUN		0x0004
281
282/* RXCSR in Host mode */
283#define MUSB_RXCSR_H_AUTOREQ		0x4000
284#define MUSB_RXCSR_H_WR_DATATOGGLE	0x0400
285#define MUSB_RXCSR_H_DATATOGGLE		0x0200
286#define MUSB_RXCSR_H_RXSTALL		0x0040
287#define MUSB_RXCSR_H_REQPKT		0x0020
288#define MUSB_RXCSR_H_ERROR		0x0004
289#define MUSB_S_RXCSR_H_DATATOGGLE	9
290
291/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
292#define MUSB_RXCSR_P_WZC_BITS	\
293	(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
294	| MUSB_RXCSR_RXPKTRDY)
295#define MUSB_RXCSR_H_WZC_BITS	\
296	(MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
297	| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
298
299/* HUBADDR */
300#define MUSB_HUBADDR_MULTI_TT		0x80
301
302/* Endpoint configuration information. Note: The value of endpoint fifo size
303 * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other
304 * values are not supported
305 */
306struct musb_epinfo {
307	u8	epnum;	/* endpoint number	*/
308	u8	epdir;	/* endpoint direction	*/
309	u16	epsize;	/* endpoint FIFO size	*/
310};
311
312/*
313 * Platform specific MUSB configuration. Any platform using the musb
314 * functionality should create one instance of this structure in the
315 * platform specific file.
316 */
317struct musb_config {
318	struct	musb_regs	*regs;
319	u32			timeout;
320	u8			musb_speed;
321	u8			extvbus;
322};
323
324/* externally defined data */
325extern struct musb_config	musb_cfg;
326extern struct musb_regs		*musbr;
327
328/* exported functions */
329extern void musb_start(void);
330extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
331extern void write_fifo(u8 ep, u32 length, void *fifo_data);
332extern void read_fifo(u8 ep, u32 length, void *fifo_data);
333
334static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
335{
336	return readb(&musbr->ulpi_busctl);
337}
338static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
339{
340	writeb(val, &musbr->ulpi_busctl);
341}
342
343#endif	/* __MUSB_HDRC_DEFS_H__ */
344