1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Mediatek "glue layer" 4 * 5 * Copyright (C) 2019-2021 by Mediatek 6 * Based on the AllWinner SUNXI "glue layer" code. 7 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 8 * Copyright (C) 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi> 9 * 10 * This file is part of the Inventra Controller Driver for Linux. 11 */ 12#include <common.h> 13#include <clk.h> 14#include <dm.h> 15#include <dm/device_compat.h> 16#include <dm/lists.h> 17#include <dm/root.h> 18#include <linux/delay.h> 19#include <linux/printk.h> 20#include <linux/usb/musb.h> 21#include <usb.h> 22#include "linux-compat.h" 23#include "musb_core.h" 24#include "musb_uboot.h" 25 26#define DBG_I(fmt, ...) \ 27 pr_info(fmt, ##__VA_ARGS__) 28 29struct mtk_musb_config { 30 struct musb_hdrc_config *config; 31}; 32 33struct mtk_musb_glue { 34 struct musb_host_data mdata; 35 struct clk usbpllclk; 36 struct clk usbmcuclk; 37 struct clk usbclk; 38 struct mtk_musb_config *cfg; 39 struct device dev; 40}; 41 42#define to_mtk_musb_glue(d) container_of(d, struct mtk_musb_glue, dev) 43 44/****************************************************************************** 45 * phy settings 46 ******************************************************************************/ 47#define USB20_PHY_BASE 0x11110800 48#define USBPHY_READ8(offset) \ 49 readb((void *)(USB20_PHY_BASE + (offset))) 50#define USBPHY_WRITE8(offset, value) \ 51 writeb(value, (void *)(USB20_PHY_BASE + (offset))) 52#define USBPHY_SET8(offset, mask) \ 53 USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask)) 54#define USBPHY_CLR8(offset, mask) \ 55 USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~(mask))) 56 57static void mt_usb_phy_poweron(void) 58{ 59 /* 60 * switch to USB function. 61 * (system register, force ip into usb mode). 62 */ 63 USBPHY_CLR8(0x6b, 0x04); 64 USBPHY_CLR8(0x6e, 0x01); 65 USBPHY_CLR8(0x21, 0x03); 66 67 /* RG_USB20_BC11_SW_EN = 1'b0 */ 68 USBPHY_SET8(0x22, 0x04); 69 USBPHY_CLR8(0x1a, 0x80); 70 71 /* RG_USB20_DP_100K_EN = 1'b0 */ 72 /* RG_USB20_DP_100K_EN = 1'b0 */ 73 USBPHY_CLR8(0x22, 0x03); 74 75 /*OTG enable*/ 76 USBPHY_SET8(0x20, 0x10); 77 /* release force suspendm */ 78 USBPHY_CLR8(0x6a, 0x04); 79 80 mdelay(800); 81 82 /* force enter device mode */ 83 USBPHY_CLR8(0x6c, 0x10); 84 USBPHY_SET8(0x6c, 0x2E); 85 USBPHY_SET8(0x6d, 0x3E); 86} 87 88static void mt_usb_phy_savecurrent(void) 89{ 90 /* 91 * switch to USB function. 92 * (system register, force ip into usb mode). 93 */ 94 USBPHY_CLR8(0x6b, 0x04); 95 USBPHY_CLR8(0x6e, 0x01); 96 USBPHY_CLR8(0x21, 0x03); 97 98 /* release force suspendm */ 99 USBPHY_CLR8(0x6a, 0x04); 100 USBPHY_SET8(0x68, 0x04); 101 /* RG_DPPULLDOWN./RG_DMPULLDOWN. */ 102 USBPHY_SET8(0x68, 0xc0); 103 /* RG_XCVRSEL[1:0] = 2'b01 */ 104 USBPHY_CLR8(0x68, 0x30); 105 USBPHY_SET8(0x68, 0x10); 106 /* RG_TERMSEL = 1'b1 */ 107 USBPHY_SET8(0x68, 0x04); 108 /* RG_DATAIN[3:0] = 4'b0000 */ 109 USBPHY_CLR8(0x69, 0x3c); 110 111 /* 112 * force_dp_pulldown, force_dm_pulldown, 113 * force_xcversel, force_termsel. 114 */ 115 USBPHY_SET8(0x6a, 0xba); 116 117 /* RG_USB20_BC11_SW_EN = 1'b0 */ 118 USBPHY_CLR8(0x1a, 0x80); 119 /* RG_USB20_OTG_VBUSSCMP_EN = 1'b0 */ 120 USBPHY_CLR8(0x1a, 0x10); 121 122 mdelay(800); 123 124 USBPHY_CLR8(0x6a, 0x04); 125 /* rg_usb20_pll_stable = 1 */ 126 //USBPHY_SET8(0x63, 0x02); 127 128 mdelay(1); 129 130 /* force suspendm = 1 */ 131 //USBPHY_SET8(0x6a, 0x04); 132} 133 134static void mt_usb_phy_recover(void) 135{ 136 /* clean PUPD_BIST_EN */ 137 /* PUPD_BIST_EN = 1'b0 */ 138 /* PMIC will use it to detect charger type */ 139 USBPHY_CLR8(0x1d, 0x10); 140 141 /* force_uart_en = 1'b0 */ 142 USBPHY_CLR8(0x6b, 0x04); 143 /* RG_UART_EN = 1'b0 */ 144 USBPHY_CLR8(0x6e, 0x01); 145 /* force_uart_en = 1'b0 */ 146 USBPHY_CLR8(0x6a, 0x04); 147 148 USBPHY_CLR8(0x21, 0x03); 149 USBPHY_CLR8(0x68, 0xf4); 150 151 /* RG_DATAIN[3:0] = 4'b0000 */ 152 USBPHY_CLR8(0x69, 0x3c); 153 154 USBPHY_CLR8(0x6a, 0xba); 155 156 /* RG_USB20_BC11_SW_EN = 1'b0 */ 157 USBPHY_CLR8(0x1a, 0x80); 158 /* RG_USB20_OTG_VBUSSCMP_EN = 1'b1 */ 159 USBPHY_SET8(0x1a, 0x10); 160 161 //HQA adjustment 162 USBPHY_CLR8(0x18, 0x08); 163 USBPHY_SET8(0x18, 0x06); 164 mdelay(800); 165 166 /* force enter device mode */ 167 //USBPHY_CLR8(0x6c, 0x10); 168 //USBPHY_SET8(0x6c, 0x2E); 169 //USBPHY_SET8(0x6d, 0x3E); 170 171 /* enable VRT internal R architecture */ 172 /* RG_USB20_INTR_EN = 1'b1 */ 173 USBPHY_SET8(0x00, 0x20); 174} 175 176/****************************************************************************** 177 * MUSB Glue code 178 ******************************************************************************/ 179 180static irqreturn_t mtk_musb_interrupt(int irq, void *__hci) 181{ 182 struct musb *musb = __hci; 183 irqreturn_t retval = IRQ_NONE; 184 185 /* read and flush interrupts */ 186 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 187// last_int_usb = musb->int_usb; 188 if (musb->int_usb) 189 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); 190 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 191 if (musb->int_tx) 192 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); 193 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 194 if (musb->int_rx) 195 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); 196 197 if (musb->int_usb || musb->int_tx || musb->int_rx) 198 retval |= musb_interrupt(musb); 199 200 return retval; 201} 202 203/* musb_core does not call enable / disable in a balanced manner <sigh> */ 204static bool enabled; 205 206static int mtk_musb_enable(struct musb *musb) 207{ 208 struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller); 209 210 DBG_I("%s():\n", __func__); 211 212 musb_ep_select(musb->mregs, 0); 213 musb_writeb(musb->mregs, MUSB_FADDR, 0); 214 215 if (enabled) 216 return 0; 217 218 mt_usb_phy_recover(); 219 220 enabled = true; 221 222 return 0; 223} 224 225static void mtk_musb_disable(struct musb *musb) 226{ 227 struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller); 228 int ret; 229 230 DBG_I("%s():\n", __func__); 231 232 if (!enabled) 233 return; 234 235 mt_usb_phy_savecurrent(); 236 237 enabled = false; 238} 239 240static int mtk_musb_init(struct musb *musb) 241{ 242 struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller); 243 int ret; 244 245 DBG_I("%s():\n", __func__); 246 247 ret = clk_enable(&glue->usbpllclk); 248 if (ret) { 249 dev_err(musb->controller, "failed to enable usbpll clock\n"); 250 return ret; 251 } 252 ret = clk_enable(&glue->usbmcuclk); 253 if (ret) { 254 dev_err(musb->controller, "failed to enable usbmcu clock\n"); 255 return ret; 256 } 257 ret = clk_enable(&glue->usbclk); 258 if (ret) { 259 dev_err(musb->controller, "failed to enable usb clock\n"); 260 return ret; 261 } 262 263 musb->isr = mtk_musb_interrupt; 264 265 return 0; 266} 267 268static int mtk_musb_exit(struct musb *musb) 269{ 270 struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller); 271 272 clk_disable(&glue->usbclk); 273 clk_disable(&glue->usbmcuclk); 274 clk_disable(&glue->usbpllclk); 275 276 return 0; 277} 278 279static const struct musb_platform_ops mtk_musb_ops = { 280 .init = mtk_musb_init, 281 .exit = mtk_musb_exit, 282 .enable = mtk_musb_enable, 283 .disable = mtk_musb_disable, 284}; 285 286/* MTK OTG supports up to 7 endpoints */ 287#define MTK_MUSB_MAX_EP_NUM 8 288#define MTK_MUSB_RAM_BITS 16 289 290static struct musb_fifo_cfg mtk_musb_mode_cfg[] = { 291 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 292 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 293 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 294 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 295 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 296 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 297 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 298 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 299 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 300 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 301 MUSB_EP_FIFO_SINGLE(6, FIFO_TX, 512), 302 MUSB_EP_FIFO_SINGLE(6, FIFO_RX, 512), 303 MUSB_EP_FIFO_SINGLE(7, FIFO_TX, 512), 304 MUSB_EP_FIFO_SINGLE(7, FIFO_RX, 512), 305}; 306 307static struct musb_hdrc_config musb_config = { 308 .fifo_cfg = mtk_musb_mode_cfg, 309 .fifo_cfg_size = ARRAY_SIZE(mtk_musb_mode_cfg), 310 .multipoint = true, 311 .dyn_fifo = true, 312 .num_eps = MTK_MUSB_MAX_EP_NUM, 313 .ram_bits = MTK_MUSB_RAM_BITS, 314}; 315 316static int musb_usb_probe(struct udevice *dev) 317{ 318 struct mtk_musb_glue *glue = dev_get_priv(dev); 319 struct musb_host_data *host = &glue->mdata; 320 struct musb_hdrc_platform_data pdata; 321 void *base = dev_read_addr_ptr(dev); 322 int ret; 323 324 DBG_I("%s():\n", __func__); 325 326#ifdef CONFIG_USB_MUSB_HOST 327 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 328#endif 329 330 if (!base) 331 return -EINVAL; 332 333 glue->cfg = (struct mtk_musb_config *)dev_get_driver_data(dev); 334 if (!glue->cfg) 335 return -EINVAL; 336 337 ret = clk_get_by_name(dev, "usbpll", &glue->usbpllclk); 338 if (ret) { 339 dev_err(dev, "failed to get usbpll clock\n"); 340 return ret; 341 } 342 ret = clk_get_by_name(dev, "usbmcu", &glue->usbmcuclk); 343 if (ret) { 344 dev_err(dev, "failed to get usbmcu clock\n"); 345 return ret; 346 } 347 ret = clk_get_by_name(dev, "usb", &glue->usbclk); 348 if (ret) { 349 dev_err(dev, "failed to get usb clock\n"); 350 return ret; 351 } 352 353 memset(&pdata, 0, sizeof(pdata)); 354 pdata.power = (u8)400; 355 pdata.platform_ops = &mtk_musb_ops; 356 pdata.config = glue->cfg->config; 357 358#ifdef CONFIG_USB_MUSB_HOST 359 priv->desc_before_addr = true; 360 361 pdata.mode = MUSB_HOST; 362 host->host = musb_init_controller(&pdata, &glue->dev, base); 363 if (!host->host) 364 return -EIO; 365 366 ret = musb_lowlevel_init(host); 367 if (!ret) 368 printf("MTK MUSB OTG (Host)\n"); 369#else 370 pdata.mode = MUSB_PERIPHERAL; 371 host->host = musb_register(&pdata, &glue->dev, base); 372 if (!host->host) 373 return -EIO; 374 375 printf("MTK MUSB OTG (Peripheral)\n"); 376#endif 377 378 mt_usb_phy_poweron(); 379 380 return ret; 381} 382 383static int musb_usb_remove(struct udevice *dev) 384{ 385 struct mtk_musb_glue *glue = dev_get_priv(dev); 386 struct musb_host_data *host = &glue->mdata; 387 388 musb_stop(host->host); 389 free(host->host); 390 host->host = NULL; 391 392 return 0; 393} 394 395static const struct mtk_musb_config mt8518_cfg = { 396 .config = &musb_config, 397}; 398 399static const struct udevice_id mtk_musb_ids[] = { 400 { .compatible = "mediatek,mt8518-musb", 401 .data = (ulong)&mt8518_cfg }, 402 { } 403}; 404 405U_BOOT_DRIVER(mtk_musb) = { 406 .name = "mtk_musb", 407#ifdef CONFIG_USB_MUSB_HOST 408 .id = UCLASS_USB, 409#else 410 .id = UCLASS_USB_GADGET_GENERIC, 411#endif 412 .of_match = mtk_musb_ids, 413 .probe = musb_usb_probe, 414 .remove = musb_usb_remove, 415#ifdef CONFIG_USB_MUSB_HOST 416 .ops = &musb_usb_ops, 417#endif 418 .plat_auto = sizeof(struct usb_plat), 419 .priv_auto = sizeof(struct mtk_musb_glue), 420}; 421