1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * USB HOST XHCI Controller stack 4 * 5 * Based on xHCI host controller driver in linux-kernel 6 * by Sarah Sharp. 7 * 8 * Copyright (C) 2008 Intel Corp. 9 * Author: Sarah Sharp 10 * 11 * Copyright (C) 2013 Samsung Electronics Co.Ltd 12 * Authors: Vivek Gautam <gautam.vivek@samsung.com> 13 * Vikas Sajjan <vikas.sajjan@samsung.com> 14 */ 15 16/** 17 * This file gives the xhci stack for usb3.0 looking into 18 * xhci specification Rev1.0 (5/21/10). 19 * The quirk devices support hasn't been given yet. 20 */ 21 22#include <common.h> 23#include <cpu_func.h> 24#include <dm.h> 25#include <dm/device_compat.h> 26#include <log.h> 27#include <malloc.h> 28#include <usb.h> 29#include <usb/xhci.h> 30#include <watchdog.h> 31#include <asm/byteorder.h> 32#include <asm/cache.h> 33#include <asm/unaligned.h> 34#include <linux/bitops.h> 35#include <linux/bug.h> 36#include <linux/delay.h> 37#include <linux/errno.h> 38#include <linux/iopoll.h> 39 40static struct descriptor { 41 struct usb_hub_descriptor hub; 42 struct usb_device_descriptor device; 43 struct usb_config_descriptor config; 44 struct usb_interface_descriptor interface; 45 struct usb_endpoint_descriptor endpoint; 46 struct usb_ss_ep_comp_descriptor ep_companion; 47} __attribute__ ((packed)) descriptor = { 48 { 49 0xc, /* bDescLength */ 50 0x2a, /* bDescriptorType: hub descriptor */ 51 2, /* bNrPorts -- runtime modified */ 52 cpu_to_le16(0x8), /* wHubCharacteristics */ 53 10, /* bPwrOn2PwrGood */ 54 0, /* bHubCntrCurrent */ 55 { /* Device removable */ 56 } /* at most 7 ports! XXX */ 57 }, 58 { 59 0x12, /* bLength */ 60 1, /* bDescriptorType: UDESC_DEVICE */ 61 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */ 62 9, /* bDeviceClass: UDCLASS_HUB */ 63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 64 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */ 65 9, /* bMaxPacketSize: 512 bytes 2^9 */ 66 0x0000, /* idVendor */ 67 0x0000, /* idProduct */ 68 cpu_to_le16(0x0100), /* bcdDevice */ 69 1, /* iManufacturer */ 70 2, /* iProduct */ 71 0, /* iSerialNumber */ 72 1 /* bNumConfigurations: 1 */ 73 }, 74 { 75 0x9, 76 2, /* bDescriptorType: UDESC_CONFIG */ 77 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */ 78 1, /* bNumInterface */ 79 1, /* bConfigurationValue */ 80 0, /* iConfiguration */ 81 0x40, /* bmAttributes: UC_SELF_POWER */ 82 0 /* bMaxPower */ 83 }, 84 { 85 0x9, /* bLength */ 86 4, /* bDescriptorType: UDESC_INTERFACE */ 87 0, /* bInterfaceNumber */ 88 0, /* bAlternateSetting */ 89 1, /* bNumEndpoints */ 90 9, /* bInterfaceClass: UICLASS_HUB */ 91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 93 0 /* iInterface */ 94 }, 95 { 96 0x7, /* bLength */ 97 5, /* bDescriptorType: UDESC_ENDPOINT */ 98 0x81, /* bEndpointAddress: IN endpoint 1 */ 99 3, /* bmAttributes: UE_INTERRUPT */ 100 8, /* wMaxPacketSize */ 101 255 /* bInterval */ 102 }, 103 { 104 0x06, /* ss_bLength */ 105 0x30, /* ss_bDescriptorType: SS EP Companion */ 106 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */ 107 /* ss_bmAttributes: 1 packet per service interval */ 108 0x00, 109 /* ss_wBytesPerInterval: 15 bits for max 15 ports */ 110 cpu_to_le16(0x02), 111 }, 112}; 113 114struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) 115{ 116 struct udevice *dev; 117 118 /* Find the USB controller */ 119 for (dev = udev->dev; 120 device_get_uclass_id(dev) != UCLASS_USB; 121 dev = dev->parent) 122 ; 123 return dev_get_priv(dev); 124} 125 126/** 127 * Waits for as per specified amount of time 128 * for the "result" to match with "done" 129 * 130 * @param ptr pointer to the register to be read 131 * @param mask mask for the value read 132 * @param done value to be campared with result 133 * @param usec time to wait till 134 * Return: 0 if handshake is success else < 0 on failure 135 */ 136static int 137handshake(uint32_t volatile *ptr, uint32_t mask, uint32_t done, int usec) 138{ 139 uint32_t result; 140 int ret; 141 142 ret = readx_poll_sleep_timeout(xhci_readl, ptr, result, 143 (result & mask) == done || result == U32_MAX, 144 1, usec); 145 if (result == U32_MAX) /* card removed */ 146 return -ENODEV; 147 148 return ret; 149} 150 151/** 152 * Set the run bit and wait for the host to be running. 153 * 154 * @param hcor pointer to host controller operation registers 155 * Return: status of the Handshake 156 */ 157static int xhci_start(struct xhci_hcor *hcor) 158{ 159 u32 temp; 160 int ret; 161 162 puts("Starting the controller\n"); 163 temp = xhci_readl(&hcor->or_usbcmd); 164 temp |= (CMD_RUN); 165 xhci_writel(&hcor->or_usbcmd, temp); 166 167 /* 168 * Wait for the HCHalted Status bit to be 0 to indicate the host is 169 * running. 170 */ 171 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC); 172 if (ret) 173 debug("Host took too long to start, " 174 "waited %u microseconds.\n", 175 XHCI_MAX_HALT_USEC); 176 return ret; 177} 178 179/** 180 * Resets the XHCI Controller 181 * 182 * @param hcor pointer to host controller operation registers 183 * Return: -EBUSY if XHCI Controller is not halted else status of handshake 184 */ 185static int xhci_reset(struct xhci_hcor *hcor) 186{ 187 u32 cmd; 188 u32 state; 189 int ret; 190 191 /* Halting the Host first */ 192 debug("// Halt the HC: %p\n", hcor); 193 state = xhci_readl(&hcor->or_usbsts) & STS_HALT; 194 if (!state) { 195 cmd = xhci_readl(&hcor->or_usbcmd); 196 cmd &= ~CMD_RUN; 197 xhci_writel(&hcor->or_usbcmd, cmd); 198 } 199 200 ret = handshake(&hcor->or_usbsts, 201 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); 202 if (ret) { 203 printf("Host not halted after %u microseconds.\n", 204 XHCI_MAX_HALT_USEC); 205 return -EBUSY; 206 } 207 208 debug("// Reset the HC\n"); 209 cmd = xhci_readl(&hcor->or_usbcmd); 210 cmd |= CMD_RESET; 211 xhci_writel(&hcor->or_usbcmd, cmd); 212 213 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC); 214 if (ret) 215 return ret; 216 217 /* 218 * xHCI cannot write to any doorbells or operational registers other 219 * than status until the "Controller Not Ready" flag is cleared. 220 */ 221 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC); 222} 223 224/** 225 * Used for passing endpoint bitmasks between the core and HCDs. 226 * Find the index for an endpoint given its descriptor. 227 * Use the return value to right shift 1 for the bitmask. 228 * 229 * Index = (epnum * 2) + direction - 1, 230 * where direction = 0 for OUT, 1 for IN. 231 * For control endpoints, the IN index is used (OUT index is unused), so 232 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) 233 * 234 * @param desc USB enpdoint Descriptor 235 * Return: index of the Endpoint 236 */ 237static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc) 238{ 239 unsigned int index; 240 241 if (usb_endpoint_xfer_control(desc)) 242 index = (unsigned int)(usb_endpoint_num(desc) * 2); 243 else 244 index = (unsigned int)((usb_endpoint_num(desc) * 2) - 245 (usb_endpoint_dir_in(desc) ? 0 : 1)); 246 247 return index; 248} 249 250/* 251 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of 252 * microframes, rounded down to nearest power of 2. 253 */ 254static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval, 255 unsigned int min_exponent, 256 unsigned int max_exponent) 257{ 258 unsigned int interval; 259 260 interval = fls(desc_interval) - 1; 261 interval = clamp_val(interval, min_exponent, max_exponent); 262 if ((1 << interval) != desc_interval) 263 debug("rounding interval to %d microframes, "\ 264 "ep desc says %d microframes\n", 265 1 << interval, desc_interval); 266 267 return interval; 268} 269 270static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, 271 struct usb_endpoint_descriptor *endpt_desc) 272{ 273 if (endpt_desc->bInterval == 0) 274 return 0; 275 276 return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15); 277} 278 279static unsigned int xhci_parse_frame_interval(struct usb_device *udev, 280 struct usb_endpoint_descriptor *endpt_desc) 281{ 282 return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10); 283} 284 285/* 286 * Convert interval expressed as 2^(bInterval - 1) == interval into 287 * straight exponent value 2^n == interval. 288 */ 289static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, 290 struct usb_endpoint_descriptor *endpt_desc) 291{ 292 unsigned int interval; 293 294 interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1; 295 if (interval != endpt_desc->bInterval - 1) 296 debug("ep %#x - rounding interval to %d %sframes\n", 297 endpt_desc->bEndpointAddress, 1 << interval, 298 udev->speed == USB_SPEED_FULL ? "" : "micro"); 299 300 if (udev->speed == USB_SPEED_FULL) { 301 /* 302 * Full speed isoc endpoints specify interval in frames, 303 * not microframes. We are using microframes everywhere, 304 * so adjust accordingly. 305 */ 306 interval += 3; /* 1 frame = 2^3 uframes */ 307 } 308 309 return interval; 310} 311 312/* 313 * Return the polling or NAK interval. 314 * 315 * The polling interval is expressed in "microframes". If xHCI's Interval field 316 * is set to N, it will service the endpoint every 2^(Interval)*125us. 317 * 318 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval 319 * is set to 0. 320 */ 321static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, 322 struct usb_endpoint_descriptor *endpt_desc) 323{ 324 unsigned int interval = 0; 325 326 switch (udev->speed) { 327 case USB_SPEED_HIGH: 328 /* Max NAK rate */ 329 if (usb_endpoint_xfer_control(endpt_desc) || 330 usb_endpoint_xfer_bulk(endpt_desc)) { 331 interval = xhci_parse_microframe_interval(udev, 332 endpt_desc); 333 break; 334 } 335 /* Fall through - SS and HS isoc/int have same decoding */ 336 337 case USB_SPEED_SUPER: 338 if (usb_endpoint_xfer_int(endpt_desc) || 339 usb_endpoint_xfer_isoc(endpt_desc)) { 340 interval = xhci_parse_exponent_interval(udev, 341 endpt_desc); 342 } 343 break; 344 345 case USB_SPEED_FULL: 346 if (usb_endpoint_xfer_isoc(endpt_desc)) { 347 interval = xhci_parse_exponent_interval(udev, 348 endpt_desc); 349 break; 350 } 351 /* 352 * Fall through for interrupt endpoint interval decoding 353 * since it uses the same rules as low speed interrupt 354 * endpoints. 355 */ 356 357 case USB_SPEED_LOW: 358 if (usb_endpoint_xfer_int(endpt_desc) || 359 usb_endpoint_xfer_isoc(endpt_desc)) { 360 interval = xhci_parse_frame_interval(udev, endpt_desc); 361 } 362 break; 363 364 default: 365 BUG(); 366 } 367 368 return interval; 369} 370 371/* 372 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. 373 * High speed endpoint descriptors can define "the number of additional 374 * transaction opportunities per microframe", but that goes in the Max Burst 375 * endpoint context field. 376 */ 377static u32 xhci_get_endpoint_mult(struct usb_device *udev, 378 struct usb_endpoint_descriptor *endpt_desc, 379 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc) 380{ 381 if (udev->speed < USB_SPEED_SUPER || 382 !usb_endpoint_xfer_isoc(endpt_desc)) 383 return 0; 384 385 return ss_ep_comp_desc->bmAttributes; 386} 387 388static u32 xhci_get_endpoint_max_burst(struct usb_device *udev, 389 struct usb_endpoint_descriptor *endpt_desc, 390 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc) 391{ 392 /* Super speed and Plus have max burst in ep companion desc */ 393 if (udev->speed >= USB_SPEED_SUPER) 394 return ss_ep_comp_desc->bMaxBurst; 395 396 if (udev->speed == USB_SPEED_HIGH && 397 (usb_endpoint_xfer_isoc(endpt_desc) || 398 usb_endpoint_xfer_int(endpt_desc))) 399 return usb_endpoint_maxp_mult(endpt_desc) - 1; 400 401 return 0; 402} 403 404/* 405 * Return the maximum endpoint service interval time (ESIT) payload. 406 * Basically, this is the maxpacket size, multiplied by the burst size 407 * and mult size. 408 */ 409static u32 xhci_get_max_esit_payload(struct usb_device *udev, 410 struct usb_endpoint_descriptor *endpt_desc, 411 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc) 412{ 413 int max_burst; 414 int max_packet; 415 416 /* Only applies for interrupt or isochronous endpoints */ 417 if (usb_endpoint_xfer_control(endpt_desc) || 418 usb_endpoint_xfer_bulk(endpt_desc)) 419 return 0; 420 421 /* SuperSpeed Isoc ep with less than 48k per esit */ 422 if (udev->speed >= USB_SPEED_SUPER) 423 return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval); 424 425 max_packet = usb_endpoint_maxp(endpt_desc); 426 max_burst = usb_endpoint_maxp_mult(endpt_desc); 427 428 /* A 0 in max burst means 1 transfer per ESIT */ 429 return max_packet * max_burst; 430} 431 432/** 433 * Issue a configure endpoint command or evaluate context command 434 * and wait for it to finish. 435 * 436 * @param udev pointer to the Device Data Structure 437 * @param ctx_change flag to indicate the Context has changed or NOT 438 * Return: 0 on success, -1 on failure 439 */ 440static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change) 441{ 442 struct xhci_container_ctx *in_ctx; 443 struct xhci_virt_device *virt_dev; 444 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 445 union xhci_trb *event; 446 447 virt_dev = ctrl->devs[udev->slot_id]; 448 in_ctx = virt_dev->in_ctx; 449 450 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size); 451 xhci_queue_command(ctrl, in_ctx->dma, udev->slot_id, 0, 452 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP); 453 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); 454 if (!event) 455 return -ETIMEDOUT; 456 457 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) 458 != udev->slot_id); 459 460 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { 461 case COMP_SUCCESS: 462 debug("Successful %s command\n", 463 ctx_change ? "Evaluate Context" : "Configure Endpoint"); 464 break; 465 default: 466 printf("ERROR: %s command returned completion code %d.\n", 467 ctx_change ? "Evaluate Context" : "Configure Endpoint", 468 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); 469 return -EINVAL; 470 } 471 472 xhci_acknowledge_event(ctrl); 473 474 return 0; 475} 476 477/** 478 * Fill endpoint contexts for interface descriptor ifdesc. 479 * 480 * @param udev pointer to the USB device structure 481 * @param ctrl pointer to the xhci pravte device structure 482 * @param virt_dev pointer to the xhci virtual device structure 483 * @param ifdesc pointer to the USB interface config descriptor 484 * Return: returns the status of xhci_init_ep_contexts_if 485 */ 486static int xhci_init_ep_contexts_if(struct usb_device *udev, 487 struct xhci_ctrl *ctrl, 488 struct xhci_virt_device *virt_dev, 489 struct usb_interface *ifdesc 490 ) 491{ 492 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM]; 493 int cur_ep; 494 int ep_index; 495 unsigned int dir; 496 unsigned int ep_type; 497 u64 trb_64 = 0; 498 u32 max_esit_payload; 499 unsigned int interval; 500 unsigned int mult; 501 unsigned int max_burst; 502 unsigned int avg_trb_len; 503 unsigned int err_count = 0; 504 int num_of_ep = ifdesc->no_of_ep; 505 506 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { 507 struct usb_endpoint_descriptor *endpt_desc = NULL; 508 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL; 509 510 endpt_desc = &ifdesc->ep_desc[cur_ep]; 511 ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep]; 512 trb_64 = 0; 513 514 /* 515 * Get values to fill the endpoint context, mostly from ep 516 * descriptor. The average TRB buffer lengt for bulk endpoints 517 * is unclear as we have no clue on scatter gather list entry 518 * size. For Isoc and Int, set it to max available. 519 * See xHCI 1.1 spec 4.14.1.1 for details. 520 */ 521 max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc, 522 ss_ep_comp_desc); 523 interval = xhci_get_endpoint_interval(udev, endpt_desc); 524 mult = xhci_get_endpoint_mult(udev, endpt_desc, 525 ss_ep_comp_desc); 526 max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc, 527 ss_ep_comp_desc); 528 avg_trb_len = max_esit_payload; 529 530 ep_index = xhci_get_ep_index(endpt_desc); 531 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 532 ep_index); 533 534 /* Allocate the ep rings */ 535 virt_dev->eps[ep_index].ring = xhci_ring_alloc(ctrl, 1, true); 536 if (!virt_dev->eps[ep_index].ring) 537 return -ENOMEM; 538 539 /*NOTE: ep_desc[0] actually represents EP1 and so on */ 540 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7); 541 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2)); 542 543 ep_ctx[ep_index]->ep_info = 544 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | 545 EP_INTERVAL(interval) | EP_MULT(mult)); 546 547 ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type)); 548 ep_ctx[ep_index]->ep_info2 |= 549 cpu_to_le32(MAX_PACKET 550 (get_unaligned(&endpt_desc->wMaxPacketSize))); 551 552 /* Allow 3 retries for everything but isoc, set CErr = 3 */ 553 if (!usb_endpoint_xfer_isoc(endpt_desc)) 554 err_count = 3; 555 ep_ctx[ep_index]->ep_info2 |= 556 cpu_to_le32(MAX_BURST(max_burst) | 557 ERROR_COUNT(err_count)); 558 559 trb_64 = xhci_trb_virt_to_dma(virt_dev->eps[ep_index].ring->enq_seg, 560 virt_dev->eps[ep_index].ring->enqueue); 561 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 | 562 virt_dev->eps[ep_index].ring->cycle_state); 563 564 /* 565 * xHCI spec 6.2.3: 566 * 'Average TRB Length' should be 8 for control endpoints. 567 */ 568 if (usb_endpoint_xfer_control(endpt_desc)) 569 avg_trb_len = 8; 570 ep_ctx[ep_index]->tx_info = 571 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | 572 EP_AVG_TRB_LENGTH(avg_trb_len)); 573 574 /* 575 * The MediaTek xHCI defines some extra SW parameters which 576 * are put into reserved DWs in Slot and Endpoint Contexts 577 * for synchronous endpoints. 578 */ 579 if (ctrl->quirks & XHCI_MTK_HOST) { 580 ep_ctx[ep_index]->reserved[0] = 581 cpu_to_le32(EP_BPKTS(1) | EP_BBM(1)); 582 } 583 } 584 585 return 0; 586} 587 588/** 589 * Configure the endpoint, programming the device contexts. 590 * 591 * @param udev pointer to the USB device structure 592 * Return: returns the status of the xhci_configure_endpoints 593 */ 594static int xhci_set_configuration(struct usb_device *udev) 595{ 596 struct xhci_container_ctx *out_ctx; 597 struct xhci_container_ctx *in_ctx; 598 struct xhci_input_control_ctx *ctrl_ctx; 599 struct xhci_slot_ctx *slot_ctx; 600 int err; 601 int cur_ep; 602 int max_ep_flag = 0; 603 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 604 int num_of_ep; 605 int ep_flag = 0; 606 int slot_id = udev->slot_id; 607 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; 608 struct usb_interface *ifdesc; 609 unsigned int ifnum; 610 unsigned int max_ifnum = min((unsigned int)USB_MAX_ACTIVE_INTERFACES, 611 (unsigned int)udev->config.no_of_if); 612 613 out_ctx = virt_dev->out_ctx; 614 in_ctx = virt_dev->in_ctx; 615 616 ctrl_ctx = xhci_get_input_control_ctx(in_ctx); 617 /* Initialize the input context control */ 618 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); 619 ctrl_ctx->drop_flags = 0; 620 621 for (ifnum = 0; ifnum < max_ifnum; ifnum++) { 622 ifdesc = &udev->config.if_desc[ifnum]; 623 num_of_ep = ifdesc->no_of_ep; 624 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */ 625 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { 626 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]); 627 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1)); 628 if (max_ep_flag < ep_flag) 629 max_ep_flag = ep_flag; 630 } 631 } 632 633 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); 634 635 /* slot context */ 636 xhci_slot_copy(ctrl, in_ctx, out_ctx); 637 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); 638 slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK)); 639 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0); 640 641 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); 642 643 /* filling up ep contexts */ 644 for (ifnum = 0; ifnum < max_ifnum; ifnum++) { 645 ifdesc = &udev->config.if_desc[ifnum]; 646 err = xhci_init_ep_contexts_if(udev, ctrl, virt_dev, ifdesc); 647 if (err < 0) 648 return err; 649 } 650 651 return xhci_configure_endpoints(udev, false); 652} 653 654/** 655 * Issue an Address Device command (which will issue a SetAddress request to 656 * the device). 657 * 658 * @param udev pointer to the Device Data Structure 659 * Return: 0 if successful else error code on failure 660 */ 661static int xhci_address_device(struct usb_device *udev, int root_portnr) 662{ 663 int ret = 0; 664 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 665 struct xhci_slot_ctx *slot_ctx; 666 struct xhci_input_control_ctx *ctrl_ctx; 667 struct xhci_virt_device *virt_dev; 668 int slot_id = udev->slot_id; 669 union xhci_trb *event; 670 671 virt_dev = ctrl->devs[slot_id]; 672 673 /* 674 * This is the first Set Address since device plug-in 675 * so setting up the slot context. 676 */ 677 debug("Setting up addressable devices %p\n", ctrl->dcbaa); 678 xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr); 679 680 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 681 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); 682 ctrl_ctx->drop_flags = 0; 683 684 xhci_queue_command(ctrl, virt_dev->in_ctx->dma, 685 slot_id, 0, TRB_ADDR_DEV); 686 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); 687 if (!event) 688 return -ETIMEDOUT; 689 690 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id); 691 692 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { 693 case COMP_CTX_STATE: 694 case COMP_EBADSLT: 695 printf("Setup ERROR: address device command for slot %d.\n", 696 slot_id); 697 ret = -EINVAL; 698 break; 699 case COMP_TX_ERR: 700 puts("Device not responding to set address.\n"); 701 ret = -EPROTO; 702 break; 703 case COMP_DEV_ERR: 704 puts("ERROR: Incompatible device" 705 "for address device command.\n"); 706 ret = -ENODEV; 707 break; 708 case COMP_SUCCESS: 709 debug("Successful Address Device command\n"); 710 udev->status = 0; 711 break; 712 default: 713 printf("ERROR: unexpected command completion code 0x%x.\n", 714 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); 715 ret = -EINVAL; 716 break; 717 } 718 719 xhci_acknowledge_event(ctrl); 720 721 if (ret < 0) 722 /* 723 * TODO: Unsuccessful Address Device command shall leave the 724 * slot in default state. So, issue Disable Slot command now. 725 */ 726 return ret; 727 728 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes, 729 virt_dev->out_ctx->size); 730 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx); 731 732 debug("xHC internal address is: %d\n", 733 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); 734 735 return 0; 736} 737 738/** 739 * Issue Enable slot command to the controller to allocate 740 * device slot and assign the slot id. It fails if the xHC 741 * ran out of device slots, the Enable Slot command timed out, 742 * or allocating memory failed. 743 * 744 * @param udev pointer to the Device Data Structure 745 * Return: Returns 0 on succes else return error code on failure 746 */ 747static int _xhci_alloc_device(struct usb_device *udev) 748{ 749 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 750 union xhci_trb *event; 751 int ret; 752 753 /* 754 * Root hub will be first device to be initailized. 755 * If this device is root-hub, don't do any xHC related 756 * stuff. 757 */ 758 if (ctrl->rootdev == 0) { 759 udev->speed = USB_SPEED_SUPER; 760 return 0; 761 } 762 763 xhci_queue_command(ctrl, 0, 0, 0, TRB_ENABLE_SLOT); 764 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); 765 if (!event) 766 return -ETIMEDOUT; 767 768 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)) 769 != COMP_SUCCESS); 770 771 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)); 772 773 xhci_acknowledge_event(ctrl); 774 775 ret = xhci_alloc_virt_device(ctrl, udev->slot_id); 776 if (ret < 0) { 777 /* 778 * TODO: Unsuccessful Address Device command shall leave 779 * the slot in default. So, issue Disable Slot command now. 780 */ 781 puts("Could not allocate xHCI USB device data structures\n"); 782 return ret; 783 } 784 785 return 0; 786} 787 788/* 789 * Full speed devices may have a max packet size greater than 8 bytes, but the 790 * USB core doesn't know that until it reads the first 8 bytes of the 791 * descriptor. If the usb_device's max packet size changes after that point, 792 * we need to issue an evaluate context command and wait on it. 793 * 794 * @param udev pointer to the Device Data Structure 795 * Return: returns the status of the xhci_configure_endpoints 796 */ 797int xhci_check_maxpacket(struct usb_device *udev) 798{ 799 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 800 unsigned int slot_id = udev->slot_id; 801 int ep_index = 0; /* control endpoint */ 802 struct xhci_container_ctx *in_ctx; 803 struct xhci_container_ctx *out_ctx; 804 struct xhci_input_control_ctx *ctrl_ctx; 805 struct xhci_ep_ctx *ep_ctx; 806 int max_packet_size; 807 int hw_max_packet_size; 808 int ret = 0; 809 810 out_ctx = ctrl->devs[slot_id]->out_ctx; 811 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); 812 813 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index); 814 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); 815 max_packet_size = udev->epmaxpacketin[0]; 816 if (hw_max_packet_size != max_packet_size) { 817 debug("Max Packet Size for ep 0 changed.\n"); 818 debug("Max packet size in usb_device = %d\n", max_packet_size); 819 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size); 820 debug("Issuing evaluate context command.\n"); 821 822 /* Set up the modified control endpoint 0 */ 823 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx, 824 ctrl->devs[slot_id]->out_ctx, ep_index); 825 in_ctx = ctrl->devs[slot_id]->in_ctx; 826 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); 827 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK)); 828 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); 829 830 /* 831 * Set up the input context flags for the command 832 * FIXME: This won't work if a non-default control endpoint 833 * changes max packet sizes. 834 */ 835 ctrl_ctx = xhci_get_input_control_ctx(in_ctx); 836 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); 837 ctrl_ctx->drop_flags = 0; 838 839 ret = xhci_configure_endpoints(udev, true); 840 } 841 return ret; 842} 843 844/** 845 * Clears the Change bits of the Port Status Register 846 * 847 * @param wValue request value 848 * @param wIndex request index 849 * @param addr address of posrt status register 850 * @param port_status state of port status register 851 * Return: none 852 */ 853static void xhci_clear_port_change_bit(u16 wValue, 854 u16 wIndex, volatile uint32_t *addr, u32 port_status) 855{ 856 char *port_change_bit; 857 u32 status; 858 859 switch (wValue) { 860 case USB_PORT_FEAT_C_RESET: 861 status = PORT_RC; 862 port_change_bit = "reset"; 863 break; 864 case USB_PORT_FEAT_C_CONNECTION: 865 status = PORT_CSC; 866 port_change_bit = "connect"; 867 break; 868 case USB_PORT_FEAT_C_OVER_CURRENT: 869 status = PORT_OCC; 870 port_change_bit = "over-current"; 871 break; 872 case USB_PORT_FEAT_C_ENABLE: 873 status = PORT_PEC; 874 port_change_bit = "enable/disable"; 875 break; 876 case USB_PORT_FEAT_C_SUSPEND: 877 status = PORT_PLC; 878 port_change_bit = "suspend/resume"; 879 break; 880 default: 881 /* Should never happen */ 882 return; 883 } 884 885 /* Change bits are all write 1 to clear */ 886 xhci_writel(addr, port_status | status); 887 888 port_status = xhci_readl(addr); 889 debug("clear port %s change, actual port %d status = 0x%x\n", 890 port_change_bit, wIndex, port_status); 891} 892 893/** 894 * Save Read Only (RO) bits and save read/write bits where 895 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 896 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 897 * 898 * @param state state of the Port Status and Control Regsiter 899 * Return: a value that would result in the port being in the 900 * same state, if the value was written to the port 901 * status control register. 902 */ 903static u32 xhci_port_state_to_neutral(u32 state) 904{ 905 /* Save read-only status and port state */ 906 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 907} 908 909/** 910 * Submits the Requests to the XHCI Host Controller 911 * 912 * @param udev pointer to the USB device structure 913 * @param pipe contains the DIR_IN or OUT , devnum 914 * @param buffer buffer to be read/written based on the request 915 * Return: returns 0 if successful else -1 on failure 916 */ 917static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, 918 void *buffer, struct devrequest *req) 919{ 920 uint8_t tmpbuf[4]; 921 u16 typeReq; 922 void *srcptr = NULL; 923 int len, srclen; 924 uint32_t reg; 925 volatile uint32_t *status_reg; 926 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 927 struct xhci_hccr *hccr = ctrl->hccr; 928 struct xhci_hcor *hcor = ctrl->hcor; 929 int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1)); 930 931 if ((req->requesttype & USB_RT_PORT) && 932 le16_to_cpu(req->index) > max_ports) { 933 printf("The request port(%d) exceeds maximum port number\n", 934 le16_to_cpu(req->index) - 1); 935 return -EINVAL; 936 } 937 938 status_reg = (volatile uint32_t *) 939 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc); 940 srclen = 0; 941 942 typeReq = req->request | req->requesttype << 8; 943 944 switch (typeReq) { 945 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 946 switch (le16_to_cpu(req->value) >> 8) { 947 case USB_DT_DEVICE: 948 debug("USB_DT_DEVICE request\n"); 949 srcptr = &descriptor.device; 950 srclen = 0x12; 951 break; 952 case USB_DT_CONFIG: 953 debug("USB_DT_CONFIG config\n"); 954 srcptr = &descriptor.config; 955 srclen = 0x19; 956 break; 957 case USB_DT_STRING: 958 debug("USB_DT_STRING config\n"); 959 switch (le16_to_cpu(req->value) & 0xff) { 960 case 0: /* Language */ 961 srcptr = "\4\3\11\4"; 962 srclen = 4; 963 break; 964 case 1: /* Vendor String */ 965 srcptr = "\16\3U\0-\0B\0o\0o\0t\0"; 966 srclen = 14; 967 break; 968 case 2: /* Product Name */ 969 srcptr = "\52\3X\0H\0C\0I\0 " 970 "\0H\0o\0s\0t\0 " 971 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 972 srclen = 42; 973 break; 974 default: 975 printf("unknown value DT_STRING %x\n", 976 le16_to_cpu(req->value)); 977 goto unknown; 978 } 979 break; 980 default: 981 printf("unknown value %x\n", le16_to_cpu(req->value)); 982 goto unknown; 983 } 984 break; 985 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 986 switch (le16_to_cpu(req->value) >> 8) { 987 case USB_DT_HUB: 988 case USB_DT_SS_HUB: 989 debug("USB_DT_HUB config\n"); 990 srcptr = &ctrl->hub_desc; 991 srclen = 0x8; 992 break; 993 default: 994 printf("unknown value %x\n", le16_to_cpu(req->value)); 995 goto unknown; 996 } 997 break; 998 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 999 debug("USB_REQ_SET_ADDRESS\n"); 1000 ctrl->rootdev = le16_to_cpu(req->value); 1001 break; 1002 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 1003 /* Do nothing */ 1004 break; 1005 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 1006 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 1007 tmpbuf[1] = 0; 1008 srcptr = tmpbuf; 1009 srclen = 2; 1010 break; 1011 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 1012 memset(tmpbuf, 0, 4); 1013 reg = xhci_readl(status_reg); 1014 if (reg & PORT_CONNECT) { 1015 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 1016 switch (reg & DEV_SPEED_MASK) { 1017 case XDEV_FS: 1018 debug("SPEED = FULLSPEED\n"); 1019 break; 1020 case XDEV_LS: 1021 debug("SPEED = LOWSPEED\n"); 1022 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 1023 break; 1024 case XDEV_HS: 1025 debug("SPEED = HIGHSPEED\n"); 1026 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 1027 break; 1028 case XDEV_SS: 1029 debug("SPEED = SUPERSPEED\n"); 1030 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8; 1031 break; 1032 } 1033 } 1034 if (reg & PORT_PE) 1035 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 1036 if ((reg & PORT_PLS_MASK) == XDEV_U3) 1037 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 1038 if (reg & PORT_OC) 1039 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 1040 if (reg & PORT_RESET) 1041 tmpbuf[0] |= USB_PORT_STAT_RESET; 1042 if (reg & PORT_POWER) 1043 /* 1044 * XXX: This Port power bit (for USB 3.0 hub) 1045 * we are faking in USB 2.0 hub port status; 1046 * since there's a change in bit positions in 1047 * two: 1048 * USB 2.0 port status PP is at position[8] 1049 * USB 3.0 port status PP is at position[9] 1050 * So, we are still keeping it at position [8] 1051 */ 1052 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 1053 if (reg & PORT_CSC) 1054 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 1055 if (reg & PORT_PEC) 1056 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 1057 if (reg & PORT_OCC) 1058 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 1059 if (reg & PORT_RC) 1060 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 1061 1062 srcptr = tmpbuf; 1063 srclen = 4; 1064 break; 1065 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 1066 reg = xhci_readl(status_reg); 1067 reg = xhci_port_state_to_neutral(reg); 1068 switch (le16_to_cpu(req->value)) { 1069 case USB_PORT_FEAT_ENABLE: 1070 reg |= PORT_PE; 1071 xhci_writel(status_reg, reg); 1072 break; 1073 case USB_PORT_FEAT_POWER: 1074 reg |= PORT_POWER; 1075 xhci_writel(status_reg, reg); 1076 break; 1077 case USB_PORT_FEAT_RESET: 1078 reg |= PORT_RESET; 1079 xhci_writel(status_reg, reg); 1080 break; 1081 default: 1082 printf("unknown feature %x\n", le16_to_cpu(req->value)); 1083 goto unknown; 1084 } 1085 break; 1086 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 1087 reg = xhci_readl(status_reg); 1088 reg = xhci_port_state_to_neutral(reg); 1089 switch (le16_to_cpu(req->value)) { 1090 case USB_PORT_FEAT_ENABLE: 1091 reg &= ~PORT_PE; 1092 break; 1093 case USB_PORT_FEAT_POWER: 1094 reg &= ~PORT_POWER; 1095 break; 1096 case USB_PORT_FEAT_C_RESET: 1097 case USB_PORT_FEAT_C_CONNECTION: 1098 case USB_PORT_FEAT_C_OVER_CURRENT: 1099 case USB_PORT_FEAT_C_ENABLE: 1100 xhci_clear_port_change_bit((le16_to_cpu(req->value)), 1101 le16_to_cpu(req->index), 1102 status_reg, reg); 1103 break; 1104 default: 1105 printf("unknown feature %x\n", le16_to_cpu(req->value)); 1106 goto unknown; 1107 } 1108 xhci_writel(status_reg, reg); 1109 break; 1110 default: 1111 puts("Unknown request\n"); 1112 goto unknown; 1113 } 1114 1115 debug("scrlen = %d\n req->length = %d\n", 1116 srclen, le16_to_cpu(req->length)); 1117 1118 len = min(srclen, (int)le16_to_cpu(req->length)); 1119 1120 if (srcptr != NULL && len > 0) 1121 memcpy(buffer, srcptr, len); 1122 else 1123 debug("Len is 0\n"); 1124 1125 udev->act_len = len; 1126 udev->status = 0; 1127 1128 return 0; 1129 1130unknown: 1131 udev->act_len = 0; 1132 udev->status = USB_ST_STALLED; 1133 1134 return -ENODEV; 1135} 1136 1137/** 1138 * Submits the INT request to XHCI Host cotroller 1139 * 1140 * @param udev pointer to the USB device 1141 * @param pipe contains the DIR_IN or OUT , devnum 1142 * @param buffer buffer to be read/written based on the request 1143 * @param length length of the buffer 1144 * @param interval interval of the interrupt 1145 * Return: 0 1146 */ 1147static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe, 1148 void *buffer, int length, int interval, 1149 bool nonblock) 1150{ 1151 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1152 printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1153 return -EINVAL; 1154 } 1155 1156 /* 1157 * xHCI uses normal TRBs for both bulk and interrupt. When the 1158 * interrupt endpoint is to be serviced, the xHC will consume 1159 * (at most) one TD. A TD (comprised of sg list entries) can 1160 * take several service intervals to transmit. 1161 */ 1162 return xhci_bulk_tx(udev, pipe, length, buffer); 1163} 1164 1165/** 1166 * submit the BULK type of request to the USB Device 1167 * 1168 * @param udev pointer to the USB device 1169 * @param pipe contains the DIR_IN or OUT , devnum 1170 * @param buffer buffer to be read/written based on the request 1171 * @param length length of the buffer 1172 * Return: returns 0 if successful else -1 on failure 1173 */ 1174static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe, 1175 void *buffer, int length) 1176{ 1177 if (usb_pipetype(pipe) != PIPE_BULK) { 1178 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 1179 return -EINVAL; 1180 } 1181 1182 return xhci_bulk_tx(udev, pipe, length, buffer); 1183} 1184 1185/** 1186 * submit the control type of request to the Root hub/Device based on the devnum 1187 * 1188 * @param udev pointer to the USB device 1189 * @param pipe contains the DIR_IN or OUT , devnum 1190 * @param buffer buffer to be read/written based on the request 1191 * @param length length of the buffer 1192 * @param setup Request type 1193 * @param root_portnr Root port number that this device is on 1194 * Return: returns 0 if successful else -1 on failure 1195 */ 1196static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe, 1197 void *buffer, int length, 1198 struct devrequest *setup, int root_portnr) 1199{ 1200 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 1201 int ret = 0; 1202 1203 if (usb_pipetype(pipe) != PIPE_CONTROL) { 1204 printf("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1205 return -EINVAL; 1206 } 1207 1208 if (usb_pipedevice(pipe) == ctrl->rootdev) 1209 return xhci_submit_root(udev, pipe, buffer, setup); 1210 1211 if (setup->request == USB_REQ_SET_ADDRESS && 1212 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) 1213 return xhci_address_device(udev, root_portnr); 1214 1215 if (setup->request == USB_REQ_SET_CONFIGURATION && 1216 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1217 ret = xhci_set_configuration(udev); 1218 if (ret) { 1219 puts("Failed to configure xHCI endpoint\n"); 1220 return ret; 1221 } 1222 } 1223 1224 return xhci_ctrl_tx(udev, pipe, setup, length, buffer); 1225} 1226 1227static int xhci_lowlevel_init(struct xhci_ctrl *ctrl) 1228{ 1229 struct xhci_hccr *hccr; 1230 struct xhci_hcor *hcor; 1231 uint32_t val; 1232 uint32_t val2; 1233 uint32_t reg; 1234 1235 hccr = ctrl->hccr; 1236 hcor = ctrl->hcor; 1237 /* 1238 * Program the Number of Device Slots Enabled field in the CONFIG 1239 * register with the max value of slots the HC can handle. 1240 */ 1241 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK); 1242 val2 = xhci_readl(&hcor->or_config); 1243 val |= (val2 & ~HCS_SLOTS_MASK); 1244 xhci_writel(&hcor->or_config, val); 1245 1246 /* initializing xhci data structures */ 1247 if (xhci_mem_init(ctrl, hccr, hcor) < 0) 1248 return -ENOMEM; 1249 ctrl->hub_desc = descriptor.hub; 1250 1251 reg = xhci_readl(&hccr->cr_hcsparams1); 1252 ctrl->hub_desc.bNbrPorts = HCS_MAX_PORTS(reg); 1253 printf("Register %x NbrPorts %d\n", reg, ctrl->hub_desc.bNbrPorts); 1254 1255 /* Port Indicators */ 1256 reg = xhci_readl(&hccr->cr_hccparams); 1257 if (HCS_INDICATOR(reg)) 1258 put_unaligned(get_unaligned(&ctrl->hub_desc.wHubCharacteristics) 1259 | 0x80, &ctrl->hub_desc.wHubCharacteristics); 1260 1261 /* Port Power Control */ 1262 if (HCC_PPC(reg)) 1263 put_unaligned(get_unaligned(&ctrl->hub_desc.wHubCharacteristics) 1264 | 0x01, &ctrl->hub_desc.wHubCharacteristics); 1265 1266 if (xhci_start(hcor)) { 1267 xhci_reset(hcor); 1268 return -ENODEV; 1269 } 1270 1271 /* Zero'ing IRQ control register and IRQ pending register */ 1272 xhci_writel(&ctrl->ir_set->irq_control, 0x0); 1273 xhci_writel(&ctrl->ir_set->irq_pending, 0x0); 1274 1275 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); 1276 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); 1277 ctrl->hci_version = reg; 1278 1279 return 0; 1280} 1281 1282static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) 1283{ 1284 u32 temp; 1285 1286 xhci_reset(ctrl->hcor); 1287 1288 debug("// Disabling event ring interrupts\n"); 1289 temp = xhci_readl(&ctrl->hcor->or_usbsts); 1290 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT); 1291 temp = xhci_readl(&ctrl->ir_set->irq_pending); 1292 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp)); 1293 1294 return 0; 1295} 1296 1297static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1298 unsigned long pipe, void *buffer, int length, 1299 struct devrequest *setup) 1300{ 1301 struct usb_device *uhop; 1302 struct udevice *hub; 1303 int root_portnr = 0; 1304 1305 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1306 dev->name, udev, udev->dev->name, udev->portnr); 1307 hub = udev->dev; 1308 if (device_get_uclass_id(hub) == UCLASS_USB_HUB) { 1309 /* Figure out our port number on the root hub */ 1310 if (usb_hub_is_root_hub(hub)) { 1311 root_portnr = udev->portnr; 1312 } else { 1313 while (!usb_hub_is_root_hub(hub->parent)) 1314 hub = hub->parent; 1315 uhop = dev_get_parent_priv(hub); 1316 root_portnr = uhop->portnr; 1317 } 1318 } 1319/* 1320 struct usb_device *hop = udev; 1321 1322 if (hop->parent) 1323 while (hop->parent->parent) 1324 hop = hop->parent; 1325*/ 1326 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, 1327 root_portnr); 1328} 1329 1330static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1331 unsigned long pipe, void *buffer, int length) 1332{ 1333 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1334 return _xhci_submit_bulk_msg(udev, pipe, buffer, length); 1335} 1336 1337static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1338 unsigned long pipe, void *buffer, int length, 1339 int interval, bool nonblock) 1340{ 1341 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1342 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval, 1343 nonblock); 1344} 1345 1346static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev) 1347{ 1348 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1349 return _xhci_alloc_device(udev); 1350} 1351 1352static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev) 1353{ 1354 struct xhci_ctrl *ctrl = dev_get_priv(dev); 1355 struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev); 1356 struct xhci_virt_device *virt_dev; 1357 struct xhci_input_control_ctx *ctrl_ctx; 1358 struct xhci_container_ctx *out_ctx; 1359 struct xhci_container_ctx *in_ctx; 1360 struct xhci_slot_ctx *slot_ctx; 1361 int slot_id = udev->slot_id; 1362 unsigned think_time; 1363 1364 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1365 1366 /* Ignore root hubs */ 1367 if (usb_hub_is_root_hub(udev->dev)) 1368 return 0; 1369 1370 virt_dev = ctrl->devs[slot_id]; 1371 BUG_ON(!virt_dev); 1372 1373 out_ctx = virt_dev->out_ctx; 1374 in_ctx = virt_dev->in_ctx; 1375 1376 ctrl_ctx = xhci_get_input_control_ctx(in_ctx); 1377 /* Initialize the input context control */ 1378 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); 1379 ctrl_ctx->drop_flags = 0; 1380 1381 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); 1382 1383 /* slot context */ 1384 xhci_slot_copy(ctrl, in_ctx, out_ctx); 1385 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); 1386 1387 /* Update hub related fields */ 1388 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); 1389 /* 1390 * refer to section 6.2.2: MTT should be 0 for full speed hub, 1391 * but it may be already set to 1 when setup an xHCI virtual 1392 * device, so clear it anyway. 1393 */ 1394 if (hub->tt.multi) 1395 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); 1396 else if (udev->speed == USB_SPEED_FULL) 1397 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT); 1398 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild)); 1399 /* 1400 * Set TT think time - convert from ns to FS bit times. 1401 * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns 1402 * 1403 * 0 = 8 FS bit times, 1 = 16 FS bit times, 1404 * 2 = 24 FS bit times, 3 = 32 FS bit times. 1405 * 1406 * This field shall be 0 if the device is not a high-spped hub. 1407 */ 1408 think_time = hub->tt.think_time; 1409 if (think_time != 0) 1410 think_time = (think_time / 666) - 1; 1411 if (udev->speed == USB_SPEED_HIGH) 1412 slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time)); 1413 slot_ctx->dev_state = 0; 1414 1415 return xhci_configure_endpoints(udev, false); 1416} 1417 1418static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size) 1419{ 1420 /* 1421 * xHCD allocates one segment which includes 64 TRBs for each endpoint 1422 * and the last TRB in this segment is configured as a link TRB to form 1423 * a TRB ring. Each TRB can transfer up to 64K bytes, however data 1424 * buffers referenced by transfer TRBs shall not span 64KB boundaries. 1425 * Hence the maximum number of TRBs we can use in one transfer is 62. 1426 */ 1427 *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE; 1428 1429 return 0; 1430} 1431 1432int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, 1433 struct xhci_hcor *hcor) 1434{ 1435 struct xhci_ctrl *ctrl = dev_get_priv(dev); 1436 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 1437 int ret; 1438 1439 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name, 1440 ctrl, hccr, hcor); 1441 1442 ctrl->dev = dev; 1443 1444 /* 1445 * XHCI needs to issue a Address device command to setup 1446 * proper device context structures, before it can interact 1447 * with the device. So a get_descriptor will fail before any 1448 * of that is done for XHCI unlike EHCI. 1449 */ 1450 priv->desc_before_addr = false; 1451 1452 ret = xhci_reset(hcor); 1453 if (ret) 1454 goto err; 1455 1456 ctrl->hccr = hccr; 1457 ctrl->hcor = hcor; 1458 ret = xhci_lowlevel_init(ctrl); 1459 if (ret) 1460 goto err; 1461 1462 return 0; 1463err: 1464 debug("%s: failed, ret=%d\n", __func__, ret); 1465 return ret; 1466} 1467 1468int xhci_deregister(struct udevice *dev) 1469{ 1470 struct xhci_ctrl *ctrl = dev_get_priv(dev); 1471 1472 xhci_lowlevel_stop(ctrl); 1473 xhci_cleanup(ctrl); 1474 1475 return 0; 1476} 1477 1478struct dm_usb_ops xhci_usb_ops = { 1479 .control = xhci_submit_control_msg, 1480 .bulk = xhci_submit_bulk_msg, 1481 .interrupt = xhci_submit_int_msg, 1482 .alloc_device = xhci_alloc_device, 1483 .update_hub_device = xhci_update_hub_device, 1484 .get_max_xfer_size = xhci_get_max_xfer_size, 1485}; 1486