1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * Copyright (c) 2009-2015 NVIDIA Corporation 5 * Copyright (c) 2013 Lucas Stach 6 */ 7 8#include <common.h> 9#include <dm.h> 10#include <log.h> 11#include <linux/delay.h> 12#include <linux/errno.h> 13#include <asm/io.h> 14#include <asm-generic/gpio.h> 15#include <asm/arch/clock.h> 16#include <asm/arch-tegra/usb.h> 17#include <asm/arch-tegra/clk_rst.h> 18#include <usb.h> 19#include <usb/ulpi.h> 20#include <linux/libfdt.h> 21 22#include "ehci.h" 23 24#define USB1_ADDR_MASK 0xFFFF0000 25 26#define HOSTPC1_DEVLC 0x84 27#define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 28 29#ifdef CONFIG_USB_ULPI 30 #ifndef CONFIG_USB_ULPI_VIEWPORT 31 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 32 define CONFIG_USB_ULPI_VIEWPORT" 33 #endif 34#endif 35 36/* Parameters we need for USB */ 37enum { 38 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 39 PARAM_DIVM, /* PLL INPUT DIVIDER */ 40 PARAM_DIVP, /* POST DIVIDER (2^N) */ 41 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 42 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 43 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 44 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 45 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 46 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 47 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 48 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 49 50 PARAM_COUNT 51}; 52 53/* Possible port types (dual role mode) */ 54enum dr_mode { 55 DR_MODE_NONE = 0, 56 DR_MODE_HOST, /* supports host operation */ 57 DR_MODE_DEVICE, /* supports device operation */ 58 DR_MODE_OTG, /* supports both */ 59}; 60 61enum usb_ctlr_type { 62 USB_CTLR_T20, 63 USB_CTLR_T30, 64 USB_CTLR_T114, 65 USB_CTLR_T210, 66 67 USB_CTRL_COUNT, 68}; 69 70/* Information about a USB port */ 71struct fdt_usb { 72 struct ehci_ctrl ehci; 73 struct usb_ctlr *reg; /* address of registers in physical memory */ 74 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 75 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 76 unsigned enabled:1; /* 1 to enable, 0 to disable */ 77 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 78 enum usb_ctlr_type type; 79 enum usb_init_type init_type; 80 enum dr_mode dr_mode; /* dual role mode */ 81 enum periph_id periph_id;/* peripheral id */ 82 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 83 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 84}; 85 86/* 87 * This table has USB timing parameters for each Oscillator frequency we 88 * support. There are four sets of values: 89 * 90 * 1. PLLU configuration information (reference clock is osc/clk_m and 91 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 92 * 93 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 94 * ---------------------------------------------------------------------- 95 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 96 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 97 * Filter frequency (MHz) 1 4.8 6 2 98 * CPCON 1100b 0011b 1100b 1100b 99 * LFCON0 0 0 0 0 100 * 101 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 102 * 103 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 104 * --------------------------------------------------------------------------- 105 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 106 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 107 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 108 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 109 * 110 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 111 * SessEnd. Each of these signals have their own debouncer and for each of 112 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 113 * BIAS_DEBOUNCE_B). 114 * 115 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 116 * 0xffff -> No debouncing at all 117 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 118 * 119 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 120 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 121 * 122 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 123 * values, so we can keep those to default. 124 * 125 * 4. The 20 microsecond delay after bias cell operation. 126 */ 127static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 128 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 129 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 130 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 131 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 132 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 133 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 134 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 135 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 136 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 137 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 138 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 139 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 140 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 141 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 142}; 143 144static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 145 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 146 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 147 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 148 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 149 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 150 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 151 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 152 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 153 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 154 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 155 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 156 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 157 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 158 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 159}; 160 161static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 162 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 163 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 164 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 165 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 166 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 167 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 168 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 169 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 170 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 171 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 172 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 173 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 174 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 175 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 } 176}; 177 178/* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ 179static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 180 /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ 181 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, 182 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, 183 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, 184 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, 185 { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, 186 { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, 187 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, 188 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, 189 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, 190 { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 }, 191 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, 192 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, 193 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 } 194}; 195 196/* UTMIP Idle Wait Delay */ 197static const u8 utmip_idle_wait_delay = 17; 198 199/* UTMIP Elastic limit */ 200static const u8 utmip_elastic_limit = 16; 201 202/* UTMIP High Speed Sync Start Delay */ 203static const u8 utmip_hs_sync_start_delay = 9; 204 205struct fdt_usb_controller { 206 /* flag to determine whether controller supports hostpc register */ 207 u32 has_hostpc:1; 208 const unsigned *pll_parameter; 209}; 210 211static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 212 { 213 .has_hostpc = 0, 214 .pll_parameter = (const unsigned *)T20_usb_pll, 215 }, 216 { 217 .has_hostpc = 1, 218 .pll_parameter = (const unsigned *)T30_usb_pll, 219 }, 220 { 221 .has_hostpc = 1, 222 .pll_parameter = (const unsigned *)T114_usb_pll, 223 }, 224 { 225 .has_hostpc = 1, 226 .pll_parameter = (const unsigned *)T210_usb_pll, 227 }, 228}; 229 230/* 231 * A known hardware issue where Connect Status Change bit of PORTSC register 232 * of USB1 controller will be set after Port Reset. 233 * We have to clear it in order for later device enumeration to proceed. 234 */ 235static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 236 uint32_t *status_reg, uint32_t *reg) 237{ 238 struct fdt_usb *config = ctrl->priv; 239 struct fdt_usb_controller *controller; 240 241 controller = &fdt_usb_controllers[config->type]; 242 mdelay(50); 243 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 244 if (controller->has_hostpc) 245 *reg |= EHCI_PS_PE; 246 247 if (!config->has_legacy_mode) 248 return; 249 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 250 if (ehci_readl(status_reg) & EHCI_PS_CSC) 251 *reg |= EHCI_PS_CSC; 252} 253 254static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 255{ 256 struct fdt_usb *config = ctrl->priv; 257 struct usb_ctlr *usbctlr; 258 uint32_t tmp; 259 260 usbctlr = config->reg; 261 262 tmp = ehci_readl(&usbctlr->usb_mode); 263 tmp |= USBMODE_CM_HC; 264 ehci_writel(&usbctlr->usb_mode, tmp); 265} 266 267static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 268{ 269 struct fdt_usb *config = ctrl->priv; 270 struct fdt_usb_controller *controller; 271 uint32_t tmp; 272 uint32_t *reg_ptr; 273 274 controller = &fdt_usb_controllers[config->type]; 275 if (controller->has_hostpc) { 276 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 277 HOSTPC1_DEVLC); 278 tmp = ehci_readl(reg_ptr); 279 return HOSTPC1_PSPD(tmp); 280 } else 281 return PORTSC_PSPD(reg); 282} 283 284/* Set up VBUS for host/device mode */ 285static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 286{ 287 /* 288 * If we are an OTG port initializing in host mode, 289 * check if remote host is driving VBus and bail out in this case. 290 */ 291 if (init == USB_INIT_HOST && 292 config->dr_mode == DR_MODE_OTG && 293 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 294 printf("tegrausb: VBUS input active; not enabling as host\n"); 295 return; 296 } 297 298 if (dm_gpio_is_valid(&config->vbus_gpio)) { 299 int vbus_value; 300 301 vbus_value = (init == USB_INIT_HOST); 302 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 303 304 debug("set_up_vbus: GPIO %d %d\n", 305 gpio_get_number(&config->vbus_gpio), vbus_value); 306 } 307} 308 309static void usbf_reset_controller(struct fdt_usb *config, 310 struct usb_ctlr *usbctlr) 311{ 312 /* Reset the USB controller with 2us delay */ 313 reset_periph(config->periph_id, 2); 314 315 /* 316 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 317 * base address 318 */ 319 if (config->has_legacy_mode) 320 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 321 322 /* Put UTMIP1/3 in reset */ 323 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 324 325 /* Enable the UTMIP PHY */ 326 if (config->utmi) 327 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 328} 329 330static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 331{ 332 const unsigned *timing; 333 334 timing = controller->pll_parameter + 335 clock_get_osc_freq() * PARAM_COUNT; 336 337 return timing; 338} 339 340/* select the PHY to use with a USB controller */ 341static void init_phy_mux(struct fdt_usb *config, uint pts, 342 enum usb_init_type init) 343{ 344 struct usb_ctlr *usbctlr = config->reg; 345 346#if defined(CONFIG_TEGRA20) 347 if (config->periph_id == PERIPH_ID_USBD) { 348 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 349 pts << PTS1_SHIFT); 350 clrbits_le32(&usbctlr->port_sc1, STS1); 351 } else { 352 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 353 pts << PTS_SHIFT); 354 clrbits_le32(&usbctlr->port_sc1, STS); 355 } 356#else 357 /* Set to Host mode (if applicable) after Controller Reset was done */ 358 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 359 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 360 /* 361 * Select PHY interface after setting host mode. 362 * For device mode, the ordering requirement is not an issue, since 363 * only the first USB controller supports device mode, and that USB 364 * controller can only talk to a UTMI PHY, so the PHY selection is 365 * already made at reset time, so this write is a no-op. 366 */ 367 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 368 pts << PTS_SHIFT); 369 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 370#endif 371} 372 373/* set up the UTMI USB controller with the parameters provided */ 374static int init_utmi_usb_controller(struct fdt_usb *config, 375 enum usb_init_type init) 376{ 377 struct fdt_usb_controller *controller; 378 u32 b_sess_valid_mask, val; 379 int loop_count; 380 const unsigned *timing; 381 struct usb_ctlr *usbctlr = config->reg; 382 struct clk_rst_ctlr *clkrst; 383 struct usb_ctlr *usb1ctlr; 384 385 clock_enable(config->periph_id); 386 387 /* Reset the usb controller */ 388 usbf_reset_controller(config, usbctlr); 389 390 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 391 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 392 393 /* Follow the crystal clock disable by >100ns delay */ 394 udelay(1); 395 396 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 397 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 398 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 399 400 /* 401 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 402 * mux must be switched to actually use a_sess_vld threshold. 403 */ 404 if (config->dr_mode == DR_MODE_OTG && 405 dm_gpio_is_valid(&config->vbus_gpio)) 406 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 407 VBUS_SENSE_CTL_MASK, 408 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 409 410 controller = &fdt_usb_controllers[config->type]; 411 debug("controller=%p, type=%d\n", controller, config->type); 412 413 /* 414 * PLL Delay CONFIGURATION settings. The following parameters control 415 * the bring up of the plls. 416 */ 417 timing = get_pll_timing(controller); 418 419 if (!controller->has_hostpc) { 420 val = readl(&usbctlr->utmip_misc_cfg1); 421 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 422 timing[PARAM_STABLE_COUNT] << 423 UTMIP_PLLU_STABLE_COUNT_SHIFT); 424 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 425 timing[PARAM_ACTIVE_DELAY_COUNT] << 426 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 427 writel(val, &usbctlr->utmip_misc_cfg1); 428 429 /* Set PLL enable delay count and crystal frequency count */ 430 val = readl(&usbctlr->utmip_pll_cfg1); 431 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 432 timing[PARAM_ENABLE_DELAY_COUNT] << 433 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 434 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 435 timing[PARAM_XTAL_FREQ_COUNT] << 436 UTMIP_XTAL_FREQ_COUNT_SHIFT); 437 writel(val, &usbctlr->utmip_pll_cfg1); 438 } else { 439 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 440 441 val = readl(&clkrst->crc_utmip_pll_cfg2); 442 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 443 timing[PARAM_STABLE_COUNT] << 444 UTMIP_PLLU_STABLE_COUNT_SHIFT); 445 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 446 timing[PARAM_ACTIVE_DELAY_COUNT] << 447 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 448 writel(val, &clkrst->crc_utmip_pll_cfg2); 449 450 /* Set PLL enable delay count and crystal frequency count */ 451 val = readl(&clkrst->crc_utmip_pll_cfg1); 452 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 453 timing[PARAM_ENABLE_DELAY_COUNT] << 454 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 455 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 456 timing[PARAM_XTAL_FREQ_COUNT] << 457 UTMIP_XTAL_FREQ_COUNT_SHIFT); 458 writel(val, &clkrst->crc_utmip_pll_cfg1); 459 460 /* Disable Power Down state for PLL */ 461 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 462 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 463 PLL_ACTIVE_POWERDOWN); 464 465 /* Recommended PHY settings for EYE diagram */ 466 val = readl(&usbctlr->utmip_xcvr_cfg0); 467 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 468 0x4 << UTMIP_XCVR_SETUP_SHIFT); 469 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 470 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 471 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 472 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 473 writel(val, &usbctlr->utmip_xcvr_cfg0); 474 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 475 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 476 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 477 478 /* Some registers can be controlled from USB1 only. */ 479 if (config->periph_id != PERIPH_ID_USBD) { 480 clock_enable(PERIPH_ID_USBD); 481 /* Disable Reset if in Reset state */ 482 reset_set_enable(PERIPH_ID_USBD, 0); 483 } 484 usb1ctlr = (struct usb_ctlr *) 485 ((unsigned long)config->reg & USB1_ADDR_MASK); 486 val = readl(&usb1ctlr->utmip_bias_cfg0); 487 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 488 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 489 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 490 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 491 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 492 writel(val, &usb1ctlr->utmip_bias_cfg0); 493 494 /* Miscellaneous setting mentioned in Programming Guide */ 495 clrbits_le32(&usbctlr->utmip_misc_cfg0, 496 UTMIP_SUSPEND_EXIT_ON_EDGE); 497 } 498 499 /* Setting the tracking length time */ 500 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 501 UTMIP_BIAS_PDTRK_COUNT_MASK, 502 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 503 504 /* Program debounce time for VBUS to become valid */ 505 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 506 UTMIP_DEBOUNCE_CFG0_MASK, 507 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 508 509 if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) { 510 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 511 UTMIP_DEBOUNCE_CFG0_MASK, 512 (timing[PARAM_DEBOUNCE_A_TIME] >> 1) 513 << UTMIP_DEBOUNCE_CFG0_SHIFT); 514 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 515 UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK, 516 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT); 517 } 518 519 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 520 521 /* Disable battery charge enabling bit */ 522 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 523 524 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 525 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 526 527 /* 528 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 529 * Setting these fields, together with default values of the 530 * other fields, results in programming the registers below as 531 * follows: 532 * UTMIP_HSRX_CFG0 = 0x9168c000 533 * UTMIP_HSRX_CFG1 = 0x13 534 */ 535 536 /* Set PLL enable delay count and Crystal frequency count */ 537 val = readl(&usbctlr->utmip_hsrx_cfg0); 538 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 539 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 540 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 541 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 542 writel(val, &usbctlr->utmip_hsrx_cfg0); 543 544 /* Configure the UTMIP_HS_SYNC_START_DLY */ 545 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 546 UTMIP_HS_SYNC_START_DLY_MASK, 547 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 548 549 /* Preceed the crystal clock disable by >100ns delay. */ 550 udelay(1); 551 552 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 553 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 554 555 if (controller->has_hostpc) { 556 if (config->periph_id == PERIPH_ID_USBD) 557 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 558 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 559 if (config->periph_id == PERIPH_ID_USB2) 560 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 561 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 562 if (config->periph_id == PERIPH_ID_USB3) 563 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 564 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 565 } 566 /* Finished the per-controller init. */ 567 568 /* De-assert UTMIP_RESET to bring out of reset. */ 569 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 570 571 /* Wait for the phy clock to become valid in 100 ms */ 572 for (loop_count = 100000; loop_count != 0; loop_count--) { 573 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 574 break; 575 udelay(1); 576 } 577 if (!loop_count) 578 return -ETIMEDOUT; 579 580 /* Disable ICUSB FS/LS transceiver */ 581 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 582 583 /* Select UTMI parallel interface */ 584 init_phy_mux(config, PTS_UTMI, init); 585 586 /* Deassert power down state */ 587 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 588 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 589 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 590 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 591 592 if (controller->has_hostpc) { 593 /* 594 * BIAS Pad Power Down is common among all 3 USB 595 * controllers and can be controlled from USB1 only. 596 */ 597 usb1ctlr = (struct usb_ctlr *) 598 ((unsigned long)config->reg & USB1_ADDR_MASK); 599 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 600 udelay(25); 601 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 602 UTMIP_FORCE_PDTRK_POWERDOWN); 603 } 604 return 0; 605} 606 607#ifdef CONFIG_USB_ULPI 608/* if board file does not set a ULPI reference frequency we default to 24MHz */ 609#ifndef CFG_ULPI_REF_CLK 610#define CFG_ULPI_REF_CLK 24000000 611#endif 612 613/* set up the ULPI USB controller with the parameters provided */ 614static int init_ulpi_usb_controller(struct fdt_usb *config, 615 enum usb_init_type init) 616{ 617 u32 val; 618 int loop_count; 619 struct ulpi_viewport ulpi_vp; 620 struct usb_ctlr *usbctlr = config->reg; 621 int ret; 622 623 /* set up ULPI reference clock on pllp_out4 */ 624 clock_enable(PERIPH_ID_DEV2_OUT); 625 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CFG_ULPI_REF_CLK); 626 627 /* reset ULPI phy */ 628 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 629 /* 630 * This GPIO is typically active-low, and marked as such in 631 * device tree. dm_gpio_set_value() takes this into account 632 * and inverts the value we pass here if required. In other 633 * words, this first call logically asserts the reset signal, 634 * which typically results in driving the physical GPIO low, 635 * and the second call logically de-asserts the reset signal, 636 * which typically results in driver the GPIO high. 637 */ 638 dm_gpio_set_value(&config->phy_reset_gpio, 1); 639 mdelay(5); 640 dm_gpio_set_value(&config->phy_reset_gpio, 0); 641 } 642 643 /* Reset the usb controller */ 644 clock_enable(config->periph_id); 645 usbf_reset_controller(config, usbctlr); 646 647 /* enable pinmux bypass */ 648 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 649 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 650 651 /* Select ULPI parallel interface */ 652 init_phy_mux(config, PTS_ULPI, init); 653 654 /* enable ULPI transceiver */ 655 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 656 657 /* configure ULPI transceiver timings */ 658 val = 0; 659 writel(val, &usbctlr->ulpi_timing_ctrl_1); 660 661 val |= ULPI_DATA_TRIMMER_SEL(4); 662 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 663 val |= ULPI_DIR_TRIMMER_SEL(4); 664 writel(val, &usbctlr->ulpi_timing_ctrl_1); 665 udelay(10); 666 667 val |= ULPI_DATA_TRIMMER_LOAD; 668 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 669 val |= ULPI_DIR_TRIMMER_LOAD; 670 writel(val, &usbctlr->ulpi_timing_ctrl_1); 671 672 /* set up phy for host operation with external vbus supply */ 673 ulpi_vp.port_num = 0; 674 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 675 676 ret = ulpi_init(&ulpi_vp); 677 if (ret) { 678 printf("Tegra ULPI viewport init failed\n"); 679 return ret; 680 } 681 682 ulpi_set_vbus(&ulpi_vp, 1, 1); 683 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 684 685 /* enable wakeup events */ 686 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 687 688 /* Enable and wait for the phy clock to become valid in 100 ms */ 689 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 690 for (loop_count = 100000; loop_count != 0; loop_count--) { 691 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 692 break; 693 udelay(1); 694 } 695 if (!loop_count) 696 return -ETIMEDOUT; 697 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 698 699 return 0; 700} 701#else 702static int init_ulpi_usb_controller(struct fdt_usb *config, 703 enum usb_init_type init) 704{ 705 printf("No code to set up ULPI controller, please enable" 706 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 707 return -ENOSYS; 708} 709#endif 710 711static void config_clock(const u32 timing[]) 712{ 713 debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n", 714 __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], 715 timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); 716 717 clock_start_pll(CLOCK_ID_USB, 718 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 719 timing[PARAM_CPCON], timing[PARAM_LFCON]); 720} 721 722static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config) 723{ 724 const char *phy, *mode; 725 726 config->reg = dev_read_addr_ptr(dev); 727 debug("reg=%p\n", config->reg); 728 mode = dev_read_string(dev, "dr_mode"); 729 if (mode) { 730 if (0 == strcmp(mode, "host")) 731 config->dr_mode = DR_MODE_HOST; 732 else if (0 == strcmp(mode, "peripheral")) 733 config->dr_mode = DR_MODE_DEVICE; 734 else if (0 == strcmp(mode, "otg")) 735 config->dr_mode = DR_MODE_OTG; 736 else { 737 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 738 mode); 739 return -EINVAL; 740 } 741 } else { 742 config->dr_mode = DR_MODE_HOST; 743 } 744 745 phy = dev_read_string(dev, "phy_type"); 746 config->utmi = phy && 0 == strcmp("utmi", phy); 747 config->ulpi = phy && 0 == strcmp("ulpi", phy); 748 config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode"); 749 config->periph_id = clock_decode_periph_id(dev); 750 if (config->periph_id == PERIPH_ID_NONE) { 751 debug("%s: Missing/invalid peripheral ID\n", __func__); 752 return -EINVAL; 753 } 754 gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio, 755 GPIOD_IS_OUT); 756 gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0, 757 &config->phy_reset_gpio, GPIOD_IS_OUT); 758 debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n", 759 config->has_legacy_mode, config->utmi, config->ulpi, 760 config->periph_id, gpio_get_number(&config->vbus_gpio), 761 gpio_get_number(&config->phy_reset_gpio), config->dr_mode, 762 config->reg); 763 764 return 0; 765} 766 767int usb_common_init(struct fdt_usb *config, enum usb_init_type init) 768{ 769 int ret = 0; 770 771 switch (init) { 772 case USB_INIT_HOST: 773 switch (config->dr_mode) { 774 case DR_MODE_HOST: 775 case DR_MODE_OTG: 776 break; 777 default: 778 printf("tegrausb: Invalid dr_mode %d for host mode\n", 779 config->dr_mode); 780 return -1; 781 } 782 break; 783 case USB_INIT_DEVICE: 784 if (config->periph_id != PERIPH_ID_USBD) { 785 printf("tegrausb: Device mode only supported on first USB controller\n"); 786 return -1; 787 } 788 if (!config->utmi) { 789 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 790 return -1; 791 } 792 switch (config->dr_mode) { 793 case DR_MODE_DEVICE: 794 case DR_MODE_OTG: 795 break; 796 default: 797 printf("tegrausb: Invalid dr_mode %d for device mode\n", 798 config->dr_mode); 799 return -1; 800 } 801 break; 802 default: 803 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 804 return -1; 805 } 806 807 debug("%d, %d\n", config->utmi, config->ulpi); 808 if (config->utmi) 809 ret = init_utmi_usb_controller(config, init); 810 else if (config->ulpi) 811 ret = init_ulpi_usb_controller(config, init); 812 if (ret) 813 return ret; 814 815 set_up_vbus(config, init); 816 817 config->init_type = init; 818 819 return 0; 820} 821 822void usb_common_uninit(struct fdt_usb *priv) 823{ 824 struct usb_ctlr *usbctlr; 825 826 usbctlr = priv->reg; 827 828 /* Stop controller */ 829 writel(0, &usbctlr->usb_cmd); 830 udelay(1000); 831 832 /* Initiate controller reset */ 833 writel(2, &usbctlr->usb_cmd); 834 udelay(1000); 835} 836 837static const struct ehci_ops tegra_ehci_ops = { 838 .set_usb_mode = tegra_ehci_set_usbmode, 839 .get_port_speed = tegra_ehci_get_port_speed, 840 .powerup_fixup = tegra_ehci_powerup_fixup, 841}; 842 843static int ehci_usb_of_to_plat(struct udevice *dev) 844{ 845 struct fdt_usb *priv = dev_get_priv(dev); 846 int ret; 847 848 ret = fdt_decode_usb(dev, priv); 849 if (ret) 850 return ret; 851 852 priv->type = dev_get_driver_data(dev); 853 854 return 0; 855} 856 857static int ehci_usb_probe(struct udevice *dev) 858{ 859 struct usb_plat *plat = dev_get_plat(dev); 860 struct fdt_usb *priv = dev_get_priv(dev); 861 struct ehci_hccr *hccr; 862 struct ehci_hcor *hcor; 863 static bool clk_done; 864 int ret; 865 866 ret = usb_common_init(priv, plat->init_type); 867 if (ret) 868 return ret; 869 hccr = (struct ehci_hccr *)&priv->reg->cap_length; 870 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; 871 if (!clk_done) { 872 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); 873 clk_done = true; 874 } 875 876 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, 877 plat->init_type); 878} 879 880static const struct udevice_id ehci_usb_ids[] = { 881 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, 882 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, 883 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, 884 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 }, 885 { } 886}; 887 888U_BOOT_DRIVER(usb_ehci) = { 889 .name = "ehci_tegra", 890 .id = UCLASS_USB, 891 .of_match = ehci_usb_ids, 892 .of_to_plat = ehci_usb_of_to_plat, 893 .probe = ehci_usb_probe, 894 .remove = ehci_deregister, 895 .ops = &ehci_usb_ops, 896 .plat_auto = sizeof(struct usb_plat), 897 .priv_auto = sizeof(struct fdt_usb), 898 .flags = DM_FLAG_ALLOC_PRIV_DMA, 899}; 900