1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NXP FlexSPI(FSPI) controller driver. 4 * 5 * Copyright (c) 2019 Michael Walle <michael@walle.cc> 6 * Copyright (c) 2019 NXP 7 * 8 * This driver was originally ported from the linux kernel v5.4-rc3, which had 9 * the following notes: 10 * 11 * FlexSPI is a flexsible SPI host controller which supports two SPI 12 * channels and up to 4 external devices. Each channel supports 13 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 14 * data lines). 15 * 16 * FlexSPI controller is driven by the LUT(Look-up Table) registers 17 * LUT registers are a look-up-table for sequences of instructions. 18 * A valid sequence consists of four LUT registers. 19 * Maximum 32 LUT sequences can be programmed simultaneously. 20 * 21 * LUTs are being created at run-time based on the commands passed 22 * from the spi-mem framework, thus using single LUT index. 23 * 24 * Software triggered Flash read/write access by IP Bus. 25 * 26 * Memory mapped read access by AHB Bus. 27 * 28 * Based on SPI MEM interface and spi-fsl-qspi.c driver. 29 * 30 * Author: 31 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 32 * Boris Brezillon <bbrezillon@kernel.org> 33 * Frieder Schrempf <frieder.schrempf@kontron.de> 34 */ 35 36#include <common.h> 37#include <clk.h> 38#include <dm.h> 39#include <dm/device_compat.h> 40#include <malloc.h> 41#include <spi.h> 42#include <spi-mem.h> 43#include <asm/io.h> 44#ifdef CONFIG_FSL_LAYERSCAPE 45#include <asm/arch/clock.h> 46#include <asm/arch/soc.h> 47#include <asm/arch/speed.h> 48#endif 49#include <linux/bitops.h> 50#include <linux/kernel.h> 51#include <linux/sizes.h> 52#include <linux/iopoll.h> 53#include <linux/bug.h> 54#include <linux/err.h> 55 56/* 57 * The driver only uses one single LUT entry, that is updated on 58 * each call of exec_op(). Index 0 is preset at boot with a basic 59 * read operation, so let's use the last entry (31). 60 */ 61#define SEQID_LUT 31 62 63/* Registers used by the driver */ 64#define FSPI_MCR0 0x00 65#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 66#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 67#define FSPI_MCR0_LEARN_EN BIT(15) 68#define FSPI_MCR0_SCRFRUN_EN BIT(14) 69#define FSPI_MCR0_OCTCOMB_EN BIT(13) 70#define FSPI_MCR0_DOZE_EN BIT(12) 71#define FSPI_MCR0_HSEN BIT(11) 72#define FSPI_MCR0_SERCLKDIV BIT(8) 73#define FSPI_MCR0_ATDF_EN BIT(7) 74#define FSPI_MCR0_ARDF_EN BIT(6) 75#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 76#define FSPI_MCR0_END_CFG(x) ((x) << 2) 77#define FSPI_MCR0_MDIS BIT(1) 78#define FSPI_MCR0_SWRST BIT(0) 79 80#define FSPI_MCR1 0x04 81#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 82#define FSPI_MCR1_AHB_TIMEOUT(x) (x) 83 84#define FSPI_MCR2 0x08 85#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 86#define FSPI_MCR2_SAMEDEVICEEN BIT(15) 87#define FSPI_MCR2_CLRLRPHS BIT(14) 88#define FSPI_MCR2_ABRDATSZ BIT(8) 89#define FSPI_MCR2_ABRLEARN BIT(7) 90#define FSPI_MCR2_ABR_READ BIT(6) 91#define FSPI_MCR2_ABRWRITE BIT(5) 92#define FSPI_MCR2_ABRDUMMY BIT(4) 93#define FSPI_MCR2_ABR_MODE BIT(3) 94#define FSPI_MCR2_ABRCADDR BIT(2) 95#define FSPI_MCR2_ABRRADDR BIT(1) 96#define FSPI_MCR2_ABR_CMD BIT(0) 97 98#define FSPI_AHBCR 0x0c 99#define FSPI_AHBCR_RDADDROPT BIT(6) 100#define FSPI_AHBCR_PREF_EN BIT(5) 101#define FSPI_AHBCR_BUFF_EN BIT(4) 102#define FSPI_AHBCR_CACH_EN BIT(3) 103#define FSPI_AHBCR_CLRTXBUF BIT(2) 104#define FSPI_AHBCR_CLRRXBUF BIT(1) 105#define FSPI_AHBCR_PAR_EN BIT(0) 106 107#define FSPI_INTEN 0x10 108#define FSPI_INTEN_SCLKSBWR BIT(9) 109#define FSPI_INTEN_SCLKSBRD BIT(8) 110#define FSPI_INTEN_DATALRNFL BIT(7) 111#define FSPI_INTEN_IPTXWE BIT(6) 112#define FSPI_INTEN_IPRXWA BIT(5) 113#define FSPI_INTEN_AHBCMDERR BIT(4) 114#define FSPI_INTEN_IPCMDERR BIT(3) 115#define FSPI_INTEN_AHBCMDGE BIT(2) 116#define FSPI_INTEN_IPCMDGE BIT(1) 117#define FSPI_INTEN_IPCMDDONE BIT(0) 118 119#define FSPI_INTR 0x14 120#define FSPI_INTR_SCLKSBWR BIT(9) 121#define FSPI_INTR_SCLKSBRD BIT(8) 122#define FSPI_INTR_DATALRNFL BIT(7) 123#define FSPI_INTR_IPTXWE BIT(6) 124#define FSPI_INTR_IPRXWA BIT(5) 125#define FSPI_INTR_AHBCMDERR BIT(4) 126#define FSPI_INTR_IPCMDERR BIT(3) 127#define FSPI_INTR_AHBCMDGE BIT(2) 128#define FSPI_INTR_IPCMDGE BIT(1) 129#define FSPI_INTR_IPCMDDONE BIT(0) 130 131#define FSPI_LUTKEY 0x18 132#define FSPI_LUTKEY_VALUE 0x5AF05AF0 133 134#define FSPI_LCKCR 0x1C 135 136#define FSPI_LCKER_LOCK 0x1 137#define FSPI_LCKER_UNLOCK 0x2 138 139#define FSPI_BUFXCR_INVALID_MSTRID 0xE 140#define FSPI_AHBRX_BUF0CR0 0x20 141#define FSPI_AHBRX_BUF1CR0 0x24 142#define FSPI_AHBRX_BUF2CR0 0x28 143#define FSPI_AHBRX_BUF3CR0 0x2C 144#define FSPI_AHBRX_BUF4CR0 0x30 145#define FSPI_AHBRX_BUF5CR0 0x34 146#define FSPI_AHBRX_BUF6CR0 0x38 147#define FSPI_AHBRX_BUF7CR0 0x3C 148#define FSPI_AHBRXBUF0CR7_PREF BIT(31) 149 150#define FSPI_AHBRX_BUF0CR1 0x40 151#define FSPI_AHBRX_BUF1CR1 0x44 152#define FSPI_AHBRX_BUF2CR1 0x48 153#define FSPI_AHBRX_BUF3CR1 0x4C 154#define FSPI_AHBRX_BUF4CR1 0x50 155#define FSPI_AHBRX_BUF5CR1 0x54 156#define FSPI_AHBRX_BUF6CR1 0x58 157#define FSPI_AHBRX_BUF7CR1 0x5C 158 159#define FSPI_FLSHA1CR0 0x60 160#define FSPI_FLSHA2CR0 0x64 161#define FSPI_FLSHB1CR0 0x68 162#define FSPI_FLSHB2CR0 0x6C 163#define FSPI_FLSHXCR0_SZ_KB 10 164#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 165 166#define FSPI_FLSHA1CR1 0x70 167#define FSPI_FLSHA2CR1 0x74 168#define FSPI_FLSHB1CR1 0x78 169#define FSPI_FLSHB2CR1 0x7C 170#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 171#define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 172#define FSPI_FLSHXCR1_WA BIT(10) 173#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 174#define FSPI_FLSHXCR1_TCSS(x) (x) 175 176#define FSPI_FLSHA1CR2 0x80 177#define FSPI_FLSHA2CR2 0x84 178#define FSPI_FLSHB1CR2 0x88 179#define FSPI_FLSHB2CR2 0x8C 180#define FSPI_FLSHXCR2_CLRINSP BIT(24) 181#define FSPI_FLSHXCR2_AWRWAIT BIT(16) 182#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 183#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 184#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 185#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 186 187#define FSPI_IPCR0 0xA0 188 189#define FSPI_IPCR1 0xA4 190#define FSPI_IPCR1_IPAREN BIT(31) 191#define FSPI_IPCR1_SEQNUM_SHIFT 24 192#define FSPI_IPCR1_SEQID_SHIFT 16 193#define FSPI_IPCR1_IDATSZ(x) (x) 194 195#define FSPI_IPCMD 0xB0 196#define FSPI_IPCMD_TRG BIT(0) 197 198#define FSPI_DLPR 0xB4 199 200#define FSPI_IPRXFCR 0xB8 201#define FSPI_IPRXFCR_CLR BIT(0) 202#define FSPI_IPRXFCR_DMA_EN BIT(1) 203#define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 204 205#define FSPI_IPTXFCR 0xBC 206#define FSPI_IPTXFCR_CLR BIT(0) 207#define FSPI_IPTXFCR_DMA_EN BIT(1) 208#define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 209 210#define FSPI_DLLACR 0xC0 211#define FSPI_DLLACR_OVRDEN BIT(8) 212 213#define FSPI_DLLBCR 0xC4 214#define FSPI_DLLBCR_OVRDEN BIT(8) 215 216#define FSPI_STS0 0xE0 217#define FSPI_STS0_DLPHB(x) ((x) << 8) 218#define FSPI_STS0_DLPHA(x) ((x) << 4) 219#define FSPI_STS0_CMD_SRC(x) ((x) << 2) 220#define FSPI_STS0_ARB_IDLE BIT(1) 221#define FSPI_STS0_SEQ_IDLE BIT(0) 222 223#define FSPI_STS1 0xE4 224#define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 225#define FSPI_STS1_IP_ERRID(x) ((x) << 16) 226#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 227#define FSPI_STS1_AHB_ERRID(x) (x) 228 229#define FSPI_AHBSPNST 0xEC 230#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 231#define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 232#define FSPI_AHBSPNST_ACTIVE BIT(0) 233 234#define FSPI_IPRXFSTS 0xF0 235#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 236#define FSPI_IPRXFSTS_FILL(x) (x) 237 238#define FSPI_IPTXFSTS 0xF4 239#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 240#define FSPI_IPTXFSTS_FILL(x) (x) 241 242#define FSPI_RFDR 0x100 243#define FSPI_TFDR 0x180 244 245#define FSPI_LUT_BASE 0x200 246#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 247#define FSPI_LUT_REG(idx) \ 248 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 249 250/* register map end */ 251 252/* Instruction set for the LUT register. */ 253#define LUT_STOP 0x00 254#define LUT_CMD 0x01 255#define LUT_ADDR 0x02 256#define LUT_CADDR_SDR 0x03 257#define LUT_MODE 0x04 258#define LUT_MODE2 0x05 259#define LUT_MODE4 0x06 260#define LUT_MODE8 0x07 261#define LUT_NXP_WRITE 0x08 262#define LUT_NXP_READ 0x09 263#define LUT_LEARN_SDR 0x0A 264#define LUT_DATSZ_SDR 0x0B 265#define LUT_DUMMY 0x0C 266#define LUT_DUMMY_RWDS_SDR 0x0D 267#define LUT_JMP_ON_CS 0x1F 268#define LUT_CMD_DDR 0x21 269#define LUT_ADDR_DDR 0x22 270#define LUT_CADDR_DDR 0x23 271#define LUT_MODE_DDR 0x24 272#define LUT_MODE2_DDR 0x25 273#define LUT_MODE4_DDR 0x26 274#define LUT_MODE8_DDR 0x27 275#define LUT_WRITE_DDR 0x28 276#define LUT_READ_DDR 0x29 277#define LUT_LEARN_DDR 0x2A 278#define LUT_DATSZ_DDR 0x2B 279#define LUT_DUMMY_DDR 0x2C 280#define LUT_DUMMY_RWDS_DDR 0x2D 281 282/* 283 * Calculate number of required PAD bits for LUT register. 284 * 285 * The pad stands for the number of IO lines [0:7]. 286 * For example, the octal read needs eight IO lines, 287 * so you should use LUT_PAD(8). This macro 288 * returns 3 i.e. use eight (2^3) IP lines for read. 289 */ 290#define LUT_PAD(x) (fls(x) - 1) 291 292/* 293 * Macro for constructing the LUT entries with the following 294 * register layout: 295 * 296 * --------------------------------------------------- 297 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 298 * --------------------------------------------------- 299 */ 300#define PAD_SHIFT 8 301#define INSTR_SHIFT 10 302#define OPRND_SHIFT 16 303 304/* Macros for constructing the LUT register. */ 305#define LUT_DEF(idx, ins, pad, opr) \ 306 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 307 (opr)) << (((idx) % 2) * OPRND_SHIFT)) 308 309#define POLL_TOUT 5000 310#define NXP_FSPI_MAX_CHIPSELECT 4 311 312/* Access flash memory using IP bus only */ 313#define FSPI_QUIRK_USE_IP_ONLY BIT(0) 314 315struct nxp_fspi_devtype_data { 316 unsigned int rxfifo; 317 unsigned int txfifo; 318 unsigned int ahb_buf_size; 319 unsigned int quirks; 320 bool little_endian; 321}; 322 323static struct nxp_fspi_devtype_data lx2160a_data = { 324 .rxfifo = SZ_512, /* (64 * 64 bits) */ 325 .txfifo = SZ_1K, /* (128 * 64 bits) */ 326 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 327 .quirks = 0, 328 .little_endian = true, /* little-endian */ 329}; 330 331static struct nxp_fspi_devtype_data imx8mm_data = { 332 .rxfifo = SZ_512, /* (64 * 64 bits) */ 333 .txfifo = SZ_1K, /* (128 * 64 bits) */ 334 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 335 .quirks = 0, 336 .little_endian = true, /* little-endian */ 337}; 338 339struct nxp_fspi { 340 struct udevice *dev; 341 void __iomem *iobase; 342 void __iomem *ahb_addr; 343 u32 memmap_phy; 344 u32 memmap_phy_size; 345 struct clk clk, clk_en; 346 struct nxp_fspi_devtype_data *devtype_data; 347}; 348 349static inline int needs_ip_only(struct nxp_fspi *f) 350{ 351 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 352} 353 354/* 355 * R/W functions for big- or little-endian registers: 356 * The FSPI controller's endianness is independent of 357 * the CPU core's endianness. So far, although the CPU 358 * core is little-endian the FSPI controller can use 359 * big-endian or little-endian. 360 */ 361static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 362{ 363 if (f->devtype_data->little_endian) 364 out_le32(addr, val); 365 else 366 out_be32(addr, val); 367} 368 369static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 370{ 371 if (f->devtype_data->little_endian) 372 return in_le32(addr); 373 else 374 return in_be32(addr); 375} 376 377static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 378{ 379 switch (width) { 380 case 1: 381 case 2: 382 case 4: 383 case 8: 384 return 0; 385 } 386 387 return -ENOTSUPP; 388} 389 390static bool nxp_fspi_supports_op(struct spi_slave *slave, 391 const struct spi_mem_op *op) 392{ 393 struct nxp_fspi *f; 394 struct udevice *bus; 395 int ret; 396 397 bus = slave->dev->parent; 398 f = dev_get_priv(bus); 399 400 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 401 402 if (op->addr.nbytes) 403 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 404 405 if (op->dummy.nbytes) 406 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 407 408 if (op->data.nbytes) 409 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 410 411 if (ret) 412 return false; 413 414 /* 415 * The number of address bytes should be equal to or less than 4 bytes. 416 */ 417 if (op->addr.nbytes > 4) 418 return false; 419 420 /* 421 * If requested address value is greater than controller assigned 422 * memory mapped space, return error as it didn't fit in the range 423 * of assigned address space. 424 */ 425 if (op->addr.val >= f->memmap_phy_size) 426 return false; 427 428 /* Max 64 dummy clock cycles supported */ 429 if (op->dummy.buswidth && 430 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 431 return false; 432 433 /* Max data length, check controller limits and alignment */ 434 if (op->data.dir == SPI_MEM_DATA_IN && 435 (op->data.nbytes > f->devtype_data->ahb_buf_size || 436 (op->data.nbytes > f->devtype_data->rxfifo - 4 && 437 !IS_ALIGNED(op->data.nbytes, 8)))) 438 return false; 439 440 if (op->data.dir == SPI_MEM_DATA_OUT && 441 op->data.nbytes > f->devtype_data->txfifo) 442 return false; 443 444 return spi_mem_default_supports_op(slave, op); 445} 446 447/* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */ 448static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 449 u32 mask, u32 delay_us, 450 u32 timeout_us, bool c) 451{ 452 u32 reg; 453 454 if (!f->devtype_data->little_endian) 455 mask = (u32)cpu_to_be32(mask); 456 457 if (c) 458 return readl_poll_sleep_timeout(base, reg, (reg & mask), 459 delay_us, timeout_us); 460 else 461 return readl_poll_sleep_timeout(base, reg, !(reg & mask), 462 delay_us, timeout_us); 463} 464 465/* 466 * If the slave device content being changed by Write/Erase, need to 467 * invalidate the AHB buffer. This can be achieved by doing the reset 468 * of controller after setting MCR0[SWRESET] bit. 469 */ 470static inline void nxp_fspi_invalid(struct nxp_fspi *f) 471{ 472 u32 reg; 473 int ret; 474 475 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 476 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 477 478 /* w1c register, wait unit clear */ 479 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 480 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 481 WARN_ON(ret); 482} 483 484static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 485 const struct spi_mem_op *op) 486{ 487 void __iomem *base = f->iobase; 488 u32 lutval[4] = {}; 489 int lutidx = 1, i; 490 491 /* cmd */ 492 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 493 op->cmd.opcode); 494 495 /* addr bytes */ 496 if (op->addr.nbytes) { 497 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 498 LUT_PAD(op->addr.buswidth), 499 op->addr.nbytes * 8); 500 lutidx++; 501 } 502 503 /* dummy bytes, if needed */ 504 if (op->dummy.nbytes) { 505 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 506 /* 507 * Due to FlexSPI controller limitation number of PAD for dummy 508 * buswidth needs to be programmed as equal to data buswidth. 509 */ 510 LUT_PAD(op->data.buswidth), 511 op->dummy.nbytes * 8 / 512 op->dummy.buswidth); 513 lutidx++; 514 } 515 516 /* read/write data bytes */ 517 if (op->data.nbytes) { 518 lutval[lutidx / 2] |= LUT_DEF(lutidx, 519 op->data.dir == SPI_MEM_DATA_IN ? 520 LUT_NXP_READ : LUT_NXP_WRITE, 521 LUT_PAD(op->data.buswidth), 522 0); 523 lutidx++; 524 } 525 526 /* stop condition. */ 527 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 528 529 /* unlock LUT */ 530 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 531 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 532 533 /* fill LUT */ 534 for (i = 0; i < ARRAY_SIZE(lutval); i++) 535 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 536 537 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", 538 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 539 540 /* lock LUT */ 541 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 542 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 543} 544 545#if CONFIG_IS_ENABLED(CLK) 546static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 547{ 548 int ret; 549 550 ret = clk_enable(&f->clk_en); 551 if (ret) 552 return ret; 553 554 ret = clk_enable(&f->clk); 555 if (ret) { 556 clk_disable(&f->clk_en); 557 return ret; 558 } 559 560 return 0; 561} 562 563static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 564{ 565 clk_disable(&f->clk); 566 clk_disable(&f->clk_en); 567} 568#endif 569 570/* 571 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 572 * register and start base address of the slave device. 573 * 574 * (Higher address) 575 * -------- <-- FLSHB2CR0 576 * | B2 | 577 * | | 578 * B2 start address --> -------- <-- FLSHB1CR0 579 * | B1 | 580 * | | 581 * B1 start address --> -------- <-- FLSHA2CR0 582 * | A2 | 583 * | | 584 * A2 start address --> -------- <-- FLSHA1CR0 585 * | A1 | 586 * | | 587 * A1 start address --> -------- (Lower address) 588 * 589 * 590 * Start base address defines the starting address range for given CS and 591 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 592 * 593 * But, different targets are having different combinations of number of CS, 594 * some targets only have single CS or two CS covering controller's full 595 * memory mapped space area. 596 * Thus, implementation is being done as independent of the size and number 597 * of the connected slave device. 598 * Assign controller memory mapped space size as the size to the connected 599 * slave device. 600 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 601 * chip-select Flash configuration register. 602 * 603 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 604 * memory mapped size of the controller. 605 * Value for rest of the CS FLSHxxCR0 register would be zero. 606 * 607 */ 608static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select) 609{ 610 u64 size_kb; 611 612 /* Reset FLSHxxCR0 registers */ 613 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 614 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 615 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 616 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 617 618 /* Assign controller memory mapped space as size, KBytes, of flash. */ 619 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 620 621 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 622 4 * chip_select); 623 624 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select); 625} 626 627static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 628{ 629 u32 len = op->data.nbytes; 630 631 /* Read out the data directly from the AHB buffer. */ 632 memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len); 633} 634 635static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 636 const struct spi_mem_op *op) 637{ 638 void __iomem *base = f->iobase; 639 int i, ret; 640 u8 *buf = (u8 *)op->data.buf.out; 641 642 /* clear the TX FIFO. */ 643 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 644 645 /* 646 * Default value of water mark level is 8 bytes, hence in single 647 * write request controller can write max 8 bytes of data. 648 */ 649 650 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 651 /* Wait for TXFIFO empty */ 652 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 653 FSPI_INTR_IPTXWE, 0, 654 POLL_TOUT, true); 655 WARN_ON(ret); 656 657 fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR); 658 fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4); 659 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 660 } 661 662 if (i < op->data.nbytes) { 663 u32 data = 0; 664 int j; 665 /* Wait for TXFIFO empty */ 666 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 667 FSPI_INTR_IPTXWE, 0, 668 POLL_TOUT, true); 669 WARN_ON(ret); 670 671 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 672 memcpy(&data, buf + i + j, 4); 673 fspi_writel(f, data, base + FSPI_TFDR + j); 674 } 675 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 676 } 677} 678 679static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 680 const struct spi_mem_op *op) 681{ 682 void __iomem *base = f->iobase; 683 int i, ret; 684 int len = op->data.nbytes; 685 u8 *buf = (u8 *)op->data.buf.in; 686 687 /* 688 * Default value of water mark level is 8 bytes, hence in single 689 * read request controller can read max 8 bytes of data. 690 */ 691 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 692 /* Wait for RXFIFO available */ 693 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 694 FSPI_INTR_IPRXWA, 0, 695 POLL_TOUT, true); 696 WARN_ON(ret); 697 698 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 699 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 700 /* move the FIFO pointer */ 701 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 702 } 703 704 if (i < len) { 705 u32 tmp; 706 int size, j; 707 708 buf = op->data.buf.in + i; 709 /* Wait for RXFIFO available */ 710 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 711 FSPI_INTR_IPRXWA, 0, 712 POLL_TOUT, true); 713 WARN_ON(ret); 714 715 len = op->data.nbytes - i; 716 for (j = 0; j < op->data.nbytes - i; j += 4) { 717 tmp = fspi_readl(f, base + FSPI_RFDR + j); 718 size = min(len, 4); 719 memcpy(buf + j, &tmp, size); 720 len -= size; 721 } 722 } 723 724 /* invalid the RXFIFO */ 725 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 726 /* move the FIFO pointer */ 727 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 728} 729 730static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 731{ 732 void __iomem *base = f->iobase; 733 int seqnum = 0; 734 int err = 0; 735 u32 reg; 736 737 reg = fspi_readl(f, base + FSPI_IPRXFCR); 738 /* invalid RXFIFO first */ 739 reg &= ~FSPI_IPRXFCR_DMA_EN; 740 reg = reg | FSPI_IPRXFCR_CLR; 741 fspi_writel(f, reg, base + FSPI_IPRXFCR); 742 743 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 744 /* 745 * Always start the sequence at the same index since we update 746 * the LUT at each exec_op() call. And also specify the DATA 747 * length, since it's has not been specified in the LUT. 748 */ 749 fspi_writel(f, op->data.nbytes | 750 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 751 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 752 base + FSPI_IPCR1); 753 754 /* Trigger the LUT now. */ 755 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 756 757 /* Wait for the completion. */ 758 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 759 FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true); 760 761 /* Invoke IP data read, if request is of data read. */ 762 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 763 nxp_fspi_read_rxfifo(f, op); 764 765 return err; 766} 767 768static int nxp_fspi_exec_op(struct spi_slave *slave, 769 const struct spi_mem_op *op) 770{ 771 struct nxp_fspi *f; 772 struct udevice *bus; 773 int err = 0; 774 775 bus = slave->dev->parent; 776 f = dev_get_priv(bus); 777 778 /* Wait for controller being ready. */ 779 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 780 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 781 WARN_ON(err); 782 783 nxp_fspi_prepare_lut(f, op); 784 /* 785 * If we have large chunks of data, we read them through the AHB bus by 786 * accessing the mapped memory. In all other cases we use IP commands 787 * to access the flash. Read via AHB bus may be corrupted due to 788 * existence of an errata and therefore discard AHB read in such cases. 789 */ 790 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 791 op->data.dir == SPI_MEM_DATA_IN && 792 !needs_ip_only(f)) { 793 nxp_fspi_read_ahb(f, op); 794 } else { 795 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 796 nxp_fspi_fill_txfifo(f, op); 797 798 err = nxp_fspi_do_op(f, op); 799 } 800 801 /* Invalidate the data in the AHB buffer. */ 802 nxp_fspi_invalid(f); 803 804 return err; 805} 806 807static int nxp_fspi_adjust_op_size(struct spi_slave *slave, 808 struct spi_mem_op *op) 809{ 810 struct nxp_fspi *f; 811 struct udevice *bus; 812 813 bus = slave->dev->parent; 814 f = dev_get_priv(bus); 815 816 if (op->data.dir == SPI_MEM_DATA_OUT) { 817 if (op->data.nbytes > f->devtype_data->txfifo) 818 op->data.nbytes = f->devtype_data->txfifo; 819 } else { 820 if (op->data.nbytes > f->devtype_data->ahb_buf_size) 821 op->data.nbytes = f->devtype_data->ahb_buf_size; 822 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 823 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 824 } 825 826 /* Limit data bytes to RX FIFO in case of IP read only */ 827 if (needs_ip_only(f) && 828 op->data.dir == SPI_MEM_DATA_IN && 829 op->data.nbytes > f->devtype_data->rxfifo) 830 op->data.nbytes = f->devtype_data->rxfifo; 831 832 return 0; 833} 834 835#ifdef CONFIG_FSL_LAYERSCAPE 836static void erratum_err050568(struct nxp_fspi *f) 837{ 838 struct sys_info sysinfo; 839 u32 svr = 0, freq = 0; 840 841 /* Check for LS1028A variants */ 842 svr = SVR_SOC_VER(get_svr()); 843 if (svr != SVR_LS1017A || 844 svr != SVR_LS1018A || 845 svr != SVR_LS1027A || 846 svr != SVR_LS1028A) { 847 dev_dbg(f->dev, "Errata applicable only for LS1028A variants\n"); 848 return; 849 } 850 851 /* Read PLL frequency */ 852 get_sys_info(&sysinfo); 853 freq = sysinfo.freq_systembus / 1000000; /* Convert to MHz */ 854 dev_dbg(f->dev, "svr: %08x, Frequency: %dMhz\n", svr, freq); 855 856 /* Use IP bus only if PLL is 300MHz */ 857 if (freq == 300) 858 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 859} 860#endif 861 862static int nxp_fspi_default_setup(struct nxp_fspi *f) 863{ 864 void __iomem *base = f->iobase; 865 int ret, i; 866 u32 reg; 867 868#if CONFIG_IS_ENABLED(CLK) 869 /* the default frequency, we will change it later if necessary. */ 870 ret = clk_set_rate(&f->clk, 20000000); 871 if (ret < 0) 872 return ret; 873 874 ret = nxp_fspi_clk_prep_enable(f); 875 if (ret) 876 return ret; 877#endif 878 879#ifdef CONFIG_FSL_LAYERSCAPE 880 /* 881 * ERR050568: Flash access by FlexSPI AHB command may not work with 882 * platform frequency equal to 300 MHz on LS1028A. 883 * LS1028A reuses LX2160A compatible entry. Make errata applicable for 884 * Layerscape LS1028A platform family. 885 */ 886 if (device_is_compatible(f->dev, "nxp,lx2160a-fspi")) 887 erratum_err050568(f); 888#endif 889 890 /* Reset the module */ 891 /* w1c register, wait unit clear */ 892 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 893 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 894 WARN_ON(ret); 895 896 /* Disable the module */ 897 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 898 899 /* Reset the DLL register to default value */ 900 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 901 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 902 903 /* enable module */ 904 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF), 905 base + FSPI_MCR0); 906 907 /* 908 * Disable same device enable bit and configure all slave devices 909 * independently. 910 */ 911 reg = fspi_readl(f, f->iobase + FSPI_MCR2); 912 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 913 fspi_writel(f, reg, base + FSPI_MCR2); 914 915 /* AHB configuration for access buffer 0~7. */ 916 for (i = 0; i < 7; i++) 917 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 918 919 /* 920 * Set ADATSZ with the maximum AHB buffer size to improve the read 921 * performance. 922 */ 923 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 924 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 925 926 /* prefetch and no start address alignment limitation */ 927 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 928 base + FSPI_AHBCR); 929 930 /* Reset the flashx control1 registers */ 931 reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3); 932 fspi_writel(f, reg, base + FSPI_FLSHA1CR1); 933 fspi_writel(f, reg, base + FSPI_FLSHA2CR1); 934 fspi_writel(f, reg, base + FSPI_FLSHB1CR1); 935 fspi_writel(f, reg, base + FSPI_FLSHB2CR1); 936 937 /* AHB Read - Set lut sequence ID for all CS. */ 938 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 939 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 940 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 941 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 942 943 return 0; 944} 945 946static int nxp_fspi_probe(struct udevice *bus) 947{ 948 struct nxp_fspi *f = dev_get_priv(bus); 949 950 f->devtype_data = 951 (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus); 952 nxp_fspi_default_setup(f); 953 954 return 0; 955} 956 957static int nxp_fspi_claim_bus(struct udevice *dev) 958{ 959 struct nxp_fspi *f; 960 struct udevice *bus; 961 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 962 963 bus = dev->parent; 964 f = dev_get_priv(bus); 965 966 nxp_fspi_select_mem(f, slave_plat->cs); 967 968 return 0; 969} 970 971static int nxp_fspi_set_speed(struct udevice *bus, uint speed) 972{ 973#if CONFIG_IS_ENABLED(CLK) 974 struct nxp_fspi *f = dev_get_priv(bus); 975 int ret; 976 977 nxp_fspi_clk_disable_unprep(f); 978 979 ret = clk_set_rate(&f->clk, speed); 980 if (ret < 0) 981 return ret; 982 983 ret = nxp_fspi_clk_prep_enable(f); 984 if (ret) 985 return ret; 986#endif 987 return 0; 988} 989 990static int nxp_fspi_set_mode(struct udevice *bus, uint mode) 991{ 992 /* Nothing to do */ 993 return 0; 994} 995 996static int nxp_fspi_of_to_plat(struct udevice *bus) 997{ 998 struct nxp_fspi *f = dev_get_priv(bus); 999#if CONFIG_IS_ENABLED(CLK) 1000 int ret; 1001#endif 1002 1003 fdt_addr_t iobase; 1004 fdt_addr_t iobase_size; 1005 fdt_addr_t ahb_addr; 1006 fdt_addr_t ahb_size; 1007 1008 f->dev = bus; 1009 1010 iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size); 1011 if (iobase == FDT_ADDR_T_NONE) { 1012 dev_err(bus, "fspi_base regs missing\n"); 1013 return -ENODEV; 1014 } 1015 f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE); 1016 1017 ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size); 1018 if (ahb_addr == FDT_ADDR_T_NONE) { 1019 dev_err(bus, "fspi_mmap regs missing\n"); 1020 return -ENODEV; 1021 } 1022 f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE); 1023 f->memmap_phy_size = ahb_size; 1024 1025#if CONFIG_IS_ENABLED(CLK) 1026 ret = clk_get_by_name(bus, "fspi_en", &f->clk_en); 1027 if (ret) { 1028 dev_err(bus, "failed to get fspi_en clock\n"); 1029 return ret; 1030 } 1031 1032 ret = clk_get_by_name(bus, "fspi", &f->clk); 1033 if (ret) { 1034 dev_err(bus, "failed to get fspi clock\n"); 1035 return ret; 1036 } 1037#endif 1038 1039 dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr); 1040 1041 return 0; 1042} 1043 1044static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1045 .adjust_op_size = nxp_fspi_adjust_op_size, 1046 .supports_op = nxp_fspi_supports_op, 1047 .exec_op = nxp_fspi_exec_op, 1048}; 1049 1050static const struct dm_spi_ops nxp_fspi_ops = { 1051 .claim_bus = nxp_fspi_claim_bus, 1052 .set_speed = nxp_fspi_set_speed, 1053 .set_mode = nxp_fspi_set_mode, 1054 .mem_ops = &nxp_fspi_mem_ops, 1055}; 1056 1057static const struct udevice_id nxp_fspi_ids[] = { 1058 { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, }, 1059 { .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, }, 1060 { .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, }, 1061 { } 1062}; 1063 1064U_BOOT_DRIVER(nxp_fspi) = { 1065 .name = "nxp_fspi", 1066 .id = UCLASS_SPI, 1067 .of_match = nxp_fspi_ids, 1068 .ops = &nxp_fspi_ops, 1069 .of_to_plat = nxp_fspi_of_to_plat, 1070 .priv_auto = sizeof(struct nxp_fspi), 1071 .probe = nxp_fspi_probe, 1072}; 1073