1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2021 Nuvoton Technology.
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <spi.h>
9#include <clk.h>
10#include <reset.h>
11#include <asm/gpio.h>
12#include <linux/iopoll.h>
13
14#define MAX_DIV	127
15
16/* Register offsets */
17#define PSPI_DATA		0
18#define PSPI_CTL1		2
19#define PSPI_STAT		4
20
21/* PSPI_CTL1 fields */
22#define PSPI_CTL1_SPIEN		BIT(0)
23#define PSPI_CTL1_SCM		BIT(7)
24#define PSPI_CTL1_SCIDL		BIT(8)
25#define PSPI_CTL1_SCDV_MASK	GENMASK(15, 9)
26#define PSPI_CTL1_SCDV_SHIFT	9
27
28/* PSPI_STAT fields */
29#define PSPI_STAT_BSY		BIT(0)
30#define PSPI_STAT_RBF		BIT(1)
31
32struct npcm_pspi_priv {
33	void __iomem *base;
34	struct clk clk;
35	struct gpio_desc cs_gpio;
36	u32 max_hz;
37};
38
39static inline void spi_cs_activate(struct udevice *dev)
40{
41	struct udevice *bus = dev->parent;
42	struct npcm_pspi_priv *priv = dev_get_priv(bus);
43
44	dm_gpio_set_value(&priv->cs_gpio, 1);
45}
46
47static inline void spi_cs_deactivate(struct udevice *dev)
48{
49	struct udevice *bus = dev->parent;
50	struct npcm_pspi_priv *priv = dev_get_priv(bus);
51
52	dm_gpio_set_value(&priv->cs_gpio, 0);
53}
54
55static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv)
56{
57	u16 val;
58
59	val = readw(priv->base + PSPI_CTL1);
60	val |= PSPI_CTL1_SPIEN;
61	writew(val, priv->base + PSPI_CTL1);
62}
63
64static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv)
65{
66	u16 val;
67
68	val = readw(priv->base + PSPI_CTL1);
69	val &= ~PSPI_CTL1_SPIEN;
70	writew(val, priv->base + PSPI_CTL1);
71}
72
73static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen,
74			  const void *dout, void *din, unsigned long flags)
75{
76	struct udevice *bus = dev->parent;
77	struct npcm_pspi_priv *priv = dev_get_priv(bus);
78	void __iomem *base = priv->base;
79	const u8 *tx = dout;
80	u8 *rx = din;
81	u32 bytes = bitlen / 8;
82	u8 tmp;
83	u32 val;
84	int i, ret = 0;
85
86	npcm_pspi_enable(priv);
87
88	if (flags & SPI_XFER_BEGIN)
89		spi_cs_activate(dev);
90
91	for (i = 0; i < bytes; i++) {
92		/* Making sure we can write */
93		ret = readb_poll_timeout(base + PSPI_STAT, val,
94					 !(val & PSPI_STAT_BSY),
95					 1000000);
96		if (ret < 0)
97			break;
98
99		if (tx)
100			writeb(*tx++, base + PSPI_DATA);
101		else
102			writeb(0, base + PSPI_DATA);
103
104		/* Wait till write completed */
105		ret = readb_poll_timeout(base + PSPI_STAT, val,
106					 !(val & PSPI_STAT_BSY),
107					 1000000);
108		if (ret < 0)
109			break;
110
111		/* Wait till read buffer full */
112		ret = readb_poll_timeout(base + PSPI_STAT, val,
113					 (val & PSPI_STAT_RBF),
114					 1000000);
115		if (ret < 0)
116			break;
117
118		tmp = readb(base + PSPI_DATA);
119		if (rx)
120			*rx++ = tmp;
121	}
122
123	if (flags & SPI_XFER_END)
124		spi_cs_deactivate(dev);
125
126	debug("npcm_pspi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
127	      dev->parent->name, dev->name, *(uint *)tx, *(uint *)rx, bitlen);
128
129	npcm_pspi_disable(priv);
130
131	return ret;
132}
133
134static int npcm_pspi_set_speed(struct udevice *bus, uint speed)
135{
136	struct npcm_pspi_priv *priv = dev_get_priv(bus);
137	ulong apb_clock;
138	u32 divisor;
139	u16 val;
140
141	apb_clock = clk_get_rate(&priv->clk);
142	if (!apb_clock)
143		return -EINVAL;
144
145	if (speed > priv->max_hz)
146		speed = priv->max_hz;
147
148	divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed)) - 1;
149	if (divisor > MAX_DIV)
150		divisor = MAX_DIV;
151
152	val = readw(priv->base + PSPI_CTL1);
153	val &= ~PSPI_CTL1_SCDV_MASK;
154	val |= divisor << PSPI_CTL1_SCDV_SHIFT;
155	writew(val, priv->base + PSPI_CTL1);
156
157	debug("%s: apb_clock=%lu speed=%d divisor=%u\n",
158	      __func__, apb_clock, speed, divisor);
159
160	return 0;
161}
162
163static int npcm_pspi_set_mode(struct udevice *bus, uint mode)
164{
165	struct npcm_pspi_priv *priv = dev_get_priv(bus);
166	u16 pspi_mode, val;
167
168	switch (mode & (SPI_CPOL | SPI_CPHA)) {
169	case SPI_MODE_0:
170		pspi_mode = 0;
171		break;
172	case SPI_MODE_1:
173		pspi_mode = PSPI_CTL1_SCM;
174		break;
175	case SPI_MODE_2:
176		pspi_mode = PSPI_CTL1_SCIDL;
177		break;
178	case SPI_MODE_3:
179		pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM;
180		break;
181	default:
182		break;
183	}
184
185	val = readw(priv->base + PSPI_CTL1);
186	val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM);
187	val |= pspi_mode;
188	writew(val, priv->base + PSPI_CTL1);
189
190	debug("%s: mode=%u\n", __func__, mode);
191	return 0;
192}
193
194static int npcm_pspi_probe(struct udevice *bus)
195{
196	struct npcm_pspi_priv *priv = dev_get_priv(bus);
197	int node = dev_of_offset(bus);
198	struct reset_ctl reset;
199	int ret;
200
201	ret = clk_get_by_index(bus, 0, &priv->clk);
202	if (ret < 0)
203		return ret;
204
205	priv->base = dev_read_addr_ptr(bus);
206	priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1000000);
207	gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
208				   &priv->cs_gpio, GPIOD_IS_OUT| GPIOD_ACTIVE_LOW);
209
210	/* Reset HW */
211	ret = reset_get_by_index(bus, 0, &reset);
212	if (!ret) {
213		reset_assert(&reset);
214		udelay(5);
215		reset_deassert(&reset);
216	}
217
218	return 0;
219}
220
221static const struct dm_spi_ops npcm_pspi_ops = {
222	.xfer           = npcm_pspi_xfer,
223	.set_speed      = npcm_pspi_set_speed,
224	.set_mode       = npcm_pspi_set_mode,
225};
226
227static const struct udevice_id npcm_pspi_ids[] = {
228	{ .compatible = "nuvoton,npcm845-pspi"},
229	{ .compatible = "nuvoton,npcm750-pspi"},
230	{ }
231};
232
233U_BOOT_DRIVER(npcm_pspi) = {
234	.name   = "npcm_pspi",
235	.id     = UCLASS_SPI,
236	.of_match = npcm_pspi_ids,
237	.ops    = &npcm_pspi_ops,
238	.priv_auto = sizeof(struct npcm_pspi_priv),
239	.probe  = npcm_pspi_probe,
240};
241