1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2004-2006 Atmel Corporation 4 * 5 * Modified to support C structur SoC access by 6 * Andreas Bie��mann <biessmann@corscience.de> 7 */ 8#include <common.h> 9#include <clk.h> 10#include <dm.h> 11#include <errno.h> 12#include <malloc.h> 13#include <watchdog.h> 14#include <serial.h> 15#include <debug_uart.h> 16#include <asm/global_data.h> 17#include <linux/compiler.h> 18#include <linux/delay.h> 19 20#include <asm/io.h> 21#if CONFIG_IS_ENABLED(DM_SERIAL) 22#include <asm/arch/atmel_serial.h> 23#endif 24#include <asm/arch/clk.h> 25#include <asm/arch/hardware.h> 26 27#include "atmel_usart.h" 28 29DECLARE_GLOBAL_DATA_PTR; 30 31#if !CONFIG_IS_ENABLED(DM_SERIAL) 32static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id, 33 int baudrate) 34{ 35 unsigned long divisor; 36 unsigned long usart_hz; 37 38 /* 39 * Master Clock 40 * Baud Rate = -------------- 41 * 16 * CD 42 */ 43 usart_hz = get_usart_clk_rate(id); 44 divisor = (usart_hz / 16 + baudrate / 2) / baudrate; 45 writel(USART3_BF(CD, divisor), &usart->brgr); 46} 47 48static void atmel_serial_init_internal(atmel_usart3_t *usart) 49{ 50 /* 51 * Just in case: drain transmitter register 52 * 1000us is enough for baudrate >= 9600 53 */ 54 if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY))) 55 __udelay(1000); 56 57 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); 58} 59 60static void atmel_serial_activate(atmel_usart3_t *usart) 61{ 62 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) 63 | USART3_BF(USCLKS, USART3_USCLKS_MCK) 64 | USART3_BF(CHRL, USART3_CHRL_8) 65 | USART3_BF(PAR, USART3_PAR_NONE) 66 | USART3_BF(NBSTOP, USART3_NBSTOP_1)), 67 &usart->mr); 68 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); 69 /* 100us is enough for the new settings to be settled */ 70 __udelay(100); 71} 72 73static void atmel_serial_setbrg(void) 74{ 75 atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE, 76 CFG_USART_ID, gd->baudrate); 77} 78 79static int atmel_serial_init(void) 80{ 81 atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; 82 83 atmel_serial_init_internal(usart); 84 serial_setbrg(); 85 atmel_serial_activate(usart); 86 87 return 0; 88} 89 90static void atmel_serial_putc(char c) 91{ 92 atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; 93 94 if (c == '\n') 95 serial_putc('\r'); 96 97 while (!(readl(&usart->csr) & USART3_BIT(TXRDY))); 98 writel(c, &usart->thr); 99} 100 101static int atmel_serial_getc(void) 102{ 103 atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; 104 105 while (!(readl(&usart->csr) & USART3_BIT(RXRDY))) 106 schedule(); 107 return readl(&usart->rhr); 108} 109 110static int atmel_serial_tstc(void) 111{ 112 atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; 113 return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0; 114} 115 116static struct serial_device atmel_serial_drv = { 117 .name = "atmel_serial", 118 .start = atmel_serial_init, 119 .stop = NULL, 120 .setbrg = atmel_serial_setbrg, 121 .putc = atmel_serial_putc, 122 .puts = default_serial_puts, 123 .getc = atmel_serial_getc, 124 .tstc = atmel_serial_tstc, 125}; 126 127void atmel_serial_initialize(void) 128{ 129 serial_register(&atmel_serial_drv); 130} 131 132__weak struct serial_device *default_serial_console(void) 133{ 134 return &atmel_serial_drv; 135} 136#else 137enum serial_clk_type { 138 CLK_TYPE_NORMAL = 0, 139 CLK_TYPE_DBGU, 140}; 141 142struct atmel_serial_priv { 143 atmel_usart3_t *usart; 144 ulong usart_clk_rate; 145}; 146 147static void _atmel_serial_set_brg(atmel_usart3_t *usart, 148 ulong usart_clk_rate, int baudrate) 149{ 150 unsigned long divisor; 151 152 divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate; 153 writel(USART3_BF(CD, divisor), &usart->brgr); 154} 155 156void _atmel_serial_init(atmel_usart3_t *usart, 157 ulong usart_clk_rate, int baudrate) 158{ 159 writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr); 160 161 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) | 162 USART3_BF(USCLKS, USART3_USCLKS_MCK) | 163 USART3_BF(CHRL, USART3_CHRL_8) | 164 USART3_BF(PAR, USART3_PAR_NONE) | 165 USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr); 166 167 _atmel_serial_set_brg(usart, usart_clk_rate, baudrate); 168 169 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); 170 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); 171} 172 173int atmel_serial_setbrg(struct udevice *dev, int baudrate) 174{ 175 struct atmel_serial_priv *priv = dev_get_priv(dev); 176 177 _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate); 178 179 return 0; 180} 181 182static int atmel_serial_getc(struct udevice *dev) 183{ 184 struct atmel_serial_priv *priv = dev_get_priv(dev); 185 186 if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY))) 187 return -EAGAIN; 188 189 return readl(&priv->usart->rhr); 190} 191 192static int atmel_serial_putc(struct udevice *dev, const char ch) 193{ 194 struct atmel_serial_priv *priv = dev_get_priv(dev); 195 196 if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY))) 197 return -EAGAIN; 198 199 writel(ch, &priv->usart->thr); 200 201 return 0; 202} 203 204static int atmel_serial_pending(struct udevice *dev, bool input) 205{ 206 struct atmel_serial_priv *priv = dev_get_priv(dev); 207 uint32_t csr = readl(&priv->usart->csr); 208 209 if (input) 210 return csr & USART3_BIT(RXRDY) ? 1 : 0; 211 else 212 return csr & USART3_BIT(TXEMPTY) ? 0 : 1; 213} 214 215static const struct dm_serial_ops atmel_serial_ops = { 216 .putc = atmel_serial_putc, 217 .pending = atmel_serial_pending, 218 .getc = atmel_serial_getc, 219 .setbrg = atmel_serial_setbrg, 220}; 221 222#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK) 223static int atmel_serial_enable_clk(struct udevice *dev) 224{ 225 struct atmel_serial_priv *priv = dev_get_priv(dev); 226 227 /* Use fixed clock value in SPL */ 228 priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK; 229 230 return 0; 231} 232#else 233static int atmel_serial_enable_clk(struct udevice *dev) 234{ 235 struct atmel_serial_priv *priv = dev_get_priv(dev); 236 struct clk clk; 237 ulong clk_rate; 238 int ret; 239 240 ret = clk_get_by_index(dev, 0, &clk); 241 if (ret) 242 return -EINVAL; 243 244 if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) { 245 ret = clk_enable(&clk); 246 if (ret) 247 return ret; 248 } 249 250 clk_rate = clk_get_rate(&clk); 251 if (!clk_rate) 252 return -EINVAL; 253 254 priv->usart_clk_rate = clk_rate; 255 256 return 0; 257} 258#endif 259 260static int atmel_serial_probe(struct udevice *dev) 261{ 262 struct atmel_serial_plat *plat = dev_get_plat(dev); 263 struct atmel_serial_priv *priv = dev_get_priv(dev); 264 int ret; 265#if CONFIG_IS_ENABLED(OF_CONTROL) 266 fdt_addr_t addr_base; 267 268 addr_base = dev_read_addr(dev); 269 if (addr_base == FDT_ADDR_T_NONE) 270 return -ENODEV; 271 272 plat->base_addr = (uint32_t)addr_base; 273#endif 274 priv->usart = (atmel_usart3_t *)plat->base_addr; 275 276 ret = atmel_serial_enable_clk(dev); 277 if (ret) 278 return ret; 279 280 _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate); 281 282 return 0; 283} 284 285#if CONFIG_IS_ENABLED(OF_CONTROL) 286static const struct udevice_id atmel_serial_ids[] = { 287 { 288 .compatible = "atmel,at91sam9260-dbgu", 289 .data = CLK_TYPE_DBGU, 290 }, 291 { 292 .compatible = "atmel,at91sam9260-usart", 293 .data = CLK_TYPE_NORMAL, 294 }, 295 { } 296}; 297#endif 298 299U_BOOT_DRIVER(serial_atmel) = { 300 .name = "serial_atmel", 301 .id = UCLASS_SERIAL, 302#if CONFIG_IS_ENABLED(OF_CONTROL) 303 .of_match = atmel_serial_ids, 304 .plat_auto = sizeof(struct atmel_serial_plat), 305#endif 306 .probe = atmel_serial_probe, 307 .ops = &atmel_serial_ops, 308#if !CONFIG_IS_ENABLED(OF_CONTROL) 309 .flags = DM_FLAG_PRE_RELOC, 310#endif 311 .priv_auto = sizeof(struct atmel_serial_priv), 312}; 313#endif 314 315#ifdef CONFIG_DEBUG_UART_ATMEL 316static inline void _debug_uart_init(void) 317{ 318 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); 319 320 _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); 321} 322 323static inline void _debug_uart_putc(int ch) 324{ 325 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); 326 327 while (!(readl(&usart->csr) & USART3_BIT(TXRDY))) 328 ; 329 330 writel(ch, &usart->thr); 331} 332 333DEBUG_UART_FUNCS 334#endif 335