10x12345678, 22,/* version */ 3(0 << 0) | (1 << 8) | (9 << 16) | (8 << 24),/* cpu_gen,global index */ 4(0 << 0) | (9 << 8) | (17 << 16) | (9 << 24),/* d2,d3 index */ 5(26 << 0) | (9 << 8) | (0 << 16) | (0 << 24),/* d4,d5 index */ 6(0 << 0) | (9 << 8) | (35 << 16) | (9 << 24),/* lp2,lp3 index */ 7(44 << 0) | (13 << 8) | (0 << 16) | (0 << 24),/* lp4,lp5 index */ 8(0 << 0) | (0 << 8) | (57 << 16) | (8 << 24),/* skew index, dq_map index */ 9(65 << 0) | (13 << 8) | (0 << 16) | (0 << 24), /*lp4x index*/ 10/* global info */ 110, 12(93 << 16) | 13,/* sr_idle << 16 | pd_idle */ 130,/* channel info */ 141,/* 2t info */ 150, 0, 0, 0,/* reserved */ 16 17/* ddr3 */ 18(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), 19(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), 20(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), 21/* drv when odt on */ 22(30 << PHY_DQ_DRV_SHIFT) | (41 << PHY_CA_DRV_SHIFT) | 23 (38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), 24/* drv when odt off */ 25(30 << PHY_DQ_DRV_SHIFT) | (30 << PHY_CA_DRV_SHIFT) | 26 (38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), 27/* odt info */ 28(120 << DRAM_ODT_SHIFT) | (141 << PHY_ODT_SHIFT) | 29 (1 << PHY_ODT_PUUP_EN_SHIFT) | 30 (0 << PHY_ODT_PUDN_EN_SHIFT), 31/* odt enable freq */ 32(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT), 33/* slew rate when odt enable */ 34(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) | 35 (0x1f << PHY_CLK_SR_SHIFT), 36/* slew ratee when odt disable */ 37(0x1f << PHY_DQ_SR_SHIFT) | (0x1f << PHY_CA_SR_SHIFT) | 38 (0x1f << PHY_CLK_SR_SHIFT), 39 40/* ddr4 */ 41(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), 42(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), 43(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), 44/* drv when odt on */ 45(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) | 46 (37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), 47/* drv when odt off */ 48(37 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) | 49 (37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), 50/* odt info */ 51(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) | 52 (1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT), 53/* odt enable freq */ 54(625 << DRAM_ODT_EN_FREQ_SHIFT) | (625 << PHY_ODT_EN_FREQ_SHIFT), 55/* slew rate when odt enable */ 56(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) | 57 (0x3 << PHY_CLK_SR_SHIFT), 58/* slew ratee when odt disable */ 59(0xe << PHY_DQ_SR_SHIFT) | (0x3 << PHY_CA_SR_SHIFT) | 60 (0x3 << PHY_CLK_SR_SHIFT), 61 62/* lpddr3 */ 63(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), 64(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), 65(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), 66/* drv when odt on */ 67(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) | 68 (34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), 69/* drv when odt off */ 70(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) | 71 (34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT), 72/* odt info */ 73(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) | 74 (1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT), 75/* odt enable freq */ 76(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT), 77 78/* slew rate when odt enable */ 79(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) | 80 (0x0 << PHY_CLK_SR_SHIFT), 81/* slew ratee when odt disable */ 82(0xe << PHY_DQ_SR_SHIFT) | (0x0 << PHY_CA_SR_SHIFT) | 83 (0x0 << PHY_CLK_SR_SHIFT), 84 85/* lpddr4 */ 86(924 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), 87(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), 88(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), 89 90/* drv when odt on */ 91(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) | 92 (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), 93/* drv when odt off */ 94(38 << PHY_DQ_DRV_SHIFT) | (46 << PHY_CA_DRV_SHIFT) | 95 (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), 96/* odt info and PU-cal info */ 97(240 << DRAM_ODT_SHIFT) | (80 << PHY_ODT_SHIFT) | 98 (0 << LP4_CA_ODT_SHIFT) | 99 (LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTEN_SHIFT) | 100 (LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) | 101 (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) | 102 (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT), 103/* odt enable freq */ 104(333 << PHY_LP4_ODT_EN_FREQ_SHIFT) | (333 << LP4_DQ_ODT_EN_FREQ_SHIFT), 105/* slew rate when odt enable */ 106(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | 107 (0xf << PHY_CLK_SR_SHIFT), 108/* slew ratee when odt disable */ 109(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | 110 (0xf << PHY_CLK_SR_SHIFT), 111/* ca odt en freq */ 112(333 << LP4_CA_ODT_EN_FREQ_SHIFT), 113/* cs drv info and ca odt info */ 114(0 << PHY_LP4_CS_DRV_ODTEN_SHIFT) | 115 (0 << PHY_LP4_CS_DRV_ODTOFF_SHIFT) | 116 (0 << LP4_ODTE_CK_SHIFT) | (0 << LP4_ODTE_CS_EN_SHIFT) | 117 (0 << LP4_ODTD_CA_EN_SHIFT), 118/* vref info when odt enable */ 119(200 << PHY_LP4_DQ_VREF_SHIFT) | (420 << LP4_DQ_VREF_SHIFT) | 120 (420 << LP4_CA_VREF_SHIFT), 121/* vref info when odt disable */ 122(420 << PHY_LP4_DQ_VREF_SHIFT) | (420 << LP4_DQ_VREF_SHIFT) | 123 (420 << LP4_CA_VREF_SHIFT), 124/* ddr4 map << 0 | ddr3 map << 24 */ 125((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) | 126 (0 << 8) | (0 << 16) | 127 (((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) << 24), 128/* lp3 map << 16 | lp4 map << 24 */ 129/* lp4 should equal to 0xc9 */ 130(((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0)) << 16) | 131 (((0x3 << 6) | (0x0 << 4) | (0x2 << 2) | (0x1 << 0)) << 24), 132/* lp3 dq0-7 map */ 133(2 << 0) | (6 << 4) | (4 << 8) | (0 << 12) | (3 << 16) | (7 << 20) | 134 ( 5 << 24) | (1 << 28), 135/* lp2 dq0-7 map */ 1360, 137/* ddr4 dq map */ 138/* cs0 dq0-15 */ 139 ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | 140 ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) | 141 ((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) | 142 ((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24), 143/* cs0 dq16-31 */ 144 ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) | 145 ((1 << 0 | 3 << 2 | 3 << 4 | 1 << 6) << 8) | 146 ((0 << 0 | 0 << 2 | 1 << 4 | 3 << 6) << 16) | 147 ((1 << 0 | 3 << 2 | 2 << 4 | 2 << 6) << 24), 148/* cs1 dq0-15 */ 149 ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | 150 ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 8) | 151 ((2 << 0 | 2 << 2 | 1 << 4 | 3 << 6) << 16) | 152 ((1 << 0 | 3 << 2 | 0 << 4 | 0 << 6) << 24), 153/* cs1 dq16-31 */ 154 ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 0) | 155 ((1 << 0 | 3 << 2 | 3 << 4 | 1 << 6) << 8) | 156 ((0 << 0 | 0 << 2 | 1 << 4 | 3 << 6) << 16) | 157 ((1 << 0 | 3 << 2 | 2 << 4 | 2 << 6) << 24), 158 159/* lpddr4x */ 160(1056 << DDR_FREQ_F0_SHIFT) | (328 << DDR_FREQ_F1_SHIFT), 161(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT), 162(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT), 163 164/* drv when odt on */ 165(38 << PHY_DQ_DRV_SHIFT) | (38 << PHY_CA_DRV_SHIFT) | 166 (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), 167/* drv when odt off */ 168(38 << PHY_DQ_DRV_SHIFT) | (38 << PHY_CA_DRV_SHIFT) | 169 (38 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT), 170/* odt info and PU-cal info */ 171(48 << DRAM_ODT_SHIFT) | (60 << PHY_ODT_SHIFT) | 172 (120 << LP4_CA_ODT_SHIFT) | 173 (LPDDR4X_VDDQ_0_6 << LP4_DRV_PU_CAL_ODTEN_SHIFT) | 174 (LPDDR4X_VDDQ_0_6 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) | 175 (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) | 176 (0 << PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT), 177/* odt enable freq */ 178(0 << PHY_LP4_ODT_EN_FREQ_SHIFT) | (0 << LP4_DQ_ODT_EN_FREQ_SHIFT), 179/* slew rate when odt enable */ 180(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | 181 (0xf << PHY_CLK_SR_SHIFT), 182/* slew ratee when odt disable */ 183(0xf << PHY_DQ_SR_SHIFT) | (0xf << PHY_CA_SR_SHIFT) | 184 (0xf << PHY_CLK_SR_SHIFT), 185/* ca odt en freq */ 186(333 << LP4_CA_ODT_EN_FREQ_SHIFT), 187/* cs drv info and ca odt info */ 188(0 << PHY_LP4_CS_DRV_ODTEN_SHIFT) | 189 (0 << PHY_LP4_CS_DRV_ODTOFF_SHIFT) | 190 (0 << LP4_ODTE_CK_SHIFT) | (0 << LP4_ODTE_CS_EN_SHIFT) | 191 (0 << LP4_ODTD_CA_EN_SHIFT), 192/* vref info when odt enable, phy vddq=1.1V, lp4x vddq=0.6V */ 193(153 << PHY_LP4_DQ_VREF_SHIFT) | (515 << LP4_DQ_VREF_SHIFT) | 194 (629 << LP4_CA_VREF_SHIFT), 195/* vref info when odt disable */ 196(153 << PHY_LP4_DQ_VREF_SHIFT) | (629 << LP4_DQ_VREF_SHIFT) | 197 (629 << LP4_CA_VREF_SHIFT), 198