1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <log.h> 9#include <dm/pinctrl.h> 10#include <regmap.h> 11#include <syscon.h> 12 13#include "pinctrl-rockchip.h" 14 15static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 16{ 17 struct rockchip_pinctrl_priv *priv = bank->priv; 18 int iomux_num = (pin / 8); 19 struct regmap *regmap; 20 int reg, ret, mask, mux_type; 21 u8 bit; 22 u32 data; 23 24 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 25 ? priv->regmap_pmu : priv->regmap_base; 26 27 /* get basic quadrupel of mux registers and the correct reg inside */ 28 mux_type = bank->iomux[iomux_num].type; 29 reg = bank->iomux[iomux_num].offset; 30 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 31 32 data = (mask << (bit + 16)); 33 data |= (mux & mask) << bit; 34 ret = regmap_write(regmap, reg, data); 35 36 return ret; 37} 38 39#define RK3368_PULL_GRF_OFFSET 0x100 40#define RK3368_PULL_PMU_OFFSET 0x10 41 42static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 43 int pin_num, struct regmap **regmap, 44 int *reg, u8 *bit) 45{ 46 struct rockchip_pinctrl_priv *priv = bank->priv; 47 48 /* The first 32 pins of the first bank are located in PMU */ 49 if (bank->bank_num == 0) { 50 *regmap = priv->regmap_pmu; 51 *reg = RK3368_PULL_PMU_OFFSET; 52 } else { 53 *regmap = priv->regmap_base; 54 *reg = RK3368_PULL_GRF_OFFSET; 55 56 /* correct the offset, as we're starting with the 2nd bank */ 57 *reg -= 0x10; 58 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 59 } 60 61 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 62 63 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 64 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 65} 66 67static int rk3368_set_pull(struct rockchip_pin_bank *bank, 68 int pin_num, int pull) 69{ 70 struct regmap *regmap; 71 int reg, ret; 72 u8 bit, type; 73 u32 data; 74 75 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 76 return -ENOTSUPP; 77 78 rk3368_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 79 type = bank->pull_type[pin_num / 8]; 80 ret = rockchip_translate_pull_value(type, pull); 81 if (ret < 0) { 82 debug("unsupported pull setting %d\n", pull); 83 return ret; 84 } 85 86 /* enable the write to the equivalent lower bits */ 87 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 88 data |= (ret << bit); 89 ret = regmap_write(regmap, reg, data); 90 91 return ret; 92} 93 94#define RK3368_DRV_PMU_OFFSET 0x20 95#define RK3368_DRV_GRF_OFFSET 0x200 96 97static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 98 int pin_num, struct regmap **regmap, 99 int *reg, u8 *bit) 100{ 101 struct rockchip_pinctrl_priv *priv = bank->priv; 102 103 /* The first 32 pins of the first bank are located in PMU */ 104 if (bank->bank_num == 0) { 105 *regmap = priv->regmap_pmu; 106 *reg = RK3368_DRV_PMU_OFFSET; 107 } else { 108 *regmap = priv->regmap_base; 109 *reg = RK3368_DRV_GRF_OFFSET; 110 111 /* correct the offset, as we're starting with the 2nd bank */ 112 *reg -= 0x10; 113 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 114 } 115 116 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 117 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 118 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 119} 120 121static int rk3368_set_drive(struct rockchip_pin_bank *bank, 122 int pin_num, int strength) 123{ 124 struct regmap *regmap; 125 int reg, ret; 126 u32 data; 127 u8 bit; 128 int type = bank->drv[pin_num / 8].drv_type; 129 130 rk3368_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 131 ret = rockchip_translate_drive_value(type, strength); 132 if (ret < 0) { 133 debug("unsupported driver strength %d\n", strength); 134 return ret; 135 } 136 137 /* enable the write to the equivalent lower bits */ 138 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); 139 data |= (ret << bit); 140 ret = regmap_write(regmap, reg, data); 141 142 return ret; 143} 144 145static struct rockchip_pin_bank rk3368_pin_banks[] = { 146 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 147 IOMUX_SOURCE_PMU, 148 IOMUX_SOURCE_PMU, 149 IOMUX_SOURCE_PMU 150 ), 151 PIN_BANK(1, 32, "gpio1"), 152 PIN_BANK(2, 32, "gpio2"), 153 PIN_BANK(3, 32, "gpio3"), 154}; 155 156static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 157 .pin_banks = rk3368_pin_banks, 158 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 159 .grf_mux_offset = 0x0, 160 .pmu_mux_offset = 0x0, 161 .set_mux = rk3368_set_mux, 162 .set_pull = rk3368_set_pull, 163 .set_drive = rk3368_set_drive, 164}; 165 166static const struct udevice_id rk3368_pinctrl_ids[] = { 167 { 168 .compatible = "rockchip,rk3368-pinctrl", 169 .data = (ulong)&rk3368_pin_ctrl 170 }, 171 { } 172}; 173 174U_BOOT_DRIVER(rockchip_rk3368_pinctrl) = { 175 .name = "rockchip_rk3368_pinctrl", 176 .id = UCLASS_PINCTRL, 177 .of_match = rk3368_pinctrl_ids, 178 .priv_auto = sizeof(struct rockchip_pinctrl_priv), 179 .ops = &rockchip_pinctrl_ops, 180#if CONFIG_IS_ENABLED(OF_REAL) 181 .bind = dm_scan_fdt_dev, 182#endif 183 .probe = rockchip_pinctrl_probe, 184}; 185