1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
11#include <linux/bitops.h>
12
13#include "pinctrl-rockchip.h"
14
15static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
16{
17	struct rockchip_pinctrl_priv *priv = bank->priv;
18	int iomux_num = (pin / 8);
19	struct regmap *regmap;
20	int reg, ret, mask, mux_type;
21	u8 bit;
22	u32 data;
23
24	regmap = priv->regmap_base;
25
26	/* get basic quadrupel of mux registers and the correct reg inside */
27	mux_type = bank->iomux[iomux_num].type;
28	reg = bank->iomux[iomux_num].offset;
29	reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
30
31	data = (mask << (bit + 16));
32	data |= (mux & mask) << bit;
33	ret = regmap_write(regmap, reg, data);
34
35	return ret;
36}
37
38#define RK3066_PULL_OFFSET		0x118
39#define RK3066_PULL_PINS_PER_REG	16
40#define RK3066_PULL_BANK_STRIDE		8
41
42static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
43						 int pin_num, struct regmap **regmap,
44						 int *reg, u8 *bit)
45{
46	struct rockchip_pinctrl_priv *priv = bank->priv;
47
48	*regmap = priv->regmap_base;
49	*reg = RK3066_PULL_OFFSET;
50	*reg += bank->bank_num * RK3066_PULL_BANK_STRIDE;
51	*reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4;
52
53	*bit = pin_num % RK3066_PULL_PINS_PER_REG;
54};
55
56static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank,
57				   int pin_num, int pull)
58{
59	struct regmap *regmap;
60	int reg, ret;
61	u8 bit;
62	u32 data;
63
64	if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
65	    pull != PIN_CONFIG_BIAS_DISABLE)
66		return -EOPNOTSUPP;
67
68	rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
69	data = BIT(bit + 16);
70	if (pull == PIN_CONFIG_BIAS_DISABLE)
71		data |= BIT(bit);
72	ret = regmap_write(regmap, reg, data);
73
74	return ret;
75}
76
77static struct rockchip_pin_bank rk3066_pin_banks[] = {
78	PIN_BANK(0, 32, "gpio0"),
79	PIN_BANK(1, 32, "gpio1"),
80	PIN_BANK(2, 32, "gpio2"),
81	PIN_BANK(3, 32, "gpio3"),
82	PIN_BANK(4, 32, "gpio4"),
83	PIN_BANK(6, 16, "gpio6"),
84};
85
86static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
87	.pin_banks		= rk3066_pin_banks,
88	.nr_banks		= ARRAY_SIZE(rk3066_pin_banks),
89	.grf_mux_offset		= 0xa8,
90	.set_mux		= rk3066_pinctrl_set_mux,
91	.set_pull		= rk3066_pinctrl_set_pull,
92};
93
94static const struct udevice_id rk3066_pinctrl_ids[] = {
95	{
96		.compatible = "rockchip,rk3066a-pinctrl",
97		.data = (ulong)&rk3066_pin_ctrl
98	},
99	{}
100};
101
102U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
103	.name		= "rockchip_rk3066a_pinctrl",
104	.id		= UCLASS_PINCTRL,
105	.ops		= &rockchip_pinctrl_ops,
106	.probe		= rockchip_pinctrl_probe,
107#if CONFIG_IS_ENABLED(OF_REAL)
108	.bind		= dm_scan_fdt_dev,
109#endif
110	.of_match	= rk3066_pinctrl_ids,
111	.priv_auto	= sizeof(struct rockchip_pinctrl_priv),
112};
113