1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch> 4 * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it> 5 */ 6 7#include <common.h> 8#include <mapmem.h> 9#include <dm.h> 10#include <dm/device_compat.h> 11#include <dm/devres.h> 12#include <dm/of_access.h> 13#include <dm/pinctrl.h> 14#include <linux/libfdt.h> 15#include <linux/list.h> 16#include <asm/io.h> 17#include <sort.h> 18 19/** 20 * struct single_pdata - platform data 21 * @base: first configuration register 22 * @offset: index of last configuration register 23 * @mask: configuration-value mask bits 24 * @width: configuration register bit width 25 * @bits_per_mux: true if one register controls more than one pin 26 */ 27struct single_pdata { 28 void *base; 29 int offset; 30 u32 mask; 31 u32 width; 32 u32 args_count; 33 bool bits_per_mux; 34}; 35 36/** 37 * struct single_func - pinctrl function 38 * @node: list node 39 * @name: pinctrl function name 40 * @npins: number of entries in pins array 41 * @pins: pins array 42 */ 43struct single_func { 44 struct list_head node; 45 const char *name; 46 unsigned int npins; 47 unsigned int *pins; 48}; 49 50/** 51 * struct single_gpiofunc_range - pin ranges with same mux value of gpio fun 52 * @offset: offset base of pins 53 * @npins: number pins with the same mux value of gpio function 54 * @gpiofunc: mux value of gpio function 55 * @node: list node 56 */ 57struct single_gpiofunc_range { 58 u32 offset; 59 u32 npins; 60 u32 gpiofunc; 61 struct list_head node; 62}; 63 64/** 65 * struct single_priv - private data 66 * @bits_per_pin: number of bits per pin 67 * @npins: number of selectable pins 68 * @pin_name: temporary buffer to store the pin name 69 * @functions: list pin functions 70 * @gpiofuncs: list gpio functions 71 */ 72struct single_priv { 73#if (IS_ENABLED(CONFIG_SANDBOX)) 74 u32 *sandbox_regs; 75#endif 76 unsigned int bits_per_pin; 77 unsigned int npins; 78 char pin_name[PINNAME_SIZE]; 79 struct list_head functions; 80 struct list_head gpiofuncs; 81}; 82 83/** 84 * struct single_fdt_bits_cfg - pin configuration 85 * 86 * This structure is used for the pin configuration parameters in case 87 * the register controls more than one pin. 88 * 89 * @reg: configuration register offset 90 * @val: configuration register value 91 * @mask: configuration register mask 92 */ 93struct single_fdt_bits_cfg { 94 fdt32_t reg; 95 fdt32_t val; 96 fdt32_t mask; 97}; 98 99#if (!IS_ENABLED(CONFIG_SANDBOX)) 100 101static unsigned int single_read(struct udevice *dev, void *reg) 102{ 103 struct single_pdata *pdata = dev_get_plat(dev); 104 105 switch (pdata->width) { 106 case 8: 107 return readb(reg); 108 case 16: 109 return readw(reg); 110 default: /* 32 bits */ 111 return readl(reg); 112 } 113 114 return readb(reg); 115} 116 117static void single_write(struct udevice *dev, unsigned int val, void *reg) 118{ 119 struct single_pdata *pdata = dev_get_plat(dev); 120 121 switch (pdata->width) { 122 case 8: 123 writeb(val, reg); 124 break; 125 case 16: 126 writew(val, reg); 127 break; 128 default: /* 32 bits */ 129 writel(val, reg); 130 } 131} 132 133#else /* CONFIG_SANDBOX */ 134 135static unsigned int single_read(struct udevice *dev, void *reg) 136{ 137 struct single_priv *priv = dev_get_priv(dev); 138 139 return priv->sandbox_regs[map_to_sysmem(reg)]; 140} 141 142static void single_write(struct udevice *dev, unsigned int val, void *reg) 143{ 144 struct single_priv *priv = dev_get_priv(dev); 145 146 priv->sandbox_regs[map_to_sysmem(reg)] = val; 147} 148 149#endif /* CONFIG_SANDBOX */ 150 151/** 152 * single_get_pin_by_offset() - get a pin based on the register offset 153 * @dev: single driver instance 154 * @offset: register offset from the base 155 */ 156static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset) 157{ 158 struct single_pdata *pdata = dev_get_plat(dev); 159 struct single_priv *priv = dev_get_priv(dev); 160 161 if (offset > pdata->offset) { 162 dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n", 163 offset, pdata->offset); 164 return -EINVAL; 165 } 166 167 if (pdata->bits_per_mux) 168 return (offset * BITS_PER_BYTE) / priv->bits_per_pin; 169 170 return offset / (pdata->width / BITS_PER_BYTE); 171} 172 173static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin) 174{ 175 struct single_pdata *pdata = dev_get_plat(dev); 176 struct single_priv *priv = dev_get_priv(dev); 177 unsigned int mux_bytes; 178 179 if (pin >= priv->npins) 180 return -EINVAL; 181 182 mux_bytes = pdata->width / BITS_PER_BYTE; 183 if (pdata->bits_per_mux) { 184 int byte_num; 185 186 byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE; 187 return (byte_num / mux_bytes) * mux_bytes; 188 } 189 190 return pin * mux_bytes; 191} 192 193static const char *single_get_pin_function(struct udevice *dev, 194 unsigned int pin) 195{ 196 struct single_priv *priv = dev_get_priv(dev); 197 struct single_func *func; 198 int i; 199 200 list_for_each_entry(func, &priv->functions, node) { 201 for (i = 0; i < func->npins; i++) { 202 if (pin == func->pins[i]) 203 return func->name; 204 205 if (pin < func->pins[i]) 206 break; 207 } 208 } 209 210 return NULL; 211} 212 213static int single_get_pin_muxing(struct udevice *dev, unsigned int pin, 214 char *buf, int size) 215{ 216 struct single_pdata *pdata = dev_get_plat(dev); 217 struct single_priv *priv = dev_get_priv(dev); 218 phys_addr_t phys_reg; 219 void *reg; 220 const char *fname; 221 unsigned int val; 222 int offset, pin_shift = 0; 223 224 offset = single_get_offset_by_pin(dev, pin); 225 if (offset < 0) 226 return offset; 227 228 reg = pdata->base + offset; 229 val = single_read(dev, reg); 230 231 phys_reg = map_to_sysmem(reg); 232 233 if (pdata->bits_per_mux) 234 pin_shift = pin % (pdata->width / priv->bits_per_pin) * 235 priv->bits_per_pin; 236 237 val &= (pdata->mask << pin_shift); 238 fname = single_get_pin_function(dev, pin); 239 snprintf(buf, size, "%pa 0x%08x %s", &phys_reg, val, 240 fname ? fname : "UNCLAIMED"); 241 return 0; 242} 243 244static int single_request(struct udevice *dev, int pin, int flags) 245{ 246 struct single_priv *priv = dev_get_priv(dev); 247 struct single_pdata *pdata = dev_get_plat(dev); 248 struct single_gpiofunc_range *frange = NULL; 249 struct list_head *pos, *tmp; 250 void *reg; 251 int mux_bytes = 0; 252 u32 data; 253 254 /* If function mask is null, needn't enable it. */ 255 if (!pdata->mask) 256 return -ENOTSUPP; 257 258 list_for_each_safe(pos, tmp, &priv->gpiofuncs) { 259 frange = list_entry(pos, struct single_gpiofunc_range, node); 260 if ((pin >= frange->offset + frange->npins) || 261 pin < frange->offset) 262 continue; 263 264 mux_bytes = pdata->width / BITS_PER_BYTE; 265 reg = pdata->base + pin * mux_bytes; 266 267 data = single_read(dev, reg); 268 data &= ~pdata->mask; 269 data |= frange->gpiofunc; 270 single_write(dev, data, reg); 271 break; 272 } 273 274 return 0; 275} 276 277static struct single_func *single_allocate_function(struct udevice *dev, 278 unsigned int group_pins) 279{ 280 struct single_func *func; 281 282 func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL); 283 if (!func) 284 return ERR_PTR(-ENOMEM); 285 286 func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins, 287 GFP_KERNEL); 288 if (!func->pins) 289 return ERR_PTR(-ENOMEM); 290 291 return func; 292} 293 294static int single_pin_compare(const void *s1, const void *s2) 295{ 296 int pin1 = *(const unsigned int *)s1; 297 int pin2 = *(const unsigned int *)s2; 298 299 return pin1 - pin2; 300} 301 302/** 303 * single_configure_pins() - Configure pins based on FDT data 304 * 305 * @dev: Pointer to single pin configuration device which is the parent of 306 * the pins node holding the pin configuration data. 307 * @pins: Pointer to the first element of an array of register/value pairs 308 * of type 'u32'. Each such pair describes the pin to be configured 309 * and the value to be used for configuration. 310 * The value can either be a simple value if #pinctrl-cells = 1 311 * or a configuration value and a pin mux mode value if it is 2 312 * This pointer points to a 'pinctrl-single,pins' property in the 313 * device-tree. 314 * @size: Size of the 'pins' array in bytes. 315 * The number of cells in the array therefore equals to 316 * 'size / sizeof(u32)'. 317 * @fname: Function name. 318 */ 319static int single_configure_pins(struct udevice *dev, 320 const u32 *pins, 321 int size, const char *fname) 322{ 323 struct single_pdata *pdata = dev_get_plat(dev); 324 struct single_priv *priv = dev_get_priv(dev); 325 int stride = pdata->args_count + 1; 326 int n, pin, count = size / sizeof(u32); 327 struct single_func *func; 328 void *reg; 329 u32 offset, val, mux; 330 331 /* If function mask is null, needn't enable it. */ 332 if (!pdata->mask) 333 return 0; 334 335 func = single_allocate_function(dev, count); 336 if (IS_ERR(func)) 337 return PTR_ERR(func); 338 339 func->name = fname; 340 func->npins = 0; 341 for (n = 0; n < count; n += stride) { 342 offset = fdt32_to_cpu(pins[n]); 343 if (offset > pdata->offset) { 344 dev_err(dev, " invalid register offset 0x%x\n", 345 offset); 346 continue; 347 } 348 349 /* if the pinctrl-cells is 2 then the second cell contains the mux */ 350 if (stride == 3) 351 mux = fdt32_to_cpu(pins[n + 2]); 352 else 353 mux = 0; 354 355 reg = pdata->base + offset; 356 val = (fdt32_to_cpu(pins[n + 1]) | mux) & pdata->mask; 357 pin = single_get_pin_by_offset(dev, offset); 358 if (pin < 0) { 359 dev_err(dev, " failed to get pin by offset %x\n", 360 offset); 361 continue; 362 } 363 364 single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val, 365 reg); 366 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); 367 func->pins[func->npins] = pin; 368 func->npins++; 369 } 370 371 qsort(func->pins, func->npins, sizeof(func->pins[0]), 372 single_pin_compare); 373 list_add(&func->node, &priv->functions); 374 return 0; 375} 376 377static int single_configure_bits(struct udevice *dev, 378 const struct single_fdt_bits_cfg *pins, 379 int size, const char *fname) 380{ 381 struct single_pdata *pdata = dev_get_plat(dev); 382 struct single_priv *priv = dev_get_priv(dev); 383 int n, pin, count = size / sizeof(struct single_fdt_bits_cfg); 384 int npins_in_reg, pin_num_from_lsb; 385 struct single_func *func; 386 void *reg; 387 u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask; 388 389 /* If function mask is null, needn't enable it. */ 390 if (!pdata->mask) 391 return 0; 392 393 npins_in_reg = pdata->width / priv->bits_per_pin; 394 func = single_allocate_function(dev, count * npins_in_reg); 395 if (IS_ERR(func)) 396 return PTR_ERR(func); 397 398 func->name = fname; 399 func->npins = 0; 400 for (n = 0; n < count; n++, pins++) { 401 offset = fdt32_to_cpu(pins->reg); 402 if (offset > pdata->offset) { 403 dev_dbg(dev, " invalid register offset 0x%x\n", 404 offset); 405 continue; 406 } 407 408 reg = pdata->base + offset; 409 410 pin = single_get_pin_by_offset(dev, offset); 411 if (pin < 0) { 412 dev_err(dev, " failed to get pin by offset 0x%pa\n", 413 ®); 414 continue; 415 } 416 417 mask = fdt32_to_cpu(pins->mask); 418 val = fdt32_to_cpu(pins->val) & mask; 419 single_write(dev, (single_read(dev, reg) & ~mask) | val, reg); 420 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); 421 422 while (mask) { 423 bit_pos = __ffs(mask); 424 pin_num_from_lsb = bit_pos / priv->bits_per_pin; 425 mask_pos = pdata->mask << bit_pos; 426 val_pos = val & mask_pos; 427 submask = mask & mask_pos; 428 429 if ((mask & mask_pos) == 0) { 430 dev_err(dev, "Invalid mask at 0x%x\n", offset); 431 break; 432 } 433 434 mask &= ~mask_pos; 435 436 if (submask != mask_pos) { 437 dev_warn(dev, 438 "Invalid submask 0x%x at 0x%x\n", 439 submask, offset); 440 continue; 441 } 442 443 func->pins[func->npins] = pin + pin_num_from_lsb; 444 func->npins++; 445 } 446 } 447 448 qsort(func->pins, func->npins, sizeof(func->pins[0]), 449 single_pin_compare); 450 list_add(&func->node, &priv->functions); 451 return 0; 452} 453static int single_set_state(struct udevice *dev, 454 struct udevice *config) 455{ 456 const u32 *prop; 457 const struct single_fdt_bits_cfg *prop_bits; 458 int len; 459 460 prop = dev_read_prop(config, "pinctrl-single,pins", &len); 461 462 if (prop) { 463 dev_dbg(dev, "configuring pins for %s\n", config->name); 464 if (len % sizeof(u32)) { 465 dev_dbg(dev, " invalid pin configuration in fdt\n"); 466 return -FDT_ERR_BADSTRUCTURE; 467 } 468 single_configure_pins(dev, prop, len, config->name); 469 return 0; 470 } 471 472 /* pinctrl-single,pins not found so check for pinctrl-single,bits */ 473 prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len); 474 if (prop_bits) { 475 dev_dbg(dev, "configuring pins for %s\n", config->name); 476 if (len % sizeof(struct single_fdt_bits_cfg)) { 477 dev_dbg(dev, " invalid bits configuration in fdt\n"); 478 return -FDT_ERR_BADSTRUCTURE; 479 } 480 single_configure_bits(dev, prop_bits, len, config->name); 481 return 0; 482 } 483 484 /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */ 485 return len; 486} 487 488static const char *single_get_pin_name(struct udevice *dev, 489 unsigned int selector) 490{ 491 struct single_priv *priv = dev_get_priv(dev); 492 493 if (selector >= priv->npins) 494 snprintf(priv->pin_name, PINNAME_SIZE, "Error"); 495 else 496 snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector); 497 498 return priv->pin_name; 499} 500 501static int single_get_pins_count(struct udevice *dev) 502{ 503 struct single_priv *priv = dev_get_priv(dev); 504 505 return priv->npins; 506} 507 508static int single_add_gpio_func(struct udevice *dev) 509{ 510 struct single_priv *priv = dev_get_priv(dev); 511 const char *propname = "pinctrl-single,gpio-range"; 512 const char *cellname = "#pinctrl-single,gpio-range-cells"; 513 struct single_gpiofunc_range *range; 514 struct ofnode_phandle_args gpiospec; 515 int ret, i; 516 517 for (i = 0; ; i++) { 518 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), propname, 519 cellname, 0, i, &gpiospec); 520 /* Do not treat it as error. Only treat it as end condition. */ 521 if (ret) { 522 ret = 0; 523 break; 524 } 525 range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL); 526 if (!range) { 527 ret = -ENOMEM; 528 break; 529 } 530 range->offset = gpiospec.args[0]; 531 range->npins = gpiospec.args[1]; 532 range->gpiofunc = gpiospec.args[2]; 533 list_add_tail(&range->node, &priv->gpiofuncs); 534 } 535 return ret; 536} 537 538static int single_probe(struct udevice *dev) 539{ 540 struct single_pdata *pdata = dev_get_plat(dev); 541 struct single_priv *priv = dev_get_priv(dev); 542 u32 size; 543 544 INIT_LIST_HEAD(&priv->functions); 545 INIT_LIST_HEAD(&priv->gpiofuncs); 546 547 size = pdata->offset + pdata->width / BITS_PER_BYTE; 548 #if (IS_ENABLED(CONFIG_SANDBOX)) 549 priv->sandbox_regs = 550 devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs), 551 GFP_KERNEL); 552 if (!priv->sandbox_regs) 553 return -ENOMEM; 554 #endif 555 556 /* looks like a possible divide by 0, but data->width avoids this */ 557 priv->npins = size / (pdata->width / BITS_PER_BYTE); 558 if (pdata->bits_per_mux) { 559 if (!pdata->mask) { 560 dev_err(dev, "function mask needs to be non-zero\n"); 561 return -EINVAL; 562 } 563 564 priv->bits_per_pin = fls(pdata->mask); 565 priv->npins *= (pdata->width / priv->bits_per_pin); 566 } 567 568 if (single_add_gpio_func(dev)) 569 dev_dbg(dev, "gpio functions are not added\n"); 570 571 dev_dbg(dev, "%d pins\n", priv->npins); 572 return 0; 573} 574 575static int single_of_to_plat(struct udevice *dev) 576{ 577 void *addr; 578 fdt_size_t size; 579 struct single_pdata *pdata = dev_get_plat(dev); 580 int ret; 581 582 ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width); 583 if (ret) { 584 dev_err(dev, "missing register width\n"); 585 return ret; 586 } 587 588 switch (pdata->width) { 589 case 8: 590 case 16: 591 case 32: 592 break; 593 default: 594 dev_err(dev, "wrong register width\n"); 595 return -EINVAL; 596 } 597 598 addr = dev_read_addr_size_index_ptr(dev, 0, &size); 599 if (!addr) { 600 dev_err(dev, "failed to get base register address\n"); 601 return -EINVAL; 602 } 603 604 pdata->offset = size - pdata->width / BITS_PER_BYTE; 605 pdata->base = addr; 606 607 ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask); 608 if (ret) { 609 pdata->mask = 0; 610 dev_warn(dev, "missing function register mask\n"); 611 } 612 613 pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux"); 614 615 /* If no pinctrl-cells is present, default to old style of 2 cells with 616 * bits per mux and 1 cell otherwise. 617 */ 618 ret = dev_read_u32(dev, "#pinctrl-cells", &pdata->args_count); 619 if (ret) 620 pdata->args_count = pdata->bits_per_mux ? 2 : 1; 621 622 return 0; 623} 624 625const struct pinctrl_ops single_pinctrl_ops = { 626 .get_pins_count = single_get_pins_count, 627 .get_pin_name = single_get_pin_name, 628 .set_state = single_set_state, 629 .get_pin_muxing = single_get_pin_muxing, 630 .request = single_request, 631}; 632 633static const struct udevice_id single_pinctrl_match[] = { 634 { .compatible = "pinctrl-single" }, 635 { /* sentinel */ } 636}; 637 638U_BOOT_DRIVER(single_pinctrl) = { 639 .name = "single-pinctrl", 640 .id = UCLASS_PINCTRL, 641 .of_match = single_pinctrl_match, 642 .ops = &single_pinctrl_ops, 643 .plat_auto = sizeof(struct single_pdata), 644 .priv_auto = sizeof(struct single_priv), 645 .of_to_plat = single_of_to_plat, 646 .probe = single_probe, 647}; 648