1// SPDX-License-Identifier: GPL-2.0+ 2/** 3 * sni_ave.c - Socionext UniPhier AVE ethernet driver 4 * Copyright 2016-2018 Socionext inc. 5 */ 6 7#include <clk.h> 8#include <cpu_func.h> 9#include <dm.h> 10#include <fdt_support.h> 11#include <log.h> 12#include <malloc.h> 13#include <miiphy.h> 14#include <net.h> 15#include <regmap.h> 16#include <reset.h> 17#include <syscon.h> 18#include <asm/cache.h> 19#include <asm/global_data.h> 20#include <dm/device_compat.h> 21#include <linux/bitops.h> 22#include <linux/delay.h> 23#include <linux/err.h> 24#include <linux/io.h> 25#include <linux/iopoll.h> 26#include <linux/printk.h> 27 28#define AVE_GRST_DELAY_MSEC 40 29#define AVE_MIN_XMITSIZE 60 30#define AVE_SEND_TIMEOUT_COUNT 1000 31#define AVE_MDIO_TIMEOUT_USEC 10000 32#define AVE_HALT_TIMEOUT_USEC 10000 33 34/* General Register Group */ 35#define AVE_IDR 0x000 /* ID */ 36#define AVE_VR 0x004 /* Version */ 37#define AVE_GRR 0x008 /* Global Reset */ 38#define AVE_CFGR 0x00c /* Configuration */ 39 40/* Interrupt Register Group */ 41#define AVE_GIMR 0x100 /* Global Interrupt Mask */ 42#define AVE_GISR 0x104 /* Global Interrupt Status */ 43 44/* MAC Register Group */ 45#define AVE_TXCR 0x200 /* TX Setup */ 46#define AVE_RXCR 0x204 /* RX Setup */ 47#define AVE_RXMAC1R 0x208 /* MAC address (lower) */ 48#define AVE_RXMAC2R 0x20c /* MAC address (upper) */ 49#define AVE_MDIOCTR 0x214 /* MDIO Control */ 50#define AVE_MDIOAR 0x218 /* MDIO Address */ 51#define AVE_MDIOWDR 0x21c /* MDIO Data */ 52#define AVE_MDIOSR 0x220 /* MDIO Status */ 53#define AVE_MDIORDR 0x224 /* MDIO Rd Data */ 54 55/* Descriptor Control Register Group */ 56#define AVE_DESCC 0x300 /* Descriptor Control */ 57#define AVE_TXDC 0x304 /* TX Descriptor Configuration */ 58#define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */ 59#define AVE_IIRQC 0x34c /* Interval IRQ Control */ 60 61/* 64bit descriptor memory */ 62#define AVE_DESC_SIZE_64 12 /* Descriptor Size */ 63#define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ 64#define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ 65 66/* 32bit descriptor memory */ 67#define AVE_DESC_SIZE_32 8 /* Descriptor Size */ 68#define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ 69#define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ 70 71/* RMII Bridge Register Group */ 72#define AVE_RSTCTRL 0x8028 /* Reset control */ 73#define AVE_RSTCTRL_RMIIRST BIT(16) 74#define AVE_LINKSEL 0x8034 /* Link speed setting */ 75#define AVE_LINKSEL_100M BIT(0) 76 77/* AVE_GRR */ 78#define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ 79#define AVE_GRR_GRST BIT(0) /* Reset all MAC */ 80 81/* AVE_CFGR */ 82#define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ 83 84/* AVE_GISR (common with GIMR) */ 85#define AVE_GIMR_CLR 0 86#define AVE_GISR_CLR GENMASK(31, 0) 87 88/* AVE_TXCR */ 89#define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ 90#define AVE_TXCR_TXSPD_1G BIT(17) 91#define AVE_TXCR_TXSPD_100 BIT(16) 92 93/* AVE_RXCR */ 94#define AVE_RXCR_RXEN BIT(30) /* Rx enable */ 95#define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ 96#define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ 97 98/* AVE_MDIOCTR */ 99#define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ 100#define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ 101 102/* AVE_MDIOSR */ 103#define AVE_MDIOSR_STS BIT(0) /* access status */ 104 105/* AVE_DESCC */ 106#define AVE_DESCC_RXDSTPSTS BIT(20) 107#define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ 108#define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */ 109#define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ 110 111/* AVE_TXDC/RXDC */ 112#define AVE_DESC_SIZE(priv, num) \ 113 ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \ 114 AVE_DESC_SIZE_32)) 115 116/* Command status for descriptor */ 117#define AVE_STS_OWN BIT(31) /* Descriptor ownership */ 118#define AVE_STS_OK BIT(27) /* Normal transmit */ 119#define AVE_STS_1ST BIT(26) /* Head of buffer chain */ 120#define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ 121#define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) 122#define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) 123 124#define AVE_DESC_OFS_CMDSTS 0 125#define AVE_DESC_OFS_ADDRL 4 126#define AVE_DESC_OFS_ADDRU 8 127 128/* Parameter for ethernet frame */ 129#define AVE_RXCR_MTU 1518 130 131/* SG */ 132#define SG_ETPINMODE 0x540 133#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ 134#define SG_ETPINMODE_RMII(ins) BIT(ins) 135 136#define AVE_MAX_CLKS 4 137#define AVE_MAX_RSTS 2 138 139enum desc_id { 140 AVE_DESCID_TX, 141 AVE_DESCID_RX, 142}; 143 144struct ave_private { 145 phys_addr_t iobase; 146 unsigned int nclks; 147 struct clk clk[AVE_MAX_CLKS]; 148 unsigned int nrsts; 149 struct reset_ctl rst[AVE_MAX_RSTS]; 150 struct regmap *regmap; 151 unsigned int regmap_arg; 152 153 struct mii_dev *bus; 154 struct phy_device *phydev; 155 int phy_mode; 156 int max_speed; 157 158 int rx_pos; 159 int rx_siz; 160 int rx_off; 161 int tx_num; 162 163 u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN]; 164 void *tx_adj_buf; 165 166 const struct ave_soc_data *data; 167}; 168 169struct ave_soc_data { 170 bool is_desc_64bit; 171 const char *clock_names[AVE_MAX_CLKS]; 172 const char *reset_names[AVE_MAX_RSTS]; 173 int (*get_pinmode)(struct ave_private *priv); 174}; 175 176static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, 177 int offset) 178{ 179 int desc_size; 180 u32 addr; 181 182 if (priv->data->is_desc_64bit) { 183 desc_size = AVE_DESC_SIZE_64; 184 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; 185 } else { 186 desc_size = AVE_DESC_SIZE_32; 187 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; 188 } 189 190 addr += entry * desc_size + offset; 191 192 return readl(priv->iobase + addr); 193} 194 195static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, 196 int entry) 197{ 198 return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); 199} 200 201static void ave_desc_write(struct ave_private *priv, enum desc_id id, 202 int entry, int offset, u32 val) 203{ 204 int desc_size; 205 u32 addr; 206 207 if (priv->data->is_desc_64bit) { 208 desc_size = AVE_DESC_SIZE_64; 209 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; 210 } else { 211 desc_size = AVE_DESC_SIZE_32; 212 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; 213 } 214 215 addr += entry * desc_size + offset; 216 writel(val, priv->iobase + addr); 217} 218 219static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id, 220 int entry, u32 val) 221{ 222 ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val); 223} 224 225static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id, 226 int entry, uintptr_t paddr) 227{ 228 ave_desc_write(priv, id, entry, 229 AVE_DESC_OFS_ADDRL, lower_32_bits(paddr)); 230 if (priv->data->is_desc_64bit) 231 ave_desc_write(priv, id, entry, 232 AVE_DESC_OFS_ADDRU, upper_32_bits(paddr)); 233} 234 235static void ave_cache_invalidate(uintptr_t vaddr, int len) 236{ 237 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), 238 roundup(vaddr + len, ARCH_DMA_MINALIGN)); 239} 240 241static void ave_cache_flush(uintptr_t vaddr, int len) 242{ 243 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), 244 roundup(vaddr + len, ARCH_DMA_MINALIGN)); 245} 246 247static int ave_mdiobus_read(struct mii_dev *bus, 248 int phyid, int devad, int regnum) 249{ 250 struct ave_private *priv = bus->priv; 251 u32 mdioctl, mdiosr; 252 int ret; 253 254 /* write address */ 255 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); 256 257 /* read request */ 258 mdioctl = readl(priv->iobase + AVE_MDIOCTR); 259 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); 260 261 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, 262 !(mdiosr & AVE_MDIOSR_STS), 263 AVE_MDIO_TIMEOUT_USEC); 264 if (ret) { 265 pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n", 266 priv->phydev->dev->name, phyid, regnum); 267 return ret; 268 } 269 270 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); 271} 272 273static int ave_mdiobus_write(struct mii_dev *bus, 274 int phyid, int devad, int regnum, u16 val) 275{ 276 struct ave_private *priv = bus->priv; 277 u32 mdioctl, mdiosr; 278 int ret; 279 280 /* write address */ 281 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); 282 283 /* write data */ 284 writel(val, priv->iobase + AVE_MDIOWDR); 285 286 /* write request */ 287 mdioctl = readl(priv->iobase + AVE_MDIOCTR); 288 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, 289 priv->iobase + AVE_MDIOCTR); 290 291 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, 292 !(mdiosr & AVE_MDIOSR_STS), 293 AVE_MDIO_TIMEOUT_USEC); 294 if (ret) 295 pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n", 296 priv->phydev->dev->name, phyid, regnum); 297 298 return ret; 299} 300 301static int ave_adjust_link(struct ave_private *priv) 302{ 303 struct phy_device *phydev = priv->phydev; 304 struct eth_pdata *pdata = dev_get_plat(phydev->dev); 305 u32 val, txcr, rxcr, rxcr_org; 306 u16 rmt_adv = 0, lcl_adv = 0; 307 u8 cap; 308 309 /* set RGMII speed */ 310 val = readl(priv->iobase + AVE_TXCR); 311 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); 312 313 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) 314 val |= AVE_TXCR_TXSPD_1G; 315 else if (phydev->speed == SPEED_100) 316 val |= AVE_TXCR_TXSPD_100; 317 318 writel(val, priv->iobase + AVE_TXCR); 319 320 /* set RMII speed (100M/10M only) */ 321 if (!phy_interface_is_rgmii(phydev)) { 322 val = readl(priv->iobase + AVE_LINKSEL); 323 if (phydev->speed == SPEED_10) 324 val &= ~AVE_LINKSEL_100M; 325 else 326 val |= AVE_LINKSEL_100M; 327 writel(val, priv->iobase + AVE_LINKSEL); 328 } 329 330 /* check current RXCR/TXCR */ 331 rxcr = readl(priv->iobase + AVE_RXCR); 332 txcr = readl(priv->iobase + AVE_TXCR); 333 rxcr_org = rxcr; 334 335 if (phydev->duplex) { 336 rxcr |= AVE_RXCR_FDUPEN; 337 338 if (phydev->pause) 339 rmt_adv |= LPA_PAUSE_CAP; 340 if (phydev->asym_pause) 341 rmt_adv |= LPA_PAUSE_ASYM; 342 if (phydev->advertising & ADVERTISED_Pause) 343 lcl_adv |= ADVERTISE_PAUSE_CAP; 344 if (phydev->advertising & ADVERTISED_Asym_Pause) 345 lcl_adv |= ADVERTISE_PAUSE_ASYM; 346 347 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 348 if (cap & FLOW_CTRL_TX) 349 txcr |= AVE_TXCR_FLOCTR; 350 else 351 txcr &= ~AVE_TXCR_FLOCTR; 352 if (cap & FLOW_CTRL_RX) 353 rxcr |= AVE_RXCR_FLOCTR; 354 else 355 rxcr &= ~AVE_RXCR_FLOCTR; 356 } else { 357 rxcr &= ~AVE_RXCR_FDUPEN; 358 rxcr &= ~AVE_RXCR_FLOCTR; 359 txcr &= ~AVE_TXCR_FLOCTR; 360 } 361 362 if (rxcr_org != rxcr) { 363 /* disable Rx mac */ 364 writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR); 365 /* change and enable TX/Rx mac */ 366 writel(txcr, priv->iobase + AVE_TXCR); 367 writel(rxcr, priv->iobase + AVE_RXCR); 368 } 369 370 pr_notice("%s: phy:%s speed:%d mac:%pM\n", 371 phydev->dev->name, phydev->drv->name, phydev->speed, 372 pdata->enetaddr); 373 374 return phydev->link; 375} 376 377static int ave_mdiobus_init(struct ave_private *priv, const char *name) 378{ 379 struct mii_dev *bus = mdio_alloc(); 380 381 if (!bus) 382 return -ENOMEM; 383 384 bus->read = ave_mdiobus_read; 385 bus->write = ave_mdiobus_write; 386 snprintf(bus->name, sizeof(bus->name), "%s", name); 387 bus->priv = priv; 388 389 return mdio_register(bus); 390} 391 392static int ave_phy_init(struct ave_private *priv, void *dev) 393{ 394 struct phy_device *phydev; 395 int ret; 396 397 phydev = phy_connect(priv->bus, -1, dev, priv->phy_mode); 398 if (!phydev) 399 return -ENODEV; 400 401 phydev->supported &= PHY_GBIT_FEATURES; 402 if (priv->max_speed) { 403 ret = phy_set_supported(phydev, priv->max_speed); 404 if (ret) 405 return ret; 406 } 407 phydev->advertising = phydev->supported; 408 409 priv->phydev = phydev; 410 phy_config(phydev); 411 412 return 0; 413} 414 415static void ave_stop(struct udevice *dev) 416{ 417 struct ave_private *priv = dev_get_priv(dev); 418 u32 val; 419 int ret; 420 421 val = readl(priv->iobase + AVE_GRR); 422 if (val) 423 return; 424 425 val = readl(priv->iobase + AVE_RXCR); 426 val &= ~AVE_RXCR_RXEN; 427 writel(val, priv->iobase + AVE_RXCR); 428 429 writel(0, priv->iobase + AVE_DESCC); 430 ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val, 431 AVE_HALT_TIMEOUT_USEC); 432 if (ret) 433 pr_warn("%s: halt timeout\n", priv->phydev->dev->name); 434 435 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); 436 437 phy_shutdown(priv->phydev); 438} 439 440static void ave_reset(struct ave_private *priv) 441{ 442 u32 val; 443 444 /* reset RMII register */ 445 val = readl(priv->iobase + AVE_RSTCTRL); 446 val &= ~AVE_RSTCTRL_RMIIRST; 447 writel(val, priv->iobase + AVE_RSTCTRL); 448 449 /* assert reset */ 450 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR); 451 mdelay(AVE_GRST_DELAY_MSEC); 452 453 /* 1st, negate PHY reset only */ 454 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); 455 mdelay(AVE_GRST_DELAY_MSEC); 456 457 /* negate reset */ 458 writel(0, priv->iobase + AVE_GRR); 459 mdelay(AVE_GRST_DELAY_MSEC); 460 461 /* negate RMII register */ 462 val = readl(priv->iobase + AVE_RSTCTRL); 463 val |= AVE_RSTCTRL_RMIIRST; 464 writel(val, priv->iobase + AVE_RSTCTRL); 465} 466 467static int ave_start(struct udevice *dev) 468{ 469 struct ave_private *priv = dev_get_priv(dev); 470 uintptr_t paddr; 471 u32 val; 472 int i; 473 474 ave_reset(priv); 475 476 priv->rx_pos = 0; 477 priv->rx_off = 2; /* RX data has 2byte offsets */ 478 priv->tx_num = 0; 479 priv->tx_adj_buf = 480 (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0], 481 PKTALIGN); 482 priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off); 483 484 val = 0; 485 if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII && 486 priv->phy_mode != PHY_INTERFACE_MODE_RGMII_ID && 487 priv->phy_mode != PHY_INTERFACE_MODE_RGMII_RXID && 488 priv->phy_mode != PHY_INTERFACE_MODE_RGMII_TXID) 489 val |= AVE_CFGR_MII; 490 writel(val, priv->iobase + AVE_CFGR); 491 492 /* use one descriptor for Tx */ 493 writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC); 494 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0); 495 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0); 496 497 /* use PKTBUFSRX descriptors for Rx */ 498 writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC); 499 for (i = 0; i < PKTBUFSRX; i++) { 500 paddr = (uintptr_t)net_rx_packets[i]; 501 ave_cache_flush(paddr, priv->rx_siz + priv->rx_off); 502 ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr); 503 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz); 504 } 505 506 writel(AVE_GISR_CLR, priv->iobase + AVE_GISR); 507 writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR); 508 509 writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU, 510 priv->iobase + AVE_RXCR); 511 writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC); 512 513 phy_startup(priv->phydev); 514 ave_adjust_link(priv); 515 516 return 0; 517} 518 519static int ave_write_hwaddr(struct udevice *dev) 520{ 521 struct ave_private *priv = dev_get_priv(dev); 522 struct eth_pdata *pdata = dev_get_plat(dev); 523 u8 *mac = pdata->enetaddr; 524 525 writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, 526 priv->iobase + AVE_RXMAC1R); 527 writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R); 528 529 return 0; 530} 531 532static int ave_send(struct udevice *dev, void *packet, int length) 533{ 534 struct ave_private *priv = dev_get_priv(dev); 535 u32 val; 536 void *ptr = packet; 537 int count; 538 539 /* adjust alignment for descriptor */ 540 if ((uintptr_t)ptr & 0x3) { 541 memcpy(priv->tx_adj_buf, (const void *)ptr, length); 542 ptr = priv->tx_adj_buf; 543 } 544 545 /* padding for minimum length */ 546 if (length < AVE_MIN_XMITSIZE) { 547 memset(ptr + length, 0, AVE_MIN_XMITSIZE - length); 548 length = AVE_MIN_XMITSIZE; 549 } 550 551 /* check ownership and wait for previous xmit done */ 552 count = AVE_SEND_TIMEOUT_COUNT; 553 do { 554 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); 555 } while ((val & AVE_STS_OWN) && --count); 556 if (!count) 557 return -ETIMEDOUT; 558 559 ave_cache_flush((uintptr_t)ptr, length); 560 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr); 561 562 val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | 563 (length & AVE_STS_PKTLEN_TX_MASK); 564 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val); 565 priv->tx_num++; 566 567 count = AVE_SEND_TIMEOUT_COUNT; 568 do { 569 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); 570 } while ((val & AVE_STS_OWN) && --count); 571 if (!count) 572 return -ETIMEDOUT; 573 574 if (!(val & AVE_STS_OK)) 575 pr_warn("%s: bad send packet status:%08x\n", 576 priv->phydev->dev->name, le32_to_cpu(val)); 577 578 return 0; 579} 580 581static int ave_recv(struct udevice *dev, int flags, uchar **packetp) 582{ 583 struct ave_private *priv = dev_get_priv(dev); 584 uchar *ptr; 585 int length = 0; 586 u32 cmdsts; 587 588 while (1) { 589 cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX, 590 priv->rx_pos); 591 if (!(cmdsts & AVE_STS_OWN)) 592 /* hardware ownership, no received packets */ 593 return -EAGAIN; 594 595 ptr = net_rx_packets[priv->rx_pos] + priv->rx_off; 596 if (cmdsts & AVE_STS_OK) 597 break; 598 599 pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n", 600 priv->phydev->dev->name, priv->rx_pos, 601 le32_to_cpu(cmdsts), ptr); 602 } 603 604 length = cmdsts & AVE_STS_PKTLEN_RX_MASK; 605 606 /* invalidate after DMA is done */ 607 ave_cache_invalidate((uintptr_t)ptr, length); 608 *packetp = ptr; 609 610 return length; 611} 612 613static int ave_free_packet(struct udevice *dev, uchar *packet, int length) 614{ 615 struct ave_private *priv = dev_get_priv(dev); 616 617 ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos], 618 priv->rx_siz + priv->rx_off); 619 620 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, 621 priv->rx_pos, priv->rx_siz); 622 623 if (++priv->rx_pos >= PKTBUFSRX) 624 priv->rx_pos = 0; 625 626 return 0; 627} 628 629static int ave_pro4_get_pinmode(struct ave_private *priv) 630{ 631 u32 reg, mask, val = 0; 632 633 if (priv->regmap_arg > 0) 634 return -EINVAL; 635 636 mask = SG_ETPINMODE_RMII(0); 637 638 switch (priv->phy_mode) { 639 case PHY_INTERFACE_MODE_RMII: 640 val = SG_ETPINMODE_RMII(0); 641 break; 642 case PHY_INTERFACE_MODE_MII: 643 case PHY_INTERFACE_MODE_RGMII: 644 case PHY_INTERFACE_MODE_RGMII_ID: 645 case PHY_INTERFACE_MODE_RGMII_RXID: 646 case PHY_INTERFACE_MODE_RGMII_TXID: 647 break; 648 default: 649 return -EINVAL; 650 } 651 652 regmap_read(priv->regmap, SG_ETPINMODE, ®); 653 reg &= ~mask; 654 reg |= val; 655 regmap_write(priv->regmap, SG_ETPINMODE, reg); 656 657 return 0; 658} 659 660static int ave_ld11_get_pinmode(struct ave_private *priv) 661{ 662 u32 reg, mask, val = 0; 663 664 if (priv->regmap_arg > 0) 665 return -EINVAL; 666 667 mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 668 669 switch (priv->phy_mode) { 670 case PHY_INTERFACE_MODE_INTERNAL: 671 break; 672 case PHY_INTERFACE_MODE_RMII: 673 val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 674 break; 675 default: 676 return -EINVAL; 677 } 678 679 regmap_read(priv->regmap, SG_ETPINMODE, ®); 680 reg &= ~mask; 681 reg |= val; 682 regmap_write(priv->regmap, SG_ETPINMODE, reg); 683 684 return 0; 685} 686 687static int ave_ld20_get_pinmode(struct ave_private *priv) 688{ 689 u32 reg, mask, val = 0; 690 691 if (priv->regmap_arg > 0) 692 return -EINVAL; 693 694 mask = SG_ETPINMODE_RMII(0); 695 696 switch (priv->phy_mode) { 697 case PHY_INTERFACE_MODE_RMII: 698 val = SG_ETPINMODE_RMII(0); 699 break; 700 case PHY_INTERFACE_MODE_RGMII: 701 case PHY_INTERFACE_MODE_RGMII_ID: 702 case PHY_INTERFACE_MODE_RGMII_RXID: 703 case PHY_INTERFACE_MODE_RGMII_TXID: 704 break; 705 default: 706 return -EINVAL; 707 } 708 709 regmap_read(priv->regmap, SG_ETPINMODE, ®); 710 reg &= ~mask; 711 reg |= val; 712 regmap_write(priv->regmap, SG_ETPINMODE, reg); 713 714 return 0; 715} 716 717static int ave_pxs3_get_pinmode(struct ave_private *priv) 718{ 719 u32 reg, mask, val = 0; 720 721 if (priv->regmap_arg > 1) 722 return -EINVAL; 723 724 mask = SG_ETPINMODE_RMII(priv->regmap_arg); 725 726 switch (priv->phy_mode) { 727 case PHY_INTERFACE_MODE_RMII: 728 val = SG_ETPINMODE_RMII(priv->regmap_arg); 729 break; 730 case PHY_INTERFACE_MODE_RGMII: 731 case PHY_INTERFACE_MODE_RGMII_ID: 732 case PHY_INTERFACE_MODE_RGMII_RXID: 733 case PHY_INTERFACE_MODE_RGMII_TXID: 734 break; 735 default: 736 return -EINVAL; 737 } 738 739 regmap_read(priv->regmap, SG_ETPINMODE, ®); 740 reg &= ~mask; 741 reg |= val; 742 regmap_write(priv->regmap, SG_ETPINMODE, reg); 743 744 return 0; 745} 746 747static int ave_of_to_plat(struct udevice *dev) 748{ 749 struct eth_pdata *pdata = dev_get_plat(dev); 750 struct ave_private *priv = dev_get_priv(dev); 751 struct ofnode_phandle_args args; 752 const u32 *valp; 753 int ret, nc, nr; 754 const char *name; 755 756 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); 757 if (!priv->data) 758 return -EINVAL; 759 760 pdata->iobase = dev_read_addr(dev); 761 762 pdata->phy_interface = dev_read_phy_mode(dev); 763 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) 764 return -EINVAL; 765 766 pdata->max_speed = 0; 767 valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", 768 NULL); 769 if (valp) 770 pdata->max_speed = fdt32_to_cpu(*valp); 771 772 for (nc = 0; nc < AVE_MAX_CLKS; nc++) { 773 name = priv->data->clock_names[nc]; 774 if (!name) 775 break; 776 ret = clk_get_by_name(dev, name, &priv->clk[nc]); 777 if (ret) { 778 dev_err(dev, "Failed to get clocks property: %d\n", 779 ret); 780 return ret; 781 } 782 priv->nclks++; 783 } 784 785 for (nr = 0; nr < AVE_MAX_RSTS; nr++) { 786 name = priv->data->reset_names[nr]; 787 if (!name) 788 break; 789 ret = reset_get_by_name(dev, name, &priv->rst[nr]); 790 if (ret) { 791 dev_err(dev, "Failed to get resets property: %d\n", 792 ret); 793 goto out_reset_free; 794 } 795 priv->nrsts++; 796 } 797 798 ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode", 799 NULL, 1, 0, &args); 800 if (ret) { 801 dev_err(dev, "Failed to get syscon-phy-mode property: %d\n", 802 ret); 803 goto out_reset_free; 804 } 805 806 priv->regmap = syscon_node_to_regmap(args.node); 807 if (IS_ERR(priv->regmap)) { 808 ret = PTR_ERR(priv->regmap); 809 dev_err(dev, "can't get syscon: %d\n", ret); 810 goto out_reset_free; 811 } 812 813 if (args.args_count != 1) { 814 ret = -EINVAL; 815 dev_err(dev, "Invalid argument of syscon-phy-mode\n"); 816 goto out_reset_free; 817 } 818 819 priv->regmap_arg = args.args[0]; 820 821 return 0; 822 823out_reset_free: 824 while (--nr >= 0) 825 reset_free(&priv->rst[nr]); 826 827 return ret; 828} 829 830static int ave_probe(struct udevice *dev) 831{ 832 struct eth_pdata *pdata = dev_get_plat(dev); 833 struct ave_private *priv = dev_get_priv(dev); 834 int ret, nc, nr; 835 836 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); 837 if (!priv->data) 838 return -EINVAL; 839 840 priv->iobase = pdata->iobase; 841 priv->phy_mode = pdata->phy_interface; 842 priv->max_speed = pdata->max_speed; 843 844 ret = priv->data->get_pinmode(priv); 845 if (ret) { 846 dev_err(dev, "Invalid phy-mode\n"); 847 return -EINVAL; 848 } 849 850 for (nc = 0; nc < priv->nclks; nc++) { 851 ret = clk_enable(&priv->clk[nc]); 852 if (ret) { 853 dev_err(dev, "Failed to enable clk: %d\n", ret); 854 goto out_clk_release; 855 } 856 } 857 858 for (nr = 0; nr < priv->nrsts; nr++) { 859 ret = reset_deassert(&priv->rst[nr]); 860 if (ret) { 861 dev_err(dev, "Failed to deassert reset: %d\n", ret); 862 goto out_reset_release; 863 } 864 } 865 866 ave_reset(priv); 867 868 ret = ave_mdiobus_init(priv, dev->name); 869 if (ret) { 870 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); 871 goto out_reset_release; 872 } 873 874 priv->bus = miiphy_get_dev_by_name(dev->name); 875 876 ret = ave_phy_init(priv, dev); 877 if (ret) { 878 dev_err(dev, "Failed to initialize phy: %d\n", ret); 879 goto out_mdiobus_release; 880 } 881 882 return 0; 883 884out_mdiobus_release: 885 mdio_unregister(priv->bus); 886 mdio_free(priv->bus); 887out_reset_release: 888 reset_release_all(priv->rst, nr); 889out_clk_release: 890 clk_release_all(priv->clk, nc); 891 892 return ret; 893} 894 895static int ave_remove(struct udevice *dev) 896{ 897 struct ave_private *priv = dev_get_priv(dev); 898 899 free(priv->phydev); 900 mdio_unregister(priv->bus); 901 mdio_free(priv->bus); 902 reset_release_all(priv->rst, priv->nrsts); 903 clk_release_all(priv->clk, priv->nclks); 904 905 return 0; 906} 907 908static const struct eth_ops ave_ops = { 909 .start = ave_start, 910 .stop = ave_stop, 911 .send = ave_send, 912 .recv = ave_recv, 913 .free_pkt = ave_free_packet, 914 .write_hwaddr = ave_write_hwaddr, 915}; 916 917static const struct ave_soc_data ave_pro4_data = { 918 .is_desc_64bit = false, 919 .clock_names = { 920 "gio", "ether", "ether-gb", "ether-phy", 921 }, 922 .reset_names = { 923 "gio", "ether", 924 }, 925 .get_pinmode = ave_pro4_get_pinmode, 926}; 927 928static const struct ave_soc_data ave_pxs2_data = { 929 .is_desc_64bit = false, 930 .clock_names = { 931 "ether", 932 }, 933 .reset_names = { 934 "ether", 935 }, 936 .get_pinmode = ave_pro4_get_pinmode, 937}; 938 939static const struct ave_soc_data ave_ld11_data = { 940 .is_desc_64bit = false, 941 .clock_names = { 942 "ether", 943 }, 944 .reset_names = { 945 "ether", 946 }, 947 .get_pinmode = ave_ld11_get_pinmode, 948}; 949 950static const struct ave_soc_data ave_ld20_data = { 951 .is_desc_64bit = true, 952 .clock_names = { 953 "ether", 954 }, 955 .reset_names = { 956 "ether", 957 }, 958 .get_pinmode = ave_ld20_get_pinmode, 959}; 960 961static const struct ave_soc_data ave_pxs3_data = { 962 .is_desc_64bit = false, 963 .clock_names = { 964 "ether", 965 }, 966 .reset_names = { 967 "ether", 968 }, 969 .get_pinmode = ave_pxs3_get_pinmode, 970}; 971 972static const struct udevice_id ave_ids[] = { 973 { 974 .compatible = "socionext,uniphier-pro4-ave4", 975 .data = (ulong)&ave_pro4_data, 976 }, 977 { 978 .compatible = "socionext,uniphier-pxs2-ave4", 979 .data = (ulong)&ave_pxs2_data, 980 }, 981 { 982 .compatible = "socionext,uniphier-ld11-ave4", 983 .data = (ulong)&ave_ld11_data, 984 }, 985 { 986 .compatible = "socionext,uniphier-ld20-ave4", 987 .data = (ulong)&ave_ld20_data, 988 }, 989 { 990 .compatible = "socionext,uniphier-pxs3-ave4", 991 .data = (ulong)&ave_pxs3_data, 992 }, 993 { /* Sentinel */ } 994}; 995 996U_BOOT_DRIVER(ave) = { 997 .name = "ave", 998 .id = UCLASS_ETH, 999 .of_match = ave_ids, 1000 .probe = ave_probe, 1001 .remove = ave_remove, 1002 .of_to_plat = ave_of_to_plat, 1003 .ops = &ave_ops, 1004 .priv_auto = sizeof(struct ave_private), 1005 .plat_auto = sizeof(struct eth_pdata), 1006}; 1007