1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Aquantia PHY drivers 4 * 5 * Copyright 2014 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2021 NXP 7 */ 8#include <config.h> 9#include <common.h> 10#include <dm.h> 11#include <log.h> 12#include <net.h> 13#include <phy.h> 14#include <linux/bitops.h> 15#include <linux/delay.h> 16#include <u-boot/crc.h> 17#include <malloc.h> 18#include <asm/byteorder.h> 19#include <fs.h> 20 21#define AQUNTIA_10G_CTL 0x20 22#define AQUNTIA_VENDOR_P1 0xc400 23 24#define AQUNTIA_SPEED_LSB_MASK 0x2000 25#define AQUNTIA_SPEED_MSB_MASK 0x40 26 27#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 28#define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0) 29#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 30#define AQUANTIA_FIRMWARE_ID 0x20 31#define AQUANTIA_RESERVED_STATUS 0xc885 32#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00 33#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff 34#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0 35 36#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 37#define AQUANTIA_SI_IN_USE_MASK 0x0078 38#define AQUANTIA_SI_USXGMII 0x0018 39 40/* registers in MDIO_MMD_VEND1 region */ 41#define AQUANTIA_VND1_GLOBAL_SC 0x000 42#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb) 43 44#define GLOBAL_FIRMWARE_ID 0x20 45#define GLOBAL_FAULT 0xc850 46#define GLOBAL_RSTATUS_1 0xc885 47 48#define GLOBAL_ALARM_1 0xcc00 49#define SYSTEM_READY_BIT 0x40 50 51#define GLOBAL_STANDARD_CONTROL 0x0 52#define SOFT_RESET BIT(15) 53#define LOW_POWER BIT(11) 54 55#define MAILBOX_CONTROL 0x0200 56#define MAILBOX_EXECUTE BIT(15) 57#define MAILBOX_WRITE BIT(14) 58#define MAILBOX_RESET_CRC BIT(12) 59#define MAILBOX_BUSY BIT(8) 60 61#define MAILBOX_CRC 0x0201 62 63#define MAILBOX_ADDR_MSW 0x0202 64#define MAILBOX_ADDR_LSW 0x0203 65 66#define MAILBOX_DATA_MSW 0x0204 67#define MAILBOX_DATA_LSW 0x0205 68 69#define UP_CONTROL 0xc001 70#define UP_RESET BIT(15) 71#define UP_RUN_STALL_OVERRIDE BIT(6) 72#define UP_RUN_STALL BIT(0) 73 74#define AQUANTIA_PMA_RX_VENDOR_P1 0xe400 75#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0) 76/* MDI reversal configured through registers */ 77#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1) 78/* MDI reversal enabled */ 79#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0) 80 81/* 82 * global start rate, the protocol associated with this speed is used by default 83 * on SI. 84 */ 85#define AQUANTIA_VND1_GSTART_RATE 0x31a 86#define AQUANTIA_VND1_GSTART_RATE_OFF 0 87#define AQUANTIA_VND1_GSTART_RATE_100M 1 88#define AQUANTIA_VND1_GSTART_RATE_1G 2 89#define AQUANTIA_VND1_GSTART_RATE_10G 3 90#define AQUANTIA_VND1_GSTART_RATE_2_5G 4 91#define AQUANTIA_VND1_GSTART_RATE_5G 5 92 93/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */ 94#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b 95#define AQUANTIA_VND1_GSYSCFG_100M 0 96#define AQUANTIA_VND1_GSYSCFG_1G 1 97#define AQUANTIA_VND1_GSYSCFG_2_5G 2 98#define AQUANTIA_VND1_GSYSCFG_5G 3 99#define AQUANTIA_VND1_GSYSCFG_10G 4 100 101#define AQUANTIA_VND1_SMBUS0 0xc485 102#define AQUANTIA_VND1_SMBUS1 0xc495 103 104/* addresses of memory segments in the phy */ 105#define DRAM_BASE_ADDR 0x3FFE0000 106#define IRAM_BASE_ADDR 0x40000000 107 108/* firmware image format constants */ 109#define VERSION_STRING_SIZE 0x40 110#define VERSION_STRING_OFFSET 0x0200 111#define HEADER_OFFSET 0x300 112 113/* driver private data */ 114#define AQUANTIA_NA 0 115#define AQUANTIA_GEN1 1 116#define AQUANTIA_GEN2 2 117#define AQUANTIA_GEN3 3 118 119#pragma pack(1) 120struct fw_header { 121 u8 padding[4]; 122 u8 iram_offset[3]; 123 u8 iram_size[3]; 124 u8 dram_offset[3]; 125 u8 dram_size[3]; 126}; 127 128#pragma pack() 129 130#if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW) 131static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length) 132{ 133 loff_t length, read; 134 int ret; 135 void *addr = NULL; 136 137 *fw_addr = NULL; 138 *fw_length = 0; 139 debug("Loading Aquantia microcode from %s %s\n", 140 CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME); 141 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY); 142 if (ret < 0) 143 goto cleanup; 144 145 ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length); 146 if (ret < 0) 147 goto cleanup; 148 149 addr = malloc(length); 150 if (!addr) { 151 ret = -ENOMEM; 152 goto cleanup; 153 } 154 155 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY); 156 if (ret < 0) 157 goto cleanup; 158 159 ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length, 160 &read); 161 if (ret < 0) 162 goto cleanup; 163 164 *fw_addr = addr; 165 *fw_length = length; 166 debug("Found Aquantia microcode.\n"); 167 168cleanup: 169 if (ret < 0) { 170 printf("loading firmware file %s %s failed with error %d\n", 171 CONFIG_PHY_AQUANTIA_FW_PART, 172 CONFIG_PHY_AQUANTIA_FW_NAME, ret); 173 free(addr); 174 } 175 return ret; 176} 177 178/* load data into the phy's memory */ 179static int aquantia_load_memory(struct phy_device *phydev, u32 addr, 180 const u8 *data, size_t len) 181{ 182 size_t pos; 183 u16 crc = 0, up_crc; 184 185 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC); 186 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16); 187 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc); 188 189 for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) { 190 u32 word = 0; 191 192 memcpy(&word, &data[pos], min(sizeof(u32), len - pos)); 193 194 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW, 195 (word >> 16)); 196 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW, 197 word & 0xffff); 198 199 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, 200 MAILBOX_EXECUTE | MAILBOX_WRITE); 201 202 /* keep a big endian CRC to match the phy processor */ 203 word = cpu_to_be32(word); 204 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word)); 205 } 206 207 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC); 208 if (crc != up_crc) { 209 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n", 210 phydev->dev->name, crc, up_crc); 211 return -EINVAL; 212 } 213 return 0; 214} 215 216static u32 unpack_u24(const u8 *data) 217{ 218 return (data[2] << 16) + (data[1] << 8) + data[0]; 219} 220 221static int aquantia_upload_firmware(struct phy_device *phydev) 222{ 223 int ret; 224 u8 *addr = NULL; 225 size_t fw_length = 0; 226 u16 calculated_crc, read_crc; 227 char version[VERSION_STRING_SIZE]; 228 u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size; 229 const struct fw_header *header; 230 231 ret = aquantia_read_fw(&addr, &fw_length); 232 if (ret != 0) 233 return ret; 234 235 read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1]; 236 calculated_crc = crc16_ccitt(0, addr, fw_length - 2); 237 if (read_crc != calculated_crc) { 238 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n", 239 phydev->dev->name, read_crc, calculated_crc); 240 ret = -EINVAL; 241 goto done; 242 } 243 244 /* Find the DRAM and IRAM sections within the firmware file. */ 245 primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12; 246 247 header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET]; 248 249 iram_offset = primary_offset + unpack_u24(header->iram_offset); 250 iram_size = unpack_u24(header->iram_size); 251 252 dram_offset = primary_offset + unpack_u24(header->dram_offset); 253 dram_size = unpack_u24(header->dram_size); 254 255 debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n", 256 primary_offset, iram_offset, iram_size, dram_offset, dram_size); 257 258 strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET], 259 VERSION_STRING_SIZE); 260 printf("%s loading firmware version '%s'\n", phydev->dev->name, version); 261 262 /* stall the microcprocessor */ 263 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, 264 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE); 265 266 debug("loading dram 0x%08x from offset=%d size=%d\n", 267 DRAM_BASE_ADDR, dram_offset, dram_size); 268 ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset], 269 dram_size); 270 if (ret != 0) 271 goto done; 272 273 debug("loading iram 0x%08x from offset=%d size=%d\n", 274 IRAM_BASE_ADDR, iram_offset, iram_size); 275 ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset], 276 iram_size); 277 if (ret != 0) 278 goto done; 279 280 /* make sure soft reset and low power mode are clear */ 281 phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0); 282 283 /* Release the microprocessor. UP_RESET must be held for 100 usec. */ 284 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, 285 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET); 286 287 udelay(100); 288 289 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE); 290 291 printf("%s firmware loading done.\n", phydev->dev->name); 292done: 293 free(addr); 294 return ret; 295} 296#else 297static int aquantia_upload_firmware(struct phy_device *phydev) 298{ 299 printf("ERROR %s firmware loading disabled.\n", phydev->dev->name); 300 return -1; 301} 302#endif 303 304struct { 305 u16 syscfg; 306 int cnt; 307 u16 start_rate; 308} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = { 309 [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G, 310 AQUANTIA_VND1_GSTART_RATE_1G}, 311 [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, 312 AQUANTIA_VND1_GSTART_RATE_2_5G}, 313 [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, 314 AQUANTIA_VND1_GSTART_RATE_10G}, 315 [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, 316 AQUANTIA_VND1_GSTART_RATE_10G}, 317}; 318 319static int aquantia_set_proto(struct phy_device *phydev, 320 phy_interface_t interface) 321{ 322 int i; 323 324 if (!aquantia_syscfg[interface].cnt) 325 return 0; 326 327 /* set the default rate to enable the SI link */ 328 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, 329 aquantia_syscfg[interface].start_rate); 330 331 /* set selected protocol for all relevant line side link speeds */ 332 for (i = 0; i <= aquantia_syscfg[interface].cnt; i++) 333 phy_write(phydev, MDIO_MMD_VEND1, 334 AQUANTIA_VND1_GSYSCFG_BASE + i, 335 aquantia_syscfg[interface].syscfg); 336 return 0; 337} 338 339static int aquantia_dts_config(struct phy_device *phydev) 340{ 341 ofnode node = phydev->node; 342 u32 prop; 343 u16 reg; 344 345 /* this code only works on gen2 and gen3 PHYs */ 346 if (phydev->drv->data != AQUANTIA_GEN2 && 347 phydev->drv->data != AQUANTIA_GEN3) 348 return -ENOTSUPP; 349 350 if (!ofnode_valid(node)) 351 return 0; 352 353 if (!ofnode_read_u32(node, "mdi-reversal", &prop)) { 354 debug("mdi-reversal = %d\n", (int)prop); 355 reg = phy_read(phydev, MDIO_MMD_PMAPMD, 356 AQUANTIA_PMA_RX_VENDOR_P1); 357 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK; 358 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG; 359 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0; 360 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1, 361 reg); 362 } 363 if (!ofnode_read_u32(node, "smb-addr", &prop)) { 364 debug("smb-addr = %x\n", (int)prop); 365 /* 366 * there are two addresses here, normally just one bus would 367 * be in use so we're setting both regs using the same DT 368 * property. 369 */ 370 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0, 371 (u16)(prop << 1)); 372 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1, 373 (u16)(prop << 1)); 374 } 375 376 return 0; 377} 378 379static bool aquantia_link_is_up(struct phy_device *phydev) 380{ 381 u16 reg, regmask; 382 int devad, regnum; 383 384 /* 385 * On Gen 2 and 3 we have a bit that indicates that both system and 386 * line side are ready for data, use that if possible. 387 */ 388 if (phydev->drv->data == AQUANTIA_GEN2 || 389 phydev->drv->data == AQUANTIA_GEN3) { 390 devad = MDIO_MMD_PHYXS; 391 regnum = AQUANTIA_SYSTEM_INTERFACE_SR; 392 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY; 393 } else { 394 devad = MDIO_MMD_AN; 395 regnum = MDIO_STAT1; 396 regmask = MDIO_AN_STAT1_COMPLETE; 397 } 398 /* the register should be latched, do a double read */ 399 phy_read(phydev, devad, regnum); 400 reg = phy_read(phydev, devad, regnum); 401 402 return !!(reg & regmask); 403} 404 405int aquantia_config(struct phy_device *phydev) 406{ 407 int interface = phydev->interface; 408 u32 val, id, rstatus, fault; 409 u32 reg_val1 = 0; 410 int num_retries = 5; 411 int usx_an = 0; 412 413 /* 414 * check if the system is out of reset and init sequence completed. 415 * chip-wide reset for gen1 quad phys takes longer 416 */ 417 while (--num_retries) { 418 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1); 419 if (rstatus & SYSTEM_READY_BIT) 420 break; 421 mdelay(10); 422 } 423 424 id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID); 425 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1); 426 fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT); 427 428 if (id != 0) 429 debug("%s running firmware version %X.%X.%X\n", 430 phydev->dev->name, (id >> 8), id & 0xff, 431 (rstatus >> 4) & 0xf); 432 433 if (fault != 0) 434 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault); 435 436 if (id == 0 || fault != 0) { 437 int ret; 438 439 ret = aquantia_upload_firmware(phydev); 440 if (ret != 0) 441 return ret; 442 } 443 /* 444 * for backward compatibility convert XGMII into either 10GBase-R or 445 * USXGMII based on FW config 446 */ 447 if (interface == PHY_INTERFACE_MODE_XGMII) { 448 debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n"); 449 450 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, 451 AQUANTIA_SYSTEM_INTERFACE_SR); 452 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) 453 interface = PHY_INTERFACE_MODE_USXGMII; 454 else 455 interface = PHY_INTERFACE_MODE_10GBASER; 456 } 457 458 /* 459 * if link is up already we can just use it, otherwise configure 460 * the protocols in the PHY. If link is down set the system 461 * interface protocol to use based on phydev->interface 462 */ 463 if (!aquantia_link_is_up(phydev) && 464 (phydev->drv->data == AQUANTIA_GEN2 || 465 phydev->drv->data == AQUANTIA_GEN3)) { 466 /* set PHY in low power mode so we can configure protocols */ 467 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 468 AQUANTIA_VND1_GLOBAL_SC_LP); 469 mdelay(10); 470 471 /* configure protocol based on phydev->interface */ 472 aquantia_set_proto(phydev, interface); 473 /* apply custom configuration based on DT */ 474 aquantia_dts_config(phydev); 475 476 /* wake PHY back up */ 477 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0); 478 mdelay(10); 479 } 480 481 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); 482 483 switch (interface) { 484 case PHY_INTERFACE_MODE_SGMII: 485 /* 1000BASE-T mode */ 486 phydev->advertising = SUPPORTED_1000baseT_Full; 487 phydev->supported = phydev->advertising; 488 489 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK; 490 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); 491 break; 492 case PHY_INTERFACE_MODE_USXGMII: 493 usx_an = 1; 494 /* FALLTHROUGH */ 495 case PHY_INTERFACE_MODE_10GBASER: 496 /* 10GBASE-T mode */ 497 phydev->advertising = SUPPORTED_10000baseT_Full; 498 phydev->supported = phydev->advertising; 499 500 if (!(val & AQUNTIA_SPEED_LSB_MASK) || 501 !(val & AQUNTIA_SPEED_MSB_MASK)) 502 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, 503 AQUNTIA_SPEED_LSB_MASK | 504 AQUNTIA_SPEED_MSB_MASK); 505 506 /* If SI is USXGMII then start USXGMII autoneg */ 507 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, 508 AQUANTIA_VENDOR_PROVISIONING_REG); 509 510 if (usx_an) { 511 reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA; 512 debug("%s: system interface USXGMII\n", 513 phydev->dev->name); 514 } else { 515 reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; 516 debug("%s: system interface 10GBase-R\n", 517 phydev->dev->name); 518 } 519 520 phy_write(phydev, MDIO_MMD_PHYXS, 521 AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1); 522 break; 523 case PHY_INTERFACE_MODE_2500BASEX: 524 /* 2.5GBASE-T mode */ 525 phydev->advertising = SUPPORTED_1000baseT_Full; 526 phydev->supported = phydev->advertising; 527 528 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1); 529 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440); 530 break; 531 case PHY_INTERFACE_MODE_MII: 532 /* 100BASE-TX mode */ 533 phydev->advertising = SUPPORTED_100baseT_Full; 534 phydev->supported = phydev->advertising; 535 536 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; 537 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); 538 break; 539 }; 540 541 val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS); 542 reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID); 543 544 debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name, 545 phydev->drv->name, 546 (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8, 547 reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK, 548 (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4); 549 550 return 0; 551} 552 553int aquantia_startup(struct phy_device *phydev) 554{ 555 u32 speed; 556 int i = 0; 557 int reg; 558 559 phydev->duplex = DUPLEX_FULL; 560 561 /* if the AN is still in progress, wait till timeout. */ 562 if (!aquantia_link_is_up(phydev)) { 563 printf("%s Waiting for PHY auto negotiation to complete", 564 phydev->dev->name); 565 do { 566 udelay(1000); 567 if ((i++ % 500) == 0) 568 printf("."); 569 } while (!aquantia_link_is_up(phydev) && 570 i < (4 * PHY_ANEG_TIMEOUT)); 571 572 if (i > PHY_ANEG_TIMEOUT) 573 printf(" TIMEOUT !\n"); 574 } 575 576 /* Read twice because link state is latched and a 577 * read moves the current state into the register */ 578 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); 579 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); 580 if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) 581 phydev->link = 0; 582 else 583 phydev->link = 1; 584 585 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); 586 if (speed & AQUNTIA_SPEED_MSB_MASK) { 587 if (speed & AQUNTIA_SPEED_LSB_MASK) 588 phydev->speed = SPEED_10000; 589 else 590 phydev->speed = SPEED_1000; 591 } else { 592 if (speed & AQUNTIA_SPEED_LSB_MASK) 593 phydev->speed = SPEED_100; 594 else 595 phydev->speed = SPEED_10; 596 } 597 598 return 0; 599} 600 601U_BOOT_PHY_DRIVER(aq1202) = { 602 .name = "Aquantia AQ1202", 603 .uid = 0x3a1b445, 604 .mask = 0xfffffff0, 605 .features = PHY_10G_FEATURES, 606 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| 607 MDIO_MMD_PHYXS | MDIO_MMD_AN | 608 MDIO_MMD_VEND1), 609 .config = &aquantia_config, 610 .startup = &aquantia_startup, 611 .shutdown = &gen10g_shutdown, 612}; 613 614U_BOOT_PHY_DRIVER(aq2104) = { 615 .name = "Aquantia AQ2104", 616 .uid = 0x3a1b460, 617 .mask = 0xfffffff0, 618 .features = PHY_10G_FEATURES, 619 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| 620 MDIO_MMD_PHYXS | MDIO_MMD_AN | 621 MDIO_MMD_VEND1), 622 .config = &aquantia_config, 623 .startup = &aquantia_startup, 624 .shutdown = &gen10g_shutdown, 625}; 626 627U_BOOT_PHY_DRIVER(aqr105) = { 628 .name = "Aquantia AQR105", 629 .uid = 0x3a1b4a2, 630 .mask = 0xfffffff0, 631 .features = PHY_10G_FEATURES, 632 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| 633 MDIO_MMD_PHYXS | MDIO_MMD_AN | 634 MDIO_MMD_VEND1), 635 .config = &aquantia_config, 636 .startup = &aquantia_startup, 637 .shutdown = &gen10g_shutdown, 638 .data = AQUANTIA_GEN1, 639}; 640 641U_BOOT_PHY_DRIVER(aqr106) = { 642 .name = "Aquantia AQR106", 643 .uid = 0x3a1b4d0, 644 .mask = 0xfffffff0, 645 .features = PHY_10G_FEATURES, 646 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| 647 MDIO_MMD_PHYXS | MDIO_MMD_AN | 648 MDIO_MMD_VEND1), 649 .config = &aquantia_config, 650 .startup = &aquantia_startup, 651 .shutdown = &gen10g_shutdown, 652}; 653 654U_BOOT_PHY_DRIVER(aqr107) = { 655 .name = "Aquantia AQR107", 656 .uid = 0x3a1b4e0, 657 .mask = 0xfffffff0, 658 .features = PHY_10G_FEATURES, 659 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| 660 MDIO_MMD_PHYXS | MDIO_MMD_AN | 661 MDIO_MMD_VEND1), 662 .config = &aquantia_config, 663 .startup = &aquantia_startup, 664 .shutdown = &gen10g_shutdown, 665 .data = AQUANTIA_GEN2, 666}; 667 668U_BOOT_PHY_DRIVER(aqr112) = { 669 .name = "Aquantia AQR112", 670 .uid = 0x3a1b660, 671 .mask = 0xfffffff0, 672 .features = PHY_10G_FEATURES, 673 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | 674 MDIO_MMD_PHYXS | MDIO_MMD_AN | 675 MDIO_MMD_VEND1), 676 .config = &aquantia_config, 677 .startup = &aquantia_startup, 678 .shutdown = &gen10g_shutdown, 679 .data = AQUANTIA_GEN3, 680}; 681 682U_BOOT_PHY_DRIVER(aqr113c) = { 683 .name = "Aquantia AQR113C", 684 .uid = 0x31c31c12, 685 .mask = 0xfffffff0, 686 .features = PHY_10G_FEATURES, 687 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | 688 MDIO_MMD_PHYXS | MDIO_MMD_AN | 689 MDIO_MMD_VEND1), 690 .config = &aquantia_config, 691 .startup = &aquantia_startup, 692 .shutdown = &gen10g_shutdown, 693 .data = AQUANTIA_GEN3, 694}; 695 696U_BOOT_PHY_DRIVER(aqr405) = { 697 .name = "Aquantia AQR405", 698 .uid = 0x3a1b4b2, 699 .mask = 0xfffffff0, 700 .features = PHY_10G_FEATURES, 701 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS| 702 MDIO_MMD_PHYXS | MDIO_MMD_AN | 703 MDIO_MMD_VEND1), 704 .config = &aquantia_config, 705 .startup = &aquantia_startup, 706 .shutdown = &gen10g_shutdown, 707 .data = AQUANTIA_GEN1, 708}; 709 710U_BOOT_PHY_DRIVER(aqr412) = { 711 .name = "Aquantia AQR412", 712 .uid = 0x3a1b710, 713 .mask = 0xfffffff0, 714 .features = PHY_10G_FEATURES, 715 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS | 716 MDIO_MMD_PHYXS | MDIO_MMD_AN | 717 MDIO_MMD_VEND1), 718 .config = &aquantia_config, 719 .startup = &aquantia_startup, 720 .shutdown = &gen10g_shutdown, 721 .data = AQUANTIA_GEN3, 722}; 723