1/* 2 * Altera 10/100/1000 triple speed ethernet mac driver 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <cpu_func.h> 12#include <dm.h> 13#include <errno.h> 14#include <fdt_support.h> 15#include <log.h> 16#include <memalign.h> 17#include <miiphy.h> 18#include <net.h> 19#include <asm/cache.h> 20#include <asm/global_data.h> 21#include <linux/dma-mapping.h> 22#include <asm/io.h> 23#include "altera_tse.h" 24 25DECLARE_GLOBAL_DATA_PTR; 26 27static inline void alt_sgdma_construct_descriptor( 28 struct alt_sgdma_descriptor *desc, 29 struct alt_sgdma_descriptor *next, 30 void *read_addr, 31 void *write_addr, 32 u16 length_or_eop, 33 int generate_eop, 34 int read_fixed, 35 int write_fixed_or_sop) 36{ 37 u8 val; 38 39 /* 40 * Mark the "next" descriptor as "not" owned by hardware. This prevents 41 * The SGDMA controller from continuing to process the chain. 42 */ 43 next->descriptor_control = next->descriptor_control & 44 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; 45 46 memset(desc, 0, sizeof(struct alt_sgdma_descriptor)); 47 desc->source = virt_to_phys(read_addr); 48 desc->destination = virt_to_phys(write_addr); 49 desc->next = virt_to_phys(next); 50 desc->bytes_to_transfer = length_or_eop; 51 52 /* 53 * Set the descriptor control block as follows: 54 * - Set "owned by hardware" bit 55 * - Optionally set "generate EOP" bit 56 * - Optionally set the "read from fixed address" bit 57 * - Optionally set the "write to fixed address bit (which serves 58 * serves as a "generate SOP" control bit in memory-to-stream mode). 59 * - Set the 4-bit atlantic channel, if specified 60 * 61 * Note this step is performed after all other descriptor information 62 * has been filled out so that, if the controller already happens to be 63 * pointing at this descriptor, it will not run (via the "owned by 64 * hardware" bit) until all other descriptor has been set up. 65 */ 66 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; 67 if (generate_eop) 68 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK; 69 if (read_fixed) 70 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK; 71 if (write_fixed_or_sop) 72 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK; 73 desc->descriptor_control = val; 74} 75 76static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs) 77{ 78 int status; 79 ulong ctime; 80 81 /* Wait for the descriptor (chain) to complete */ 82 ctime = get_timer(0); 83 while (1) { 84 status = readl(®s->status); 85 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK)) 86 break; 87 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { 88 status = -ETIMEDOUT; 89 debug("sgdma timeout\n"); 90 break; 91 } 92 } 93 94 /* Clear Run */ 95 writel(0, ®s->control); 96 /* Clear status */ 97 writel(0xff, ®s->status); 98 99 return status; 100} 101 102static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs, 103 struct alt_sgdma_descriptor *desc) 104{ 105 u32 val; 106 107 /* Point the controller at the descriptor */ 108 writel(virt_to_phys(desc), ®s->next_descriptor_pointer); 109 110 /* 111 * Set up SGDMA controller to: 112 * - Disable interrupt generation 113 * - Run once a valid descriptor is written to controller 114 * - Stop on an error with any particular descriptor 115 */ 116 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK; 117 writel(val, ®s->control); 118 119 return 0; 120} 121 122static void tse_adjust_link(struct altera_tse_priv *priv, 123 struct phy_device *phydev) 124{ 125 struct alt_tse_mac *mac_dev = priv->mac_dev; 126 u32 refvar; 127 128 if (!phydev->link) { 129 debug("%s: No link.\n", phydev->dev->name); 130 return; 131 } 132 133 refvar = readl(&mac_dev->command_config); 134 135 if (phydev->duplex) 136 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; 137 else 138 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; 139 140 switch (phydev->speed) { 141 case 1000: 142 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; 143 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 144 break; 145 case 100: 146 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 147 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 148 break; 149 case 10: 150 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 151 refvar |= ALTERA_TSE_CMD_ENA_10_MSK; 152 break; 153 } 154 writel(refvar, &mac_dev->command_config); 155} 156 157static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length) 158{ 159 struct altera_tse_priv *priv = dev_get_priv(dev); 160 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; 161 162 alt_sgdma_construct_descriptor( 163 tx_desc, 164 tx_desc + 1, 165 packet, /* read addr */ 166 NULL, /* write addr */ 167 length, /* length or EOP ,will change for each tx */ 168 1, /* gen eop */ 169 0, /* read fixed */ 170 1 /* write fixed or sop */ 171 ); 172 173 /* send the packet */ 174 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc); 175 alt_sgdma_wait_transfer(priv->sgdma_tx); 176 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred); 177 178 return tx_desc->actual_bytes_transferred; 179} 180 181static int altera_tse_recv_sgdma(struct udevice *dev, int flags, 182 uchar **packetp) 183{ 184 struct altera_tse_priv *priv = dev_get_priv(dev); 185 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 186 int packet_length; 187 188 if (rx_desc->descriptor_status & 189 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { 190 alt_sgdma_wait_transfer(priv->sgdma_rx); 191 packet_length = rx_desc->actual_bytes_transferred; 192 debug("recv %d bytes\n", packet_length); 193 *packetp = priv->rx_buf; 194 195 return packet_length; 196 } 197 198 return -EAGAIN; 199} 200 201static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet, 202 int length) 203{ 204 struct altera_tse_priv *priv = dev_get_priv(dev); 205 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 206 207 alt_sgdma_construct_descriptor( 208 rx_desc, 209 rx_desc + 1, 210 NULL, /* read addr */ 211 priv->rx_buf, /* write addr */ 212 0, /* length or EOP */ 213 0, /* gen eop */ 214 0, /* read fixed */ 215 0 /* write fixed or sop */ 216 ); 217 218 /* setup the sgdma */ 219 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc); 220 debug("recv setup\n"); 221 222 return 0; 223} 224 225static void altera_tse_stop_mac(struct altera_tse_priv *priv) 226{ 227 struct alt_tse_mac *mac_dev = priv->mac_dev; 228 u32 status; 229 ulong ctime; 230 231 /* reset the mac */ 232 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); 233 ctime = get_timer(0); 234 while (1) { 235 status = readl(&mac_dev->command_config); 236 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) 237 break; 238 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { 239 debug("Reset mac timeout\n"); 240 break; 241 } 242 } 243} 244 245static void altera_tse_stop_sgdma(struct udevice *dev) 246{ 247 struct altera_tse_priv *priv = dev_get_priv(dev); 248 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; 249 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 250 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 251 int ret; 252 253 /* clear rx desc & wait for sgdma to complete */ 254 rx_desc->descriptor_control = 0; 255 writel(0, &rx_sgdma->control); 256 ret = alt_sgdma_wait_transfer(rx_sgdma); 257 if (ret == -ETIMEDOUT) 258 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, 259 &rx_sgdma->control); 260 261 writel(0, &tx_sgdma->control); 262 ret = alt_sgdma_wait_transfer(tx_sgdma); 263 if (ret == -ETIMEDOUT) 264 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, 265 &tx_sgdma->control); 266} 267 268static void msgdma_reset(struct msgdma_csr *csr) 269{ 270 u32 status; 271 ulong ctime; 272 273 /* Reset mSGDMA */ 274 writel(MSGDMA_CSR_STAT_MASK, &csr->status); 275 writel(MSGDMA_CSR_CTL_RESET, &csr->control); 276 ctime = get_timer(0); 277 while (1) { 278 status = readl(&csr->status); 279 if (!(status & MSGDMA_CSR_STAT_RESETTING)) 280 break; 281 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { 282 debug("Reset msgdma timeout\n"); 283 break; 284 } 285 } 286 /* Clear status */ 287 writel(MSGDMA_CSR_STAT_MASK, &csr->status); 288} 289 290static u32 msgdma_wait(struct msgdma_csr *csr) 291{ 292 u32 status; 293 ulong ctime; 294 295 /* Wait for the descriptor to complete */ 296 ctime = get_timer(0); 297 while (1) { 298 status = readl(&csr->status); 299 if (!(status & MSGDMA_CSR_STAT_BUSY)) 300 break; 301 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { 302 debug("sgdma timeout\n"); 303 break; 304 } 305 } 306 /* Clear status */ 307 writel(MSGDMA_CSR_STAT_MASK, &csr->status); 308 309 return status; 310} 311 312static int altera_tse_send_msgdma(struct udevice *dev, void *packet, 313 int length) 314{ 315 struct altera_tse_priv *priv = dev_get_priv(dev); 316 struct msgdma_extended_desc *desc = priv->tx_desc; 317 u32 tx_buf = virt_to_phys(packet); 318 u32 status; 319 320 writel(tx_buf, &desc->read_addr_lo); 321 writel(0, &desc->read_addr_hi); 322 writel(0, &desc->write_addr_lo); 323 writel(0, &desc->write_addr_hi); 324 writel(length, &desc->len); 325 writel(0, &desc->burst_seq_num); 326 writel(MSGDMA_DESC_TX_STRIDE, &desc->stride); 327 writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control); 328 status = msgdma_wait(priv->sgdma_tx); 329 debug("sent %d bytes, status %08x\n", length, status); 330 331 return 0; 332} 333 334static int altera_tse_recv_msgdma(struct udevice *dev, int flags, 335 uchar **packetp) 336{ 337 struct altera_tse_priv *priv = dev_get_priv(dev); 338 struct msgdma_csr *csr = priv->sgdma_rx; 339 struct msgdma_response *resp = priv->rx_resp; 340 u32 level, length, status; 341 342 level = readl(&csr->resp_fill_level); 343 if (level & 0xffff) { 344 length = readl(&resp->bytes_transferred); 345 status = readl(&resp->status); 346 debug("recv %d bytes, status %08x\n", length, status); 347 *packetp = priv->rx_buf; 348 349 return length; 350 } 351 352 return -EAGAIN; 353} 354 355static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet, 356 int length) 357{ 358 struct altera_tse_priv *priv = dev_get_priv(dev); 359 struct msgdma_extended_desc *desc = priv->rx_desc; 360 u32 rx_buf = virt_to_phys(priv->rx_buf); 361 362 writel(0, &desc->read_addr_lo); 363 writel(0, &desc->read_addr_hi); 364 writel(rx_buf, &desc->write_addr_lo); 365 writel(0, &desc->write_addr_hi); 366 writel(PKTSIZE_ALIGN, &desc->len); 367 writel(0, &desc->burst_seq_num); 368 writel(MSGDMA_DESC_RX_STRIDE, &desc->stride); 369 writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control); 370 debug("recv setup\n"); 371 372 return 0; 373} 374 375static void altera_tse_stop_msgdma(struct udevice *dev) 376{ 377 struct altera_tse_priv *priv = dev_get_priv(dev); 378 379 msgdma_reset(priv->sgdma_rx); 380 msgdma_reset(priv->sgdma_tx); 381} 382 383static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 384{ 385 struct altera_tse_priv *priv = bus->priv; 386 struct alt_tse_mac *mac_dev = priv->mac_dev; 387 u32 value; 388 389 /* set mdio address */ 390 writel(addr, &mac_dev->mdio_phy1_addr); 391 /* get the data */ 392 value = readl(&mac_dev->mdio_phy1[reg]); 393 394 return value & 0xffff; 395} 396 397static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 398 u16 val) 399{ 400 struct altera_tse_priv *priv = bus->priv; 401 struct alt_tse_mac *mac_dev = priv->mac_dev; 402 403 /* set mdio address */ 404 writel(addr, &mac_dev->mdio_phy1_addr); 405 /* set the data */ 406 writel(val, &mac_dev->mdio_phy1[reg]); 407 408 return 0; 409} 410 411static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) 412{ 413 struct mii_dev *bus = mdio_alloc(); 414 415 if (!bus) { 416 printf("Failed to allocate MDIO bus\n"); 417 return -ENOMEM; 418 } 419 420 bus->read = tse_mdio_read; 421 bus->write = tse_mdio_write; 422 snprintf(bus->name, sizeof(bus->name), "%s", name); 423 424 bus->priv = (void *)priv; 425 426 return mdio_register(bus); 427} 428 429static int tse_phy_init(struct altera_tse_priv *priv, void *dev) 430{ 431 struct phy_device *phydev; 432 433 phydev = phy_connect(priv->bus, -1, dev, priv->interface); 434 if (!phydev) 435 return -ENODEV; 436 437 phydev->supported &= PHY_GBIT_FEATURES; 438 phydev->advertising = phydev->supported; 439 440 priv->phydev = phydev; 441 phy_config(phydev); 442 443 return 0; 444} 445 446static int altera_tse_write_hwaddr(struct udevice *dev) 447{ 448 struct altera_tse_priv *priv = dev_get_priv(dev); 449 struct alt_tse_mac *mac_dev = priv->mac_dev; 450 struct eth_pdata *pdata = dev_get_plat(dev); 451 u8 *hwaddr = pdata->enetaddr; 452 u32 mac_lo, mac_hi; 453 454 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) | 455 (hwaddr[1] << 8) | hwaddr[0]; 456 mac_hi = (hwaddr[5] << 8) | hwaddr[4]; 457 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo); 458 459 writel(mac_lo, &mac_dev->mac_addr_0); 460 writel(mac_hi, &mac_dev->mac_addr_1); 461 writel(mac_lo, &mac_dev->supp_mac_addr_0_0); 462 writel(mac_hi, &mac_dev->supp_mac_addr_0_1); 463 writel(mac_lo, &mac_dev->supp_mac_addr_1_0); 464 writel(mac_hi, &mac_dev->supp_mac_addr_1_1); 465 writel(mac_lo, &mac_dev->supp_mac_addr_2_0); 466 writel(mac_hi, &mac_dev->supp_mac_addr_2_1); 467 writel(mac_lo, &mac_dev->supp_mac_addr_3_0); 468 writel(mac_hi, &mac_dev->supp_mac_addr_3_1); 469 470 return 0; 471} 472 473static int altera_tse_send(struct udevice *dev, void *packet, int length) 474{ 475 struct altera_tse_priv *priv = dev_get_priv(dev); 476 unsigned long tx_buf = (unsigned long)packet; 477 478 flush_dcache_range(tx_buf, tx_buf + length); 479 480 return priv->ops->send(dev, packet, length); 481} 482 483static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) 484{ 485 struct altera_tse_priv *priv = dev_get_priv(dev); 486 487 return priv->ops->recv(dev, flags, packetp); 488} 489 490static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, 491 int length) 492{ 493 struct altera_tse_priv *priv = dev_get_priv(dev); 494 unsigned long rx_buf = (unsigned long)priv->rx_buf; 495 496 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); 497 498 return priv->ops->free_pkt(dev, packet, length); 499} 500 501static void altera_tse_stop(struct udevice *dev) 502{ 503 struct altera_tse_priv *priv = dev_get_priv(dev); 504 505 priv->ops->stop(dev); 506 altera_tse_stop_mac(priv); 507} 508 509static int altera_tse_start(struct udevice *dev) 510{ 511 struct altera_tse_priv *priv = dev_get_priv(dev); 512 struct alt_tse_mac *mac_dev = priv->mac_dev; 513 u32 val; 514 int ret; 515 516 /* need to create sgdma */ 517 debug("Configuring rx desc\n"); 518 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN); 519 /* start TSE */ 520 debug("Configuring TSE Mac\n"); 521 /* Initialize MAC registers */ 522 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length); 523 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold); 524 writel(0, &mac_dev->rx_sel_full_threshold); 525 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold); 526 writel(0, &mac_dev->tx_sel_full_threshold); 527 writel(8, &mac_dev->rx_almost_empty_threshold); 528 writel(8, &mac_dev->rx_almost_full_threshold); 529 writel(8, &mac_dev->tx_almost_empty_threshold); 530 writel(3, &mac_dev->tx_almost_full_threshold); 531 532 /* NO Shift */ 533 writel(0, &mac_dev->rx_cmd_stat); 534 writel(0, &mac_dev->tx_cmd_stat); 535 536 /* enable MAC */ 537 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; 538 writel(val, &mac_dev->command_config); 539 540 /* Start up the PHY */ 541 ret = phy_startup(priv->phydev); 542 if (ret) { 543 debug("Could not initialize PHY %s\n", 544 priv->phydev->dev->name); 545 return ret; 546 } 547 548 tse_adjust_link(priv, priv->phydev); 549 550 if (!priv->phydev->link) 551 return -EIO; 552 553 return 0; 554} 555 556static const struct tse_ops tse_sgdma_ops = { 557 .send = altera_tse_send_sgdma, 558 .recv = altera_tse_recv_sgdma, 559 .free_pkt = altera_tse_free_pkt_sgdma, 560 .stop = altera_tse_stop_sgdma, 561}; 562 563static const struct tse_ops tse_msgdma_ops = { 564 .send = altera_tse_send_msgdma, 565 .recv = altera_tse_recv_msgdma, 566 .free_pkt = altera_tse_free_pkt_msgdma, 567 .stop = altera_tse_stop_msgdma, 568}; 569 570static int altera_tse_probe(struct udevice *dev) 571{ 572 struct eth_pdata *pdata = dev_get_plat(dev); 573 struct altera_tse_priv *priv = dev_get_priv(dev); 574 void *blob = (void *)gd->fdt_blob; 575 int node = dev_of_offset(dev); 576 const char *list, *end; 577 const fdt32_t *cell; 578 void *base, *desc_mem = NULL; 579 unsigned long addr, size; 580 int parent, addrc, sizec; 581 int len, idx; 582 int ret; 583 584 priv->dma_type = dev_get_driver_data(dev); 585 if (priv->dma_type == ALT_SGDMA) 586 priv->ops = &tse_sgdma_ops; 587 else 588 priv->ops = &tse_msgdma_ops; 589 /* 590 * decode regs. there are multiple reg tuples, and they need to 591 * match with reg-names. 592 */ 593 parent = fdt_parent_offset(blob, node); 594 fdt_support_default_count_cells(blob, parent, &addrc, &sizec); 595 list = fdt_getprop(blob, node, "reg-names", &len); 596 if (!list) 597 return -ENOENT; 598 end = list + len; 599 cell = fdt_getprop(blob, node, "reg", &len); 600 if (!cell) 601 return -ENOENT; 602 idx = 0; 603 while (list < end) { 604 addr = fdt_translate_address((void *)blob, 605 node, cell + idx); 606 size = fdt_addr_to_cpu(cell[idx + addrc]); 607 base = map_physmem(addr, size, MAP_NOCACHE); 608 len = strlen(list); 609 if (strcmp(list, "control_port") == 0) 610 priv->mac_dev = base; 611 else if (strcmp(list, "rx_csr") == 0) 612 priv->sgdma_rx = base; 613 else if (strcmp(list, "rx_desc") == 0) 614 priv->rx_desc = base; 615 else if (strcmp(list, "rx_resp") == 0) 616 priv->rx_resp = base; 617 else if (strcmp(list, "tx_csr") == 0) 618 priv->sgdma_tx = base; 619 else if (strcmp(list, "tx_desc") == 0) 620 priv->tx_desc = base; 621 else if (strcmp(list, "s1") == 0) 622 desc_mem = base; 623 idx += addrc + sizec; 624 list += (len + 1); 625 } 626 /* decode fifo depth */ 627 priv->rx_fifo_depth = fdtdec_get_int(blob, node, 628 "rx-fifo-depth", 0); 629 priv->tx_fifo_depth = fdtdec_get_int(blob, node, 630 "tx-fifo-depth", 0); 631 /* decode phy */ 632 addr = fdtdec_get_int(blob, node, 633 "phy-handle", 0); 634 addr = fdt_node_offset_by_phandle(blob, addr); 635 priv->phyaddr = fdtdec_get_int(blob, addr, 636 "reg", 0); 637 /* init desc */ 638 if (priv->dma_type == ALT_SGDMA) { 639 len = sizeof(struct alt_sgdma_descriptor) * 4; 640 if (!desc_mem) { 641 desc_mem = dma_alloc_coherent(len, &addr); 642 if (!desc_mem) 643 return -ENOMEM; 644 } 645 memset(desc_mem, 0, len); 646 priv->tx_desc = desc_mem; 647 priv->rx_desc = priv->tx_desc + 648 2 * sizeof(struct alt_sgdma_descriptor); 649 } 650 /* allocate recv packet buffer */ 651 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN); 652 if (!priv->rx_buf) 653 return -ENOMEM; 654 655 /* stop controller */ 656 debug("Reset TSE & SGDMAs\n"); 657 altera_tse_stop(dev); 658 659 /* start the phy */ 660 priv->interface = pdata->phy_interface; 661 tse_mdio_init(dev->name, priv); 662 priv->bus = miiphy_get_dev_by_name(dev->name); 663 664 ret = tse_phy_init(priv, dev); 665 666 return ret; 667} 668 669static int altera_tse_of_to_plat(struct udevice *dev) 670{ 671 struct eth_pdata *pdata = dev_get_plat(dev); 672 673 pdata->phy_interface = dev_read_phy_mode(dev); 674 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) 675 return -EINVAL; 676 677 return 0; 678} 679 680static const struct eth_ops altera_tse_ops = { 681 .start = altera_tse_start, 682 .send = altera_tse_send, 683 .recv = altera_tse_recv, 684 .free_pkt = altera_tse_free_pkt, 685 .stop = altera_tse_stop, 686 .write_hwaddr = altera_tse_write_hwaddr, 687}; 688 689static const struct udevice_id altera_tse_ids[] = { 690 { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA }, 691 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA }, 692 {} 693}; 694 695U_BOOT_DRIVER(altera_tse) = { 696 .name = "altera_tse", 697 .id = UCLASS_ETH, 698 .of_match = altera_tse_ids, 699 .ops = &altera_tse_ops, 700 .of_to_plat = altera_tse_of_to_plat, 701 .plat_auto = sizeof(struct eth_pdata), 702 .priv_auto = sizeof(struct altera_tse_priv), 703 .probe = altera_tse_probe, 704}; 705