1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> 5 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de 6 * (C) Copyright 2006 DENX Software Engineering 7 */ 8 9#include <common.h> 10#include <log.h> 11#include <asm/global_data.h> 12#include <asm/io.h> 13#include <memalign.h> 14#include <nand.h> 15#include <asm/arch/clock.h> 16#include <asm/arch/funcmux.h> 17#include <asm/arch-tegra/clk_rst.h> 18#include <dm/device_compat.h> 19#include <linux/bug.h> 20#include <linux/delay.h> 21#include <linux/errno.h> 22#include <linux/mtd/rawnand.h> 23#include <asm/gpio.h> 24#include <fdtdec.h> 25#include <bouncebuf.h> 26#include <dm.h> 27#include <linux/printk.h> 28#include "tegra_nand.h" 29 30DECLARE_GLOBAL_DATA_PTR; 31 32#define NAND_CMD_TIMEOUT_MS 10 33 34#define SKIPPED_SPARE_BYTES 4 35 36/* ECC bytes to be generated for tag data */ 37#define TAG_ECC_BYTES 4 38 39static const struct udevice_id tegra_nand_dt_ids[] = { 40 { 41 .compatible = "nvidia,tegra20-nand", 42 }, 43 { /* sentinel */ } 44}; 45 46/* 64 byte oob block info for large page (== 2KB) device 47 * 48 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC: 49 * Skipped bytes(4) 50 * Main area Ecc(36) 51 * Tag data(20) 52 * Tag data Ecc(4) 53 * 54 * Yaffs2 will use 16 tag bytes. 55 */ 56static struct nand_ecclayout eccoob = { 57 .eccbytes = 36, 58 .eccpos = { 59 4, 5, 6, 7, 8, 9, 10, 11, 12, 60 13, 14, 15, 16, 17, 18, 19, 20, 21, 61 22, 23, 24, 25, 26, 27, 28, 29, 30, 62 31, 32, 33, 34, 35, 36, 37, 38, 39, 63 }, 64 .oobavail = 20, 65 .oobfree = { 66 { 67 .offset = 40, 68 .length = 20, 69 }, 70 } 71}; 72 73enum { 74 ECC_OK, 75 ECC_TAG_ERROR = 1 << 0, 76 ECC_DATA_ERROR = 1 << 1 77}; 78 79/* Timing parameters */ 80enum { 81 FDT_NAND_MAX_TRP_TREA, 82 FDT_NAND_TWB, 83 FDT_NAND_MAX_TCR_TAR_TRR, 84 FDT_NAND_TWHR, 85 FDT_NAND_MAX_TCS_TCH_TALS_TALH, 86 FDT_NAND_TWH, 87 FDT_NAND_TWP, 88 FDT_NAND_TRH, 89 FDT_NAND_TADL, 90 91 FDT_NAND_TIMING_COUNT 92}; 93 94/* Information about an attached NAND chip */ 95struct fdt_nand { 96 struct nand_ctlr *reg; 97 int enabled; /* 1 to enable, 0 to disable */ 98 struct gpio_desc wp_gpio; /* write-protect GPIO */ 99 s32 width; /* bit width, normally 8 */ 100 u32 timing[FDT_NAND_TIMING_COUNT]; 101}; 102 103struct nand_drv { 104 struct nand_ctlr *reg; 105 struct fdt_nand config; 106}; 107 108struct tegra_nand_info { 109 struct udevice *dev; 110 struct nand_drv nand_ctrl; 111 struct nand_chip nand_chip; 112}; 113 114/** 115 * Wait for command completion 116 * 117 * @param reg nand_ctlr structure 118 * @return 119 * 1 - Command completed 120 * 0 - Timeout 121 */ 122static int nand_waitfor_cmd_completion(struct nand_ctlr *reg) 123{ 124 u32 reg_val; 125 int running; 126 int i; 127 128 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) { 129 if ((readl(®->command) & CMD_GO) || 130 !(readl(®->status) & STATUS_RBSY0) || 131 !(readl(®->isr) & ISR_IS_CMD_DONE)) { 132 udelay(1); 133 continue; 134 } 135 reg_val = readl(®->dma_mst_ctrl); 136 /* 137 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE 138 * is set, that means DMA engine is running. 139 * 140 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE 141 * is cleared, indicating DMA transfer completion. 142 */ 143 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | 144 DMA_MST_CTRL_EN_B_ENABLE); 145 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) 146 return 1; 147 udelay(1); 148 } 149 return 0; 150} 151 152/** 153 * Read one byte from the chip 154 * 155 * @param mtd MTD device structure 156 * Return: data byte 157 * 158 * Read function for 8bit bus-width 159 */ 160static uint8_t read_byte(struct mtd_info *mtd) 161{ 162 struct nand_chip *chip = mtd_to_nand(mtd); 163 struct nand_drv *info; 164 165 info = (struct nand_drv *)nand_get_controller_data(chip); 166 167 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID, 168 &info->reg->command); 169 if (!nand_waitfor_cmd_completion(info->reg)) 170 printf("Command timeout\n"); 171 172 return (uint8_t)readl(&info->reg->resp); 173} 174 175/** 176 * Read len bytes from the chip into a buffer 177 * 178 * @param mtd MTD device structure 179 * @param buf buffer to store data to 180 * @param len number of bytes to read 181 * 182 * Read function for 8bit bus-width 183 */ 184static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 185{ 186 int i, s; 187 unsigned int reg; 188 struct nand_chip *chip = mtd_to_nand(mtd); 189 struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip); 190 191 for (i = 0; i < len; i += 4) { 192 s = (len - i) > 4 ? 4 : len - i; 193 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 | 194 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO, 195 &info->reg->command); 196 if (!nand_waitfor_cmd_completion(info->reg)) 197 puts("Command timeout during read_buf\n"); 198 reg = readl(&info->reg->resp); 199 memcpy(buf + i, ®, s); 200 } 201} 202 203/** 204 * Check NAND status to see if it is ready or not 205 * 206 * @param mtd MTD device structure 207 * @return 208 * 1 - ready 209 * 0 - not ready 210 */ 211static int nand_dev_ready(struct mtd_info *mtd) 212{ 213 struct nand_chip *chip = mtd_to_nand(mtd); 214 int reg_val; 215 struct nand_drv *info; 216 217 info = (struct nand_drv *)nand_get_controller_data(chip); 218 219 reg_val = readl(&info->reg->status); 220 if (reg_val & STATUS_RBSY0) 221 return 1; 222 else 223 return 0; 224} 225 226/* Dummy implementation: we don't support multiple chips */ 227static void nand_select_chip(struct mtd_info *mtd, int chipnr) 228{ 229 switch (chipnr) { 230 case -1: 231 case 0: 232 break; 233 234 default: 235 BUG(); 236 } 237} 238 239/** 240 * Clear all interrupt status bits 241 * 242 * @param reg nand_ctlr structure 243 */ 244static void nand_clear_interrupt_status(struct nand_ctlr *reg) 245{ 246 u32 reg_val; 247 248 /* Clear interrupt status */ 249 reg_val = readl(®->isr); 250 writel(reg_val, ®->isr); 251} 252 253/** 254 * Send command to NAND device 255 * 256 * @param mtd MTD device structure 257 * @param command the command to be sent 258 * @param column the column address for this command, -1 if none 259 * @param page_addr the page address for this command, -1 if none 260 */ 261static void nand_command(struct mtd_info *mtd, unsigned int command, 262 int column, int page_addr) 263{ 264 struct nand_chip *chip = mtd_to_nand(mtd); 265 struct nand_drv *info; 266 267 info = (struct nand_drv *)nand_get_controller_data(chip); 268 269 /* 270 * Write out the command to the device. 271 * 272 * Only command NAND_CMD_RESET or NAND_CMD_READID will come 273 * here before mtd->writesize is initialized. 274 */ 275 276 /* Emulate NAND_CMD_READOOB */ 277 if (command == NAND_CMD_READOOB) { 278 assert(mtd->writesize != 0); 279 column += mtd->writesize; 280 command = NAND_CMD_READ0; 281 } 282 283 /* Adjust columns for 16 bit bus-width */ 284 if (column != -1 && (chip->options & NAND_BUSWIDTH_16)) 285 column >>= 1; 286 287 nand_clear_interrupt_status(info->reg); 288 289 /* Stop DMA engine, clear DMA completion status */ 290 writel(DMA_MST_CTRL_EN_A_DISABLE 291 | DMA_MST_CTRL_EN_B_DISABLE 292 | DMA_MST_CTRL_IS_DMA_DONE, 293 &info->reg->dma_mst_ctrl); 294 295 /* 296 * Program and erase have their own busy handlers 297 * status and sequential in needs no delay 298 */ 299 switch (command) { 300 case NAND_CMD_READID: 301 writel(NAND_CMD_READID, &info->reg->cmd_reg1); 302 writel(column & 0xFF, &info->reg->addr_reg1); 303 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, 304 &info->reg->command); 305 break; 306 case NAND_CMD_PARAM: 307 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1); 308 writel(column & 0xFF, &info->reg->addr_reg1); 309 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, 310 &info->reg->command); 311 break; 312 case NAND_CMD_READ0: 313 writel(NAND_CMD_READ0, &info->reg->cmd_reg1); 314 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2); 315 writel((page_addr << 16) | (column & 0xFFFF), 316 &info->reg->addr_reg1); 317 writel(page_addr >> 16, &info->reg->addr_reg2); 318 return; 319 case NAND_CMD_SEQIN: 320 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1); 321 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2); 322 writel((page_addr << 16) | (column & 0xFFFF), 323 &info->reg->addr_reg1); 324 writel(page_addr >> 16, 325 &info->reg->addr_reg2); 326 return; 327 case NAND_CMD_PAGEPROG: 328 return; 329 case NAND_CMD_ERASE1: 330 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1); 331 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2); 332 writel(page_addr, &info->reg->addr_reg1); 333 writel(CMD_GO | CMD_CLE | CMD_ALE | 334 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3, 335 &info->reg->command); 336 break; 337 case NAND_CMD_ERASE2: 338 return; 339 case NAND_CMD_STATUS: 340 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1); 341 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX 342 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT) 343 | CMD_CE0, 344 &info->reg->command); 345 break; 346 case NAND_CMD_RESET: 347 writel(NAND_CMD_RESET, &info->reg->cmd_reg1); 348 writel(CMD_GO | CMD_CLE | CMD_CE0, 349 &info->reg->command); 350 break; 351 case NAND_CMD_RNDOUT: 352 default: 353 printf("%s: Unsupported command %d\n", __func__, command); 354 return; 355 } 356 if (!nand_waitfor_cmd_completion(info->reg)) 357 printf("Command 0x%02X timeout\n", command); 358} 359 360/** 361 * Check whether the pointed buffer are all 0xff (blank). 362 * 363 * @param buf data buffer for blank check 364 * @param len length of the buffer in byte 365 * @return 366 * 1 - blank 367 * 0 - non-blank 368 */ 369static int blank_check(u8 *buf, int len) 370{ 371 int i; 372 373 for (i = 0; i < len; i++) 374 if (buf[i] != 0xFF) 375 return 0; 376 return 1; 377} 378 379/** 380 * After a DMA transfer for read, we call this function to see whether there 381 * is any uncorrectable error on the pointed data buffer or oob buffer. 382 * 383 * @param reg nand_ctlr structure 384 * @param databuf data buffer 385 * @param a_len data buffer length 386 * @param oobbuf oob buffer 387 * @param b_len oob buffer length 388 * @return 389 * ECC_OK - no ECC error or correctable ECC error 390 * ECC_TAG_ERROR - uncorrectable tag ECC error 391 * ECC_DATA_ERROR - uncorrectable data ECC error 392 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error 393 */ 394static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf, 395 int a_len, u8 *oobbuf, int b_len) 396{ 397 int return_val = ECC_OK; 398 u32 reg_val; 399 400 if (!(readl(®->isr) & ISR_IS_ECC_ERR)) 401 return ECC_OK; 402 403 /* 404 * Area A is used for the data block (databuf). Area B is used for 405 * the spare block (oobbuf) 406 */ 407 reg_val = readl(®->dec_status); 408 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) { 409 reg_val = readl(®->bch_dec_status_buf); 410 /* 411 * If uncorrectable error occurs on data area, then see whether 412 * they are all FF. If all are FF, it's a blank page. 413 * Not error. 414 */ 415 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) && 416 !blank_check(databuf, a_len)) 417 return_val |= ECC_DATA_ERROR; 418 } 419 420 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) { 421 reg_val = readl(®->bch_dec_status_buf); 422 /* 423 * If uncorrectable error occurs on tag area, then see whether 424 * they are all FF. If all are FF, it's a blank page. 425 * Not error. 426 */ 427 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) && 428 !blank_check(oobbuf, b_len)) 429 return_val |= ECC_TAG_ERROR; 430 } 431 432 return return_val; 433} 434 435/** 436 * Set GO bit to send command to device 437 * 438 * @param reg nand_ctlr structure 439 */ 440static void start_command(struct nand_ctlr *reg) 441{ 442 u32 reg_val; 443 444 reg_val = readl(®->command); 445 reg_val |= CMD_GO; 446 writel(reg_val, ®->command); 447} 448 449/** 450 * Clear command GO bit, DMA GO bit, and DMA completion status 451 * 452 * @param reg nand_ctlr structure 453 */ 454static void stop_command(struct nand_ctlr *reg) 455{ 456 /* Stop command */ 457 writel(0, ®->command); 458 459 /* Stop DMA engine and clear DMA completion status */ 460 writel(DMA_MST_CTRL_GO_DISABLE 461 | DMA_MST_CTRL_IS_DMA_DONE, 462 ®->dma_mst_ctrl); 463} 464 465/** 466 * Set up NAND bus width and page size 467 * 468 * @param info nand_info structure 469 * @param *reg_val address of reg_val 470 * Return: 0 if ok, -1 on error 471 */ 472static int set_bus_width_page_size(struct mtd_info *our_mtd, 473 struct fdt_nand *config, u32 *reg_val) 474{ 475 if (config->width == 8) 476 *reg_val = CFG_BUS_WIDTH_8BIT; 477 else if (config->width == 16) 478 *reg_val = CFG_BUS_WIDTH_16BIT; 479 else { 480 debug("%s: Unsupported bus width %d\n", __func__, 481 config->width); 482 return -1; 483 } 484 485 if (our_mtd->writesize == 512) 486 *reg_val |= CFG_PAGE_SIZE_512; 487 else if (our_mtd->writesize == 2048) 488 *reg_val |= CFG_PAGE_SIZE_2048; 489 else if (our_mtd->writesize == 4096) 490 *reg_val |= CFG_PAGE_SIZE_4096; 491 else { 492 debug("%s: Unsupported page size %d\n", __func__, 493 our_mtd->writesize); 494 return -1; 495 } 496 497 return 0; 498} 499 500/** 501 * Page read/write function 502 * 503 * @param mtd mtd info structure 504 * @param chip nand chip info structure 505 * @param buf data buffer 506 * @param page page number 507 * @param with_ecc 1 to enable ECC, 0 to disable ECC 508 * @param is_writing 0 for read, 1 for write 509 * Return: 0 when successfully completed 510 * -EIO when command timeout 511 */ 512static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip, 513 uint8_t *buf, int page, int with_ecc, int is_writing) 514{ 515 u32 reg_val; 516 int tag_size; 517 struct nand_oobfree *free = chip->ecc.layout->oobfree; 518 /* 4*128=512 (byte) is the value that our HW can support. */ 519 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128); 520 char *tag_ptr; 521 struct nand_drv *info; 522 struct fdt_nand *config; 523 unsigned int bbflags; 524 struct bounce_buffer bbstate, bbstate_oob; 525 526 if ((uintptr_t)buf & 0x03) { 527 printf("buf %p has to be 4-byte aligned\n", buf); 528 return -EINVAL; 529 } 530 531 info = (struct nand_drv *)nand_get_controller_data(chip); 532 config = &info->config; 533 if (set_bus_width_page_size(mtd, config, ®_val)) 534 return -EINVAL; 535 536 /* Need to be 4-byte aligned */ 537 tag_ptr = (char *)tag_buf; 538 539 stop_command(info->reg); 540 541 if (is_writing) 542 bbflags = GEN_BB_READ; 543 else 544 bbflags = GEN_BB_WRITE; 545 546 bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift, 547 bbflags); 548 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a); 549 writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr); 550 551 /* Set ECC selection, configure ECC settings */ 552 if (with_ecc) { 553 if (is_writing) 554 memcpy(tag_ptr, chip->oob_poi + free->offset, 555 chip->ecc.layout->oobavail + TAG_ECC_BYTES); 556 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES; 557 reg_val |= (CFG_SKIP_SPARE_SEL_4 558 | CFG_SKIP_SPARE_ENABLE 559 | CFG_HW_ECC_CORRECTION_ENABLE 560 | CFG_ECC_EN_TAG_DISABLE 561 | CFG_HW_ECC_SEL_RS 562 | CFG_HW_ECC_ENABLE 563 | CFG_TVAL4 564 | (tag_size - 1)); 565 566 if (!is_writing) 567 tag_size += SKIPPED_SPARE_BYTES; 568 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size, 569 bbflags); 570 } else { 571 tag_size = mtd->oobsize; 572 reg_val |= (CFG_SKIP_SPARE_DISABLE 573 | CFG_HW_ECC_CORRECTION_DISABLE 574 | CFG_ECC_EN_TAG_DISABLE 575 | CFG_HW_ECC_DISABLE 576 | (tag_size - 1)); 577 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, 578 tag_size, bbflags); 579 } 580 writel(reg_val, &info->reg->config); 581 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr); 582 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config); 583 writel(tag_size - 1, &info->reg->dma_cfg_b); 584 585 nand_clear_interrupt_status(info->reg); 586 587 reg_val = CMD_CLE | CMD_ALE 588 | CMD_SEC_CMD 589 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT) 590 | CMD_A_VALID 591 | CMD_B_VALID 592 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT) 593 | CMD_CE0; 594 if (!is_writing) 595 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); 596 else 597 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); 598 writel(reg_val, &info->reg->command); 599 600 /* Setup DMA engine */ 601 reg_val = DMA_MST_CTRL_GO_ENABLE 602 | DMA_MST_CTRL_BURST_8WORDS 603 | DMA_MST_CTRL_EN_A_ENABLE 604 | DMA_MST_CTRL_EN_B_ENABLE; 605 606 if (!is_writing) 607 reg_val |= DMA_MST_CTRL_DIR_READ; 608 else 609 reg_val |= DMA_MST_CTRL_DIR_WRITE; 610 611 writel(reg_val, &info->reg->dma_mst_ctrl); 612 613 start_command(info->reg); 614 615 if (!nand_waitfor_cmd_completion(info->reg)) { 616 if (!is_writing) 617 printf("Read Page 0x%X timeout ", page); 618 else 619 printf("Write Page 0x%X timeout ", page); 620 if (with_ecc) 621 printf("with ECC"); 622 else 623 printf("without ECC"); 624 printf("\n"); 625 return -EIO; 626 } 627 628 bounce_buffer_stop(&bbstate_oob); 629 bounce_buffer_stop(&bbstate); 630 631 if (with_ecc && !is_writing) { 632 memcpy(chip->oob_poi, tag_ptr, 633 SKIPPED_SPARE_BYTES); 634 memcpy(chip->oob_poi + free->offset, 635 tag_ptr + SKIPPED_SPARE_BYTES, 636 chip->ecc.layout->oobavail); 637 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf, 638 1 << chip->page_shift, 639 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES), 640 chip->ecc.layout->oobavail); 641 if (reg_val & ECC_TAG_ERROR) 642 printf("Read Page 0x%X tag ECC error\n", page); 643 if (reg_val & ECC_DATA_ERROR) 644 printf("Read Page 0x%X data ECC error\n", 645 page); 646 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR)) 647 return -EIO; 648 } 649 return 0; 650} 651 652/** 653 * Hardware ecc based page read function 654 * 655 * @param mtd mtd info structure 656 * @param chip nand chip info structure 657 * @param buf buffer to store read data 658 * @param page page number to read 659 * Return: 0 when successfully completed 660 * -EIO when command timeout 661 */ 662static int nand_read_page_hwecc(struct mtd_info *mtd, 663 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 664{ 665 return nand_rw_page(mtd, chip, buf, page, 1, 0); 666} 667 668/** 669 * Hardware ecc based page write function 670 * 671 * @param mtd mtd info structure 672 * @param chip nand chip info structure 673 * @param buf data buffer 674 */ 675static int nand_write_page_hwecc(struct mtd_info *mtd, 676 struct nand_chip *chip, const uint8_t *buf, int oob_required, 677 int page) 678{ 679 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1); 680 return 0; 681} 682 683 684/** 685 * Read raw page data without ecc 686 * 687 * @param mtd mtd info structure 688 * @param chip nand chip info structure 689 * @param buf buffer to store read data 690 * @param page page number to read 691 * Return: 0 when successfully completed 692 * -EINVAL when chip->oob_poi is not double-word aligned 693 * -EIO when command timeout 694 */ 695static int nand_read_page_raw(struct mtd_info *mtd, 696 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 697{ 698 return nand_rw_page(mtd, chip, buf, page, 0, 0); 699} 700 701/** 702 * Raw page write function 703 * 704 * @param mtd mtd info structure 705 * @param chip nand chip info structure 706 * @param buf data buffer 707 */ 708static int nand_write_page_raw(struct mtd_info *mtd, 709 struct nand_chip *chip, const uint8_t *buf, 710 int oob_required, int page) 711{ 712 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1); 713 return 0; 714} 715 716/** 717 * OOB data read/write function 718 * 719 * @param mtd mtd info structure 720 * @param chip nand chip info structure 721 * @param page page number to read 722 * @param with_ecc 1 to enable ECC, 0 to disable ECC 723 * @param is_writing 0 for read, 1 for write 724 * Return: 0 when successfully completed 725 * -EINVAL when chip->oob_poi is not double-word aligned 726 * -EIO when command timeout 727 */ 728static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip, 729 int page, int with_ecc, int is_writing) 730{ 731 u32 reg_val; 732 int tag_size; 733 struct nand_oobfree *free = chip->ecc.layout->oobfree; 734 struct nand_drv *info; 735 unsigned int bbflags; 736 struct bounce_buffer bbstate_oob; 737 738 if (((int)chip->oob_poi) & 0x03) 739 return -EINVAL; 740 info = (struct nand_drv *)nand_get_controller_data(chip); 741 if (set_bus_width_page_size(mtd, &info->config, ®_val)) 742 return -EINVAL; 743 744 stop_command(info->reg); 745 746 /* Set ECC selection */ 747 tag_size = mtd->oobsize; 748 if (with_ecc) 749 reg_val |= CFG_ECC_EN_TAG_ENABLE; 750 else 751 reg_val |= (CFG_ECC_EN_TAG_DISABLE); 752 753 reg_val |= ((tag_size - 1) | 754 CFG_SKIP_SPARE_DISABLE | 755 CFG_HW_ECC_CORRECTION_DISABLE | 756 CFG_HW_ECC_DISABLE); 757 writel(reg_val, &info->reg->config); 758 759 if (is_writing && with_ecc) 760 tag_size -= TAG_ECC_BYTES; 761 762 if (is_writing) 763 bbflags = GEN_BB_READ; 764 else 765 bbflags = GEN_BB_WRITE; 766 767 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size, 768 bbflags); 769 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr); 770 771 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config); 772 773 writel(tag_size - 1, &info->reg->dma_cfg_b); 774 775 nand_clear_interrupt_status(info->reg); 776 777 reg_val = CMD_CLE | CMD_ALE 778 | CMD_SEC_CMD 779 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT) 780 | CMD_B_VALID 781 | CMD_CE0; 782 if (!is_writing) 783 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); 784 else 785 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); 786 writel(reg_val, &info->reg->command); 787 788 /* Setup DMA engine */ 789 reg_val = DMA_MST_CTRL_GO_ENABLE 790 | DMA_MST_CTRL_BURST_8WORDS 791 | DMA_MST_CTRL_EN_B_ENABLE; 792 if (!is_writing) 793 reg_val |= DMA_MST_CTRL_DIR_READ; 794 else 795 reg_val |= DMA_MST_CTRL_DIR_WRITE; 796 797 writel(reg_val, &info->reg->dma_mst_ctrl); 798 799 start_command(info->reg); 800 801 if (!nand_waitfor_cmd_completion(info->reg)) { 802 if (!is_writing) 803 printf("Read OOB of Page 0x%X timeout\n", page); 804 else 805 printf("Write OOB of Page 0x%X timeout\n", page); 806 return -EIO; 807 } 808 809 bounce_buffer_stop(&bbstate_oob); 810 811 if (with_ecc && !is_writing) { 812 reg_val = (u32)check_ecc_error(info->reg, 0, 0, 813 (u8 *)(chip->oob_poi + free->offset), 814 chip->ecc.layout->oobavail); 815 if (reg_val & ECC_TAG_ERROR) 816 printf("Read OOB of Page 0x%X tag ECC error\n", page); 817 } 818 return 0; 819} 820 821/** 822 * OOB data read function 823 * 824 * @param mtd mtd info structure 825 * @param chip nand chip info structure 826 * @param page page number to read 827 */ 828static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 829 int page) 830{ 831 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 832 nand_rw_oob(mtd, chip, page, 0, 0); 833 return 0; 834} 835 836/** 837 * OOB data write function 838 * 839 * @param mtd mtd info structure 840 * @param chip nand chip info structure 841 * @param page page number to write 842 * Return: 0 when successfully completed 843 * -EINVAL when chip->oob_poi is not double-word aligned 844 * -EIO when command timeout 845 */ 846static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 847 int page) 848{ 849 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 850 851 return nand_rw_oob(mtd, chip, page, 0, 1); 852} 853 854/** 855 * Set up NAND memory timings according to the provided parameters 856 * 857 * @param timing Timing parameters 858 * @param reg NAND controller register address 859 */ 860static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT], 861 struct nand_ctlr *reg) 862{ 863 u32 reg_val, clk_rate, clk_period, time_val; 864 865 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH, 866 CLOCK_ID_PERIPH) / 1000000; 867 clk_period = 1000 / clk_rate; 868 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << 869 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK; 870 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << 871 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK; 872 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; 873 if (time_val > 2) 874 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) & 875 TIMING_TCR_TAR_TRR_CNT_MASK; 876 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << 877 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK; 878 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period; 879 if (time_val > 1) 880 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) & 881 TIMING_TCS_CNT_MASK; 882 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << 883 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK; 884 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << 885 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK; 886 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << 887 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK; 888 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << 889 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK; 890 writel(reg_val, ®->timing); 891 892 reg_val = 0; 893 time_val = timing[FDT_NAND_TADL] / clk_period; 894 if (time_val > 2) 895 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK; 896 writel(reg_val, ®->timing2); 897} 898 899/** 900 * Decode NAND parameters from the device tree 901 * 902 * @param dev Driver model device 903 * @param config Device tree NAND configuration 904 * Return: 0 if ok, -ve on error (FDT_ERR_...) 905 */ 906static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config) 907{ 908 int err; 909 910 config->reg = dev_read_addr_ptr(dev); 911 config->enabled = dev_read_enabled(dev); 912 config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8); 913 err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio, 914 GPIOD_IS_OUT); 915 if (err) 916 return err; 917 err = dev_read_u32_array(dev, "nvidia,timing", config->timing, 918 FDT_NAND_TIMING_COUNT); 919 if (err < 0) 920 return err; 921 922 return 0; 923} 924 925static int tegra_probe(struct udevice *dev) 926{ 927 struct tegra_nand_info *tegra = dev_get_priv(dev); 928 struct nand_chip *nand = &tegra->nand_chip; 929 struct nand_drv *info = &tegra->nand_ctrl; 930 struct fdt_nand *config = &info->config; 931 struct mtd_info *our_mtd; 932 int ret; 933 934 if (fdt_decode_nand(dev, config)) { 935 printf("Could not decode nand-flash in device tree\n"); 936 return -1; 937 } 938 if (!config->enabled) 939 return -1; 940 info->reg = config->reg; 941 nand->ecc.mode = NAND_ECC_HW; 942 nand->ecc.layout = &eccoob; 943 944 nand->options = LP_OPTIONS; 945 nand->cmdfunc = nand_command; 946 nand->read_byte = read_byte; 947 nand->read_buf = read_buf; 948 nand->ecc.read_page = nand_read_page_hwecc; 949 nand->ecc.write_page = nand_write_page_hwecc; 950 nand->ecc.read_page_raw = nand_read_page_raw; 951 nand->ecc.write_page_raw = nand_write_page_raw; 952 nand->ecc.read_oob = nand_read_oob; 953 nand->ecc.write_oob = nand_write_oob; 954 nand->ecc.strength = 1; 955 nand->select_chip = nand_select_chip; 956 nand->dev_ready = nand_dev_ready; 957 nand_set_controller_data(nand, &tegra->nand_ctrl); 958 959 /* Disable subpage writes as we do not provide ecc->hwctl */ 960 nand->options |= NAND_NO_SUBPAGE_WRITE; 961 962 /* Adjust controller clock rate */ 963 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000); 964 965 /* Adjust timing for NAND device */ 966 setup_timing(config->timing, info->reg); 967 968 dm_gpio_set_value(&config->wp_gpio, 1); 969 970 our_mtd = nand_to_mtd(nand); 971 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); 972 if (ret) 973 return ret; 974 975 nand->ecc.size = our_mtd->writesize; 976 nand->ecc.bytes = our_mtd->oobsize; 977 978 ret = nand_scan_tail(our_mtd); 979 if (ret) 980 return ret; 981 982 ret = nand_register(0, our_mtd); 983 if (ret) { 984 dev_err(dev, "Failed to register MTD: %d\n", ret); 985 return ret; 986 } 987 988 return 0; 989} 990 991U_BOOT_DRIVER(tegra_nand) = { 992 .name = "tegra-nand", 993 .id = UCLASS_MTD, 994 .of_match = tegra_nand_dt_ids, 995 .probe = tegra_probe, 996 .priv_auto = sizeof(struct tegra_nand_info), 997}; 998 999void board_nand_init(void) 1000{ 1001 struct udevice *dev; 1002 int ret; 1003 1004 ret = uclass_get_device_by_driver(UCLASS_MTD, 1005 DM_DRIVER_GET(tegra_nand), &dev); 1006 if (ret && ret != -ENODEV) 1007 pr_err("Failed to initialize %s. (error %d)\n", dev->name, 1008 ret); 1009} 1010