1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2004-2007 Freescale Semiconductor, Inc. 4 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de 5 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com> 6 */ 7 8#include <common.h> 9#include <log.h> 10#include <nand.h> 11#include <linux/delay.h> 12#include <linux/err.h> 13#include <linux/mtd/rawnand.h> 14#include <asm/io.h> 15#if defined(CONFIG_MX51) || defined(CONFIG_MX53) 16#include <asm/arch/imx-regs.h> 17#endif 18#include <linux/printk.h> 19#include "mxc_nand.h" 20 21#define DRIVER_NAME "mxc_nand" 22 23struct mxc_nand_host { 24 struct nand_chip *nand; 25 26 struct mxc_nand_regs __iomem *regs; 27#ifdef MXC_NFC_V3_2 28 struct mxc_nand_ip_regs __iomem *ip_regs; 29#endif 30 int spare_only; 31 int status_request; 32 int pagesize_2k; 33 int clk_act; 34 uint16_t col_addr; 35 unsigned int page_addr; 36}; 37 38static struct mxc_nand_host mxc_host; 39static struct mxc_nand_host *host = &mxc_host; 40 41/* Define delays in microsec for NAND device operations */ 42#define TROP_US_DELAY 2000 43/* Macros to get byte and bit positions of ECC */ 44#define COLPOS(x) ((x) >> 3) 45#define BITPOS(x) ((x) & 0xf) 46 47/* Define single bit Error positions in Main & Spare area */ 48#define MAIN_SINGLEBIT_ERROR 0x4 49#define SPARE_SINGLEBIT_ERROR 0x1 50 51/* OOB placement block for use with hardware ecc generation */ 52#if defined(MXC_NFC_V1) 53#ifndef CFG_SYS_NAND_LARGEPAGE 54static struct nand_ecclayout nand_hw_eccoob = { 55 .eccbytes = 5, 56 .eccpos = {6, 7, 8, 9, 10}, 57 .oobfree = { {0, 5}, {11, 5}, } 58}; 59#else 60static struct nand_ecclayout nand_hw_eccoob2k = { 61 .eccbytes = 20, 62 .eccpos = { 63 6, 7, 8, 9, 10, 64 22, 23, 24, 25, 26, 65 38, 39, 40, 41, 42, 66 54, 55, 56, 57, 58, 67 }, 68 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} }, 69}; 70#endif 71#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) 72#ifndef CFG_SYS_NAND_LARGEPAGE 73static struct nand_ecclayout nand_hw_eccoob = { 74 .eccbytes = 9, 75 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, 76 .oobfree = { {2, 5} } 77}; 78#else 79static struct nand_ecclayout nand_hw_eccoob2k = { 80 .eccbytes = 36, 81 .eccpos = { 82 7, 8, 9, 10, 11, 12, 13, 14, 15, 83 23, 24, 25, 26, 27, 28, 29, 30, 31, 84 39, 40, 41, 42, 43, 44, 45, 46, 47, 85 55, 56, 57, 58, 59, 60, 61, 62, 63, 86 }, 87 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} }, 88}; 89#endif 90#endif 91 92static int is_16bit_nand(void) 93{ 94#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) 95 return 1; 96#else 97 return 0; 98#endif 99} 100 101static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size) 102{ 103 uint32_t *d = dest; 104 105 size >>= 2; 106 while (size--) 107 __raw_writel(__raw_readl(source++), d++); 108 return dest; 109} 110 111/* 112 * This function polls the NANDFC to wait for the basic operation to 113 * complete by checking the INT bit. 114 */ 115static void wait_op_done(struct mxc_nand_host *host, int max_retries, 116 uint16_t param) 117{ 118 uint32_t tmp; 119 120 while (max_retries-- > 0) { 121#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 122 tmp = readnfc(&host->regs->config2); 123 if (tmp & NFC_V1_V2_CONFIG2_INT) { 124 tmp &= ~NFC_V1_V2_CONFIG2_INT; 125 writenfc(tmp, &host->regs->config2); 126#elif defined(MXC_NFC_V3_2) 127 tmp = readnfc(&host->ip_regs->ipc); 128 if (tmp & NFC_V3_IPC_INT) { 129 tmp &= ~NFC_V3_IPC_INT; 130 writenfc(tmp, &host->ip_regs->ipc); 131#endif 132 break; 133 } 134 udelay(1); 135 } 136 if (max_retries < 0) { 137 pr_debug("%s(%d): INT not set\n", 138 __func__, param); 139 } 140} 141 142/* 143 * This function issues the specified command to the NAND device and 144 * waits for completion. 145 */ 146static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) 147{ 148 pr_debug("send_cmd(host, 0x%x)\n", cmd); 149 150 writenfc(cmd, &host->regs->flash_cmd); 151 writenfc(NFC_CMD, &host->regs->operation); 152 153 /* Wait for operation to complete */ 154 wait_op_done(host, TROP_US_DELAY, cmd); 155} 156 157/* 158 * This function sends an address (or partial address) to the 159 * NAND device. The address is used to select the source/destination for 160 * a NAND command. 161 */ 162static void send_addr(struct mxc_nand_host *host, uint16_t addr) 163{ 164 pr_debug("send_addr(host, 0x%x)\n", addr); 165 166 writenfc(addr, &host->regs->flash_addr); 167 writenfc(NFC_ADDR, &host->regs->operation); 168 169 /* Wait for operation to complete */ 170 wait_op_done(host, TROP_US_DELAY, addr); 171} 172 173/* 174 * This function requests the NANDFC to initiate the transfer 175 * of data currently in the NANDFC RAM buffer to the NAND device. 176 */ 177static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, 178 int spare_only) 179{ 180 if (spare_only) 181 pr_debug("send_prog_page (%d)\n", spare_only); 182 183 if (is_mxc_nfc_21() || is_mxc_nfc_32()) { 184 int i; 185 /* 186 * The controller copies the 64 bytes of spare data from 187 * the first 16 bytes of each of the 4 64 byte spare buffers. 188 * Copy the contiguous data starting in spare_area[0] to 189 * the four spare area buffers. 190 */ 191 for (i = 1; i < 4; i++) { 192 void __iomem *src = &host->regs->spare_area[0][i * 16]; 193 void __iomem *dst = &host->regs->spare_area[i][0]; 194 195 mxc_nand_memcpy32(dst, src, 16); 196 } 197 } 198 199#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 200 writenfc(buf_id, &host->regs->buf_addr); 201#elif defined(MXC_NFC_V3_2) 202 uint32_t tmp = readnfc(&host->regs->config1); 203 tmp &= ~NFC_V3_CONFIG1_RBA_MASK; 204 tmp |= NFC_V3_CONFIG1_RBA(buf_id); 205 writenfc(tmp, &host->regs->config1); 206#endif 207 208 /* Configure spare or page+spare access */ 209 if (!host->pagesize_2k) { 210 uint32_t config1 = readnfc(&host->regs->config1); 211 if (spare_only) 212 config1 |= NFC_CONFIG1_SP_EN; 213 else 214 config1 &= ~NFC_CONFIG1_SP_EN; 215 writenfc(config1, &host->regs->config1); 216 } 217 218 writenfc(NFC_INPUT, &host->regs->operation); 219 220 /* Wait for operation to complete */ 221 wait_op_done(host, TROP_US_DELAY, spare_only); 222} 223 224/* 225 * Requests NANDFC to initiate the transfer of data from the 226 * NAND device into in the NANDFC ram buffer. 227 */ 228static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, 229 int spare_only) 230{ 231 pr_debug("send_read_page (%d)\n", spare_only); 232 233#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 234 writenfc(buf_id, &host->regs->buf_addr); 235#elif defined(MXC_NFC_V3_2) 236 uint32_t tmp = readnfc(&host->regs->config1); 237 tmp &= ~NFC_V3_CONFIG1_RBA_MASK; 238 tmp |= NFC_V3_CONFIG1_RBA(buf_id); 239 writenfc(tmp, &host->regs->config1); 240#endif 241 242 /* Configure spare or page+spare access */ 243 if (!host->pagesize_2k) { 244 uint32_t config1 = readnfc(&host->regs->config1); 245 if (spare_only) 246 config1 |= NFC_CONFIG1_SP_EN; 247 else 248 config1 &= ~NFC_CONFIG1_SP_EN; 249 writenfc(config1, &host->regs->config1); 250 } 251 252 writenfc(NFC_OUTPUT, &host->regs->operation); 253 254 /* Wait for operation to complete */ 255 wait_op_done(host, TROP_US_DELAY, spare_only); 256 257 if (is_mxc_nfc_21() || is_mxc_nfc_32()) { 258 int i; 259 260 /* 261 * The controller copies the 64 bytes of spare data to 262 * the first 16 bytes of each of the 4 spare buffers. 263 * Make the data contiguous starting in spare_area[0]. 264 */ 265 for (i = 1; i < 4; i++) { 266 void __iomem *src = &host->regs->spare_area[i][0]; 267 void __iomem *dst = &host->regs->spare_area[0][i * 16]; 268 269 mxc_nand_memcpy32(dst, src, 16); 270 } 271 } 272} 273 274/* Request the NANDFC to perform a read of the NAND device ID. */ 275static void send_read_id(struct mxc_nand_host *host) 276{ 277 uint32_t tmp; 278 279#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 280 /* NANDFC buffer 0 is used for device ID output */ 281 writenfc(0x0, &host->regs->buf_addr); 282#elif defined(MXC_NFC_V3_2) 283 tmp = readnfc(&host->regs->config1); 284 tmp &= ~NFC_V3_CONFIG1_RBA_MASK; 285 writenfc(tmp, &host->regs->config1); 286#endif 287 288 /* Read ID into main buffer */ 289 tmp = readnfc(&host->regs->config1); 290 tmp &= ~NFC_CONFIG1_SP_EN; 291 writenfc(tmp, &host->regs->config1); 292 293 writenfc(NFC_ID, &host->regs->operation); 294 295 /* Wait for operation to complete */ 296 wait_op_done(host, TROP_US_DELAY, 0); 297} 298 299/* 300 * This function requests the NANDFC to perform a read of the 301 * NAND device status and returns the current status. 302 */ 303static uint16_t get_dev_status(struct mxc_nand_host *host) 304{ 305#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 306 void __iomem *main_buf = host->regs->main_area[1]; 307 uint32_t store; 308#endif 309 uint32_t ret, tmp; 310 /* Issue status request to NAND device */ 311 312#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 313 /* store the main area1 first word, later do recovery */ 314 store = readl(main_buf); 315 /* NANDFC buffer 1 is used for device status */ 316 writenfc(1, &host->regs->buf_addr); 317#endif 318 319 /* Read status into main buffer */ 320 tmp = readnfc(&host->regs->config1); 321 tmp &= ~NFC_CONFIG1_SP_EN; 322 writenfc(tmp, &host->regs->config1); 323 324 writenfc(NFC_STATUS, &host->regs->operation); 325 326 /* Wait for operation to complete */ 327 wait_op_done(host, TROP_US_DELAY, 0); 328 329#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 330 /* 331 * Status is placed in first word of main buffer 332 * get status, then recovery area 1 data 333 */ 334 ret = readw(main_buf); 335 writel(store, main_buf); 336#elif defined(MXC_NFC_V3_2) 337 ret = readnfc(&host->regs->config1) >> 16; 338#endif 339 340 return ret; 341} 342 343/* This function is used by upper layer to checks if device is ready */ 344static int mxc_nand_dev_ready(struct mtd_info *mtd) 345{ 346 /* 347 * NFC handles R/B internally. Therefore, this function 348 * always returns status as ready. 349 */ 350 return 1; 351} 352 353static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) 354{ 355 struct nand_chip *nand_chip = mtd_to_nand(mtd); 356 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 357#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 358 uint16_t tmp = readnfc(&host->regs->config1); 359 360 if (on) 361 tmp |= NFC_V1_V2_CONFIG1_ECC_EN; 362 else 363 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN; 364 writenfc(tmp, &host->regs->config1); 365#elif defined(MXC_NFC_V3_2) 366 uint32_t tmp = readnfc(&host->ip_regs->config2); 367 368 if (on) 369 tmp |= NFC_V3_CONFIG2_ECC_EN; 370 else 371 tmp &= ~NFC_V3_CONFIG2_ECC_EN; 372 writenfc(tmp, &host->ip_regs->config2); 373#endif 374} 375 376#ifdef CONFIG_MXC_NAND_HWECC 377static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) 378{ 379 /* 380 * If HW ECC is enabled, we turn it on during init. There is 381 * no need to enable again here. 382 */ 383} 384 385#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) 386static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, 387 struct nand_chip *chip, 388 int page) 389{ 390 struct mxc_nand_host *host = nand_get_controller_data(chip); 391 uint8_t *buf = chip->oob_poi; 392 int length = mtd->oobsize; 393 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 394 uint8_t *bufpoi = buf; 395 int i, toread; 396 397 pr_debug("%s: Reading OOB area of page %u to oob %p\n", 398 __func__, page, buf); 399 400 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); 401 for (i = 0; i < chip->ecc.steps; i++) { 402 toread = min_t(int, length, chip->ecc.prepad); 403 if (toread) { 404 chip->read_buf(mtd, bufpoi, toread); 405 bufpoi += toread; 406 length -= toread; 407 } 408 bufpoi += chip->ecc.bytes; 409 host->col_addr += chip->ecc.bytes; 410 length -= chip->ecc.bytes; 411 412 toread = min_t(int, length, chip->ecc.postpad); 413 if (toread) { 414 chip->read_buf(mtd, bufpoi, toread); 415 bufpoi += toread; 416 length -= toread; 417 } 418 } 419 if (length > 0) 420 chip->read_buf(mtd, bufpoi, length); 421 422 _mxc_nand_enable_hwecc(mtd, 0); 423 chip->cmdfunc(mtd, NAND_CMD_READOOB, 424 mtd->writesize + chip->ecc.prepad, page); 425 bufpoi = buf + chip->ecc.prepad; 426 length = mtd->oobsize - chip->ecc.prepad; 427 for (i = 0; i < chip->ecc.steps; i++) { 428 toread = min_t(int, length, chip->ecc.bytes); 429 chip->read_buf(mtd, bufpoi, toread); 430 bufpoi += eccpitch; 431 length -= eccpitch; 432 host->col_addr += chip->ecc.postpad + chip->ecc.prepad; 433 } 434 _mxc_nand_enable_hwecc(mtd, 1); 435 return 1; 436} 437 438static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, 439 struct nand_chip *chip, 440 uint8_t *buf, 441 int oob_required, 442 int page) 443{ 444 struct mxc_nand_host *host = nand_get_controller_data(chip); 445 int eccsize = chip->ecc.size; 446 int eccbytes = chip->ecc.bytes; 447 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 448 uint8_t *oob = chip->oob_poi; 449 int steps, size; 450 int n; 451 452 _mxc_nand_enable_hwecc(mtd, 0); 453 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 454 455 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { 456 host->col_addr = n * eccsize; 457 chip->read_buf(mtd, buf, eccsize); 458 buf += eccsize; 459 460 host->col_addr = mtd->writesize + n * eccpitch; 461 if (chip->ecc.prepad) { 462 chip->read_buf(mtd, oob, chip->ecc.prepad); 463 oob += chip->ecc.prepad; 464 } 465 466 chip->read_buf(mtd, oob, eccbytes); 467 oob += eccbytes; 468 469 if (chip->ecc.postpad) { 470 chip->read_buf(mtd, oob, chip->ecc.postpad); 471 oob += chip->ecc.postpad; 472 } 473 } 474 475 size = mtd->oobsize - (oob - chip->oob_poi); 476 if (size) 477 chip->read_buf(mtd, oob, size); 478 _mxc_nand_enable_hwecc(mtd, 1); 479 480 return 0; 481} 482 483static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, 484 struct nand_chip *chip, 485 uint8_t *buf, 486 int oob_required, 487 int page) 488{ 489 struct mxc_nand_host *host = nand_get_controller_data(chip); 490 int n, eccsize = chip->ecc.size; 491 int eccbytes = chip->ecc.bytes; 492 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 493 int eccsteps = chip->ecc.steps; 494 uint8_t *p = buf; 495 uint8_t *oob = chip->oob_poi; 496 497 pr_debug("Reading page %u to buf %p oob %p\n", 498 page, buf, oob); 499 500 /* first read the data area and the available portion of OOB */ 501 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { 502 int stat; 503 504 host->col_addr = n * eccsize; 505 506 chip->read_buf(mtd, p, eccsize); 507 508 host->col_addr = mtd->writesize + n * eccpitch; 509 510 if (chip->ecc.prepad) { 511 chip->read_buf(mtd, oob, chip->ecc.prepad); 512 oob += chip->ecc.prepad; 513 } 514 515 stat = chip->ecc.correct(mtd, p, oob, NULL); 516 517 if (stat < 0) 518 mtd->ecc_stats.failed++; 519 else 520 mtd->ecc_stats.corrected += stat; 521 oob += eccbytes; 522 523 if (chip->ecc.postpad) { 524 chip->read_buf(mtd, oob, chip->ecc.postpad); 525 oob += chip->ecc.postpad; 526 } 527 } 528 529 /* Calculate remaining oob bytes */ 530 n = mtd->oobsize - (oob - chip->oob_poi); 531 if (n) 532 chip->read_buf(mtd, oob, n); 533 534 /* Then switch ECC off and read the OOB area to get the ECC code */ 535 _mxc_nand_enable_hwecc(mtd, 0); 536 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); 537 eccsteps = chip->ecc.steps; 538 oob = chip->oob_poi + chip->ecc.prepad; 539 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { 540 host->col_addr = mtd->writesize + 541 n * eccpitch + 542 chip->ecc.prepad; 543 chip->read_buf(mtd, oob, eccbytes); 544 oob += eccbytes + chip->ecc.postpad; 545 } 546 _mxc_nand_enable_hwecc(mtd, 1); 547 return 0; 548} 549 550static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd, 551 struct nand_chip *chip, int page) 552{ 553 struct mxc_nand_host *host = nand_get_controller_data(chip); 554 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 555 int length = mtd->oobsize; 556 int i, len, status, steps = chip->ecc.steps; 557 const uint8_t *bufpoi = chip->oob_poi; 558 559 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 560 for (i = 0; i < steps; i++) { 561 len = min_t(int, length, eccpitch); 562 563 chip->write_buf(mtd, bufpoi, len); 564 bufpoi += len; 565 length -= len; 566 host->col_addr += chip->ecc.prepad + chip->ecc.postpad; 567 } 568 if (length > 0) 569 chip->write_buf(mtd, bufpoi, length); 570 571 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 572 status = chip->waitfunc(mtd, chip); 573 return status & NAND_STATUS_FAIL ? -EIO : 0; 574} 575 576static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd, 577 struct nand_chip *chip, 578 const uint8_t *buf, 579 int oob_required, int page) 580{ 581 struct mxc_nand_host *host = nand_get_controller_data(chip); 582 int eccsize = chip->ecc.size; 583 int eccbytes = chip->ecc.bytes; 584 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 585 uint8_t *oob = chip->oob_poi; 586 int steps, size; 587 int n; 588 589 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { 590 host->col_addr = n * eccsize; 591 chip->write_buf(mtd, buf, eccsize); 592 buf += eccsize; 593 594 host->col_addr = mtd->writesize + n * eccpitch; 595 596 if (chip->ecc.prepad) { 597 chip->write_buf(mtd, oob, chip->ecc.prepad); 598 oob += chip->ecc.prepad; 599 } 600 601 host->col_addr += eccbytes; 602 oob += eccbytes; 603 604 if (chip->ecc.postpad) { 605 chip->write_buf(mtd, oob, chip->ecc.postpad); 606 oob += chip->ecc.postpad; 607 } 608 } 609 610 size = mtd->oobsize - (oob - chip->oob_poi); 611 if (size) 612 chip->write_buf(mtd, oob, size); 613 return 0; 614} 615 616static int mxc_nand_write_page_syndrome(struct mtd_info *mtd, 617 struct nand_chip *chip, 618 const uint8_t *buf, 619 int oob_required, int page) 620{ 621 struct mxc_nand_host *host = nand_get_controller_data(chip); 622 int i, n, eccsize = chip->ecc.size; 623 int eccbytes = chip->ecc.bytes; 624 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 625 int eccsteps = chip->ecc.steps; 626 const uint8_t *p = buf; 627 uint8_t *oob = chip->oob_poi; 628 629 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 630 631 for (i = n = 0; 632 eccsteps; 633 n++, eccsteps--, i += eccbytes, p += eccsize) { 634 host->col_addr = n * eccsize; 635 636 chip->write_buf(mtd, p, eccsize); 637 638 host->col_addr = mtd->writesize + n * eccpitch; 639 640 if (chip->ecc.prepad) { 641 chip->write_buf(mtd, oob, chip->ecc.prepad); 642 oob += chip->ecc.prepad; 643 } 644 645 chip->write_buf(mtd, oob, eccbytes); 646 oob += eccbytes; 647 648 if (chip->ecc.postpad) { 649 chip->write_buf(mtd, oob, chip->ecc.postpad); 650 oob += chip->ecc.postpad; 651 } 652 } 653 654 /* Calculate remaining oob bytes */ 655 i = mtd->oobsize - (oob - chip->oob_poi); 656 if (i) 657 chip->write_buf(mtd, oob, i); 658 return 0; 659} 660 661static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, 662 u_char *read_ecc, u_char *calc_ecc) 663{ 664 struct nand_chip *nand_chip = mtd_to_nand(mtd); 665 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 666 uint32_t ecc_status = readl(&host->regs->ecc_status_result); 667 int subpages = mtd->writesize / nand_chip->subpagesize; 668 int pg2blk_shift = nand_chip->phys_erase_shift - 669 nand_chip->page_shift; 670 671 do { 672 if ((ecc_status & 0xf) > 4) { 673 static int last_bad = -1; 674 675 if (last_bad != host->page_addr >> pg2blk_shift) { 676 last_bad = host->page_addr >> pg2blk_shift; 677 printk(KERN_DEBUG 678 "MXC_NAND: HWECC uncorrectable ECC error" 679 " in block %u page %u subpage %d\n", 680 last_bad, host->page_addr, 681 mtd->writesize / nand_chip->subpagesize 682 - subpages); 683 } 684 return -EBADMSG; 685 } 686 ecc_status >>= 4; 687 subpages--; 688 } while (subpages > 0); 689 690 return 0; 691} 692#else 693#define mxc_nand_read_page_syndrome NULL 694#define mxc_nand_read_page_raw_syndrome NULL 695#define mxc_nand_read_oob_syndrome NULL 696#define mxc_nand_write_page_syndrome NULL 697#define mxc_nand_write_page_raw_syndrome NULL 698#define mxc_nand_write_oob_syndrome NULL 699 700static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, 701 u_char *read_ecc, u_char *calc_ecc) 702{ 703 struct nand_chip *nand_chip = mtd_to_nand(mtd); 704 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 705 706 /* 707 * 1-Bit errors are automatically corrected in HW. No need for 708 * additional correction. 2-Bit errors cannot be corrected by 709 * HW ECC, so we need to return failure 710 */ 711 uint16_t ecc_status = readnfc(&host->regs->ecc_status_result); 712 713 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { 714 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); 715 return -EBADMSG; 716 } 717 718 return 0; 719} 720#endif 721 722static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 723 u_char *ecc_code) 724{ 725 return 0; 726} 727#endif 728 729static u_char mxc_nand_read_byte(struct mtd_info *mtd) 730{ 731 struct nand_chip *nand_chip = mtd_to_nand(mtd); 732 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 733 uint8_t ret = 0; 734 uint16_t col; 735 uint16_t __iomem *main_buf = 736 (uint16_t __iomem *)host->regs->main_area[0]; 737 uint16_t __iomem *spare_buf = 738 (uint16_t __iomem *)host->regs->spare_area[0]; 739 union { 740 uint16_t word; 741 uint8_t bytes[2]; 742 } nfc_word; 743 744 /* Check for status request */ 745 if (host->status_request) 746 return get_dev_status(host) & 0xFF; 747 748 /* Get column for 16-bit access */ 749 col = host->col_addr >> 1; 750 751 /* If we are accessing the spare region */ 752 if (host->spare_only) 753 nfc_word.word = readw(&spare_buf[col]); 754 else 755 nfc_word.word = readw(&main_buf[col]); 756 757 /* Pick upper/lower byte of word from RAM buffer */ 758 ret = nfc_word.bytes[host->col_addr & 0x1]; 759 760 /* Update saved column address */ 761 if (nand_chip->options & NAND_BUSWIDTH_16) 762 host->col_addr += 2; 763 else 764 host->col_addr++; 765 766 return ret; 767} 768 769static uint16_t mxc_nand_read_word(struct mtd_info *mtd) 770{ 771 struct nand_chip *nand_chip = mtd_to_nand(mtd); 772 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 773 uint16_t col, ret; 774 uint16_t __iomem *p; 775 776 pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr); 777 778 col = host->col_addr; 779 /* Adjust saved column address */ 780 if (col < mtd->writesize && host->spare_only) 781 col += mtd->writesize; 782 783 if (col < mtd->writesize) { 784 p = (uint16_t __iomem *)(host->regs->main_area[0] + 785 (col >> 1)); 786 } else { 787 p = (uint16_t __iomem *)(host->regs->spare_area[0] + 788 ((col - mtd->writesize) >> 1)); 789 } 790 791 if (col & 1) { 792 union { 793 uint16_t word; 794 uint8_t bytes[2]; 795 } nfc_word[3]; 796 797 nfc_word[0].word = readw(p); 798 nfc_word[1].word = readw(p + 1); 799 800 nfc_word[2].bytes[0] = nfc_word[0].bytes[1]; 801 nfc_word[2].bytes[1] = nfc_word[1].bytes[0]; 802 803 ret = nfc_word[2].word; 804 } else { 805 ret = readw(p); 806 } 807 808 /* Update saved column address */ 809 host->col_addr = col + 2; 810 811 return ret; 812} 813 814/* 815 * Write data of length len to buffer buf. The data to be 816 * written on NAND Flash is first copied to RAMbuffer. After the Data Input 817 * Operation by the NFC, the data is written to NAND Flash 818 */ 819static void mxc_nand_write_buf(struct mtd_info *mtd, 820 const u_char *buf, int len) 821{ 822 struct nand_chip *nand_chip = mtd_to_nand(mtd); 823 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 824 int n, col, i = 0; 825 826 pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr, 827 len); 828 829 col = host->col_addr; 830 831 /* Adjust saved column address */ 832 if (col < mtd->writesize && host->spare_only) 833 col += mtd->writesize; 834 835 n = mtd->writesize + mtd->oobsize - col; 836 n = min(len, n); 837 838 pr_debug("%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n); 839 840 while (n > 0) { 841 void __iomem *p; 842 843 if (col < mtd->writesize) { 844 p = host->regs->main_area[0] + (col & ~3); 845 } else { 846 p = host->regs->spare_area[0] - 847 mtd->writesize + (col & ~3); 848 } 849 850 pr_debug("%s:%d: p = %p\n", __func__, 851 __LINE__, p); 852 853 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) { 854 union { 855 uint32_t word; 856 uint8_t bytes[4]; 857 } nfc_word; 858 859 nfc_word.word = readl(p); 860 nfc_word.bytes[col & 3] = buf[i++]; 861 n--; 862 col++; 863 864 writel(nfc_word.word, p); 865 } else { 866 int m = mtd->writesize - col; 867 868 if (col >= mtd->writesize) 869 m += mtd->oobsize; 870 871 m = min(n, m) & ~3; 872 873 pr_debug("%s:%d: n = %d, m = %d, i = %d, col = %d\n", 874 __func__, __LINE__, n, m, i, col); 875 876 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m); 877 col += m; 878 i += m; 879 n -= m; 880 } 881 } 882 /* Update saved column address */ 883 host->col_addr = col; 884} 885 886/* 887 * Read the data buffer from the NAND Flash. To read the data from NAND 888 * Flash first the data output cycle is initiated by the NFC, which copies 889 * the data to RAMbuffer. This data of length len is then copied to buffer buf. 890 */ 891static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 892{ 893 struct nand_chip *nand_chip = mtd_to_nand(mtd); 894 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 895 int n, col, i = 0; 896 897 pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, 898 len); 899 900 col = host->col_addr; 901 902 /* Adjust saved column address */ 903 if (col < mtd->writesize && host->spare_only) 904 col += mtd->writesize; 905 906 n = mtd->writesize + mtd->oobsize - col; 907 n = min(len, n); 908 909 while (n > 0) { 910 void __iomem *p; 911 912 if (col < mtd->writesize) { 913 p = host->regs->main_area[0] + (col & ~3); 914 } else { 915 p = host->regs->spare_area[0] - 916 mtd->writesize + (col & ~3); 917 } 918 919 if (((col | (int)&buf[i]) & 3) || n < 4) { 920 union { 921 uint32_t word; 922 uint8_t bytes[4]; 923 } nfc_word; 924 925 nfc_word.word = readl(p); 926 buf[i++] = nfc_word.bytes[col & 3]; 927 n--; 928 col++; 929 } else { 930 int m = mtd->writesize - col; 931 932 if (col >= mtd->writesize) 933 m += mtd->oobsize; 934 935 m = min(n, m) & ~3; 936 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m); 937 938 col += m; 939 i += m; 940 n -= m; 941 } 942 } 943 /* Update saved column address */ 944 host->col_addr = col; 945} 946 947/* 948 * This function is used by upper layer for select and 949 * deselect of the NAND chip 950 */ 951static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) 952{ 953 struct nand_chip *nand_chip = mtd_to_nand(mtd); 954 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 955 956 switch (chip) { 957 case -1: 958 /* TODO: Disable the NFC clock */ 959 if (host->clk_act) 960 host->clk_act = 0; 961 break; 962 case 0: 963 /* TODO: Enable the NFC clock */ 964 if (!host->clk_act) 965 host->clk_act = 1; 966 break; 967 968 default: 969 break; 970 } 971} 972 973/* 974 * Used by the upper layer to write command to NAND Flash for 975 * different operations to be carried out on NAND Flash 976 */ 977void mxc_nand_command(struct mtd_info *mtd, unsigned command, 978 int column, int page_addr) 979{ 980 struct nand_chip *nand_chip = mtd_to_nand(mtd); 981 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 982 983 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", 984 command, column, page_addr); 985 986 /* Reset command state information */ 987 host->status_request = false; 988 989 /* Command pre-processing step */ 990 switch (command) { 991 992 case NAND_CMD_STATUS: 993 host->col_addr = 0; 994 host->status_request = true; 995 break; 996 997 case NAND_CMD_READ0: 998 host->page_addr = page_addr; 999 host->col_addr = column; 1000 host->spare_only = false; 1001 break; 1002 1003 case NAND_CMD_READOOB: 1004 host->col_addr = column; 1005 host->spare_only = true; 1006 if (host->pagesize_2k) 1007 command = NAND_CMD_READ0; /* only READ0 is valid */ 1008 break; 1009 1010 case NAND_CMD_SEQIN: 1011 if (column >= mtd->writesize) { 1012 /* 1013 * before sending SEQIN command for partial write, 1014 * we need read one page out. FSL NFC does not support 1015 * partial write. It always sends out 512+ecc+512+ecc 1016 * for large page nand flash. But for small page nand 1017 * flash, it does support SPARE ONLY operation. 1018 */ 1019 if (host->pagesize_2k) { 1020 /* call ourself to read a page */ 1021 mxc_nand_command(mtd, NAND_CMD_READ0, 0, 1022 page_addr); 1023 } 1024 1025 host->col_addr = column - mtd->writesize; 1026 host->spare_only = true; 1027 1028 /* Set program pointer to spare region */ 1029 if (!host->pagesize_2k) 1030 send_cmd(host, NAND_CMD_READOOB); 1031 } else { 1032 host->spare_only = false; 1033 host->col_addr = column; 1034 1035 /* Set program pointer to page start */ 1036 if (!host->pagesize_2k) 1037 send_cmd(host, NAND_CMD_READ0); 1038 } 1039 break; 1040 1041 case NAND_CMD_PAGEPROG: 1042 send_prog_page(host, 0, host->spare_only); 1043 1044 if (host->pagesize_2k && is_mxc_nfc_1()) { 1045 /* data in 4 areas */ 1046 send_prog_page(host, 1, host->spare_only); 1047 send_prog_page(host, 2, host->spare_only); 1048 send_prog_page(host, 3, host->spare_only); 1049 } 1050 1051 break; 1052 } 1053 1054 /* Write out the command to the device. */ 1055 send_cmd(host, command); 1056 1057 /* Write out column address, if necessary */ 1058 if (column != -1) { 1059 /* 1060 * MXC NANDFC can only perform full page+spare or 1061 * spare-only read/write. When the upper layers perform 1062 * a read/write buffer operation, we will use the saved 1063 * column address to index into the full page. 1064 */ 1065 send_addr(host, 0); 1066 if (host->pagesize_2k) 1067 /* another col addr cycle for 2k page */ 1068 send_addr(host, 0); 1069 } 1070 1071 /* Write out page address, if necessary */ 1072 if (page_addr != -1) { 1073 u32 page_mask = nand_chip->pagemask; 1074 do { 1075 send_addr(host, page_addr & 0xFF); 1076 page_addr >>= 8; 1077 page_mask >>= 8; 1078 } while (page_mask); 1079 } 1080 1081 /* Command post-processing step */ 1082 switch (command) { 1083 1084 case NAND_CMD_RESET: 1085 break; 1086 1087 case NAND_CMD_READOOB: 1088 case NAND_CMD_READ0: 1089 if (host->pagesize_2k) { 1090 /* send read confirm command */ 1091 send_cmd(host, NAND_CMD_READSTART); 1092 /* read for each AREA */ 1093 send_read_page(host, 0, host->spare_only); 1094 if (is_mxc_nfc_1()) { 1095 send_read_page(host, 1, host->spare_only); 1096 send_read_page(host, 2, host->spare_only); 1097 send_read_page(host, 3, host->spare_only); 1098 } 1099 } else { 1100 send_read_page(host, 0, host->spare_only); 1101 } 1102 break; 1103 1104 case NAND_CMD_READID: 1105 host->col_addr = 0; 1106 send_read_id(host); 1107 break; 1108 1109 case NAND_CMD_PAGEPROG: 1110 break; 1111 1112 case NAND_CMD_STATUS: 1113 break; 1114 1115 case NAND_CMD_ERASE2: 1116 break; 1117 } 1118} 1119 1120#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 1121 1122static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 1123static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 1124 1125static struct nand_bbt_descr bbt_main_descr = { 1126 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 1127 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1128 .offs = 0, 1129 .len = 4, 1130 .veroffs = 4, 1131 .maxblocks = 4, 1132 .pattern = bbt_pattern, 1133}; 1134 1135static struct nand_bbt_descr bbt_mirror_descr = { 1136 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 1137 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 1138 .offs = 0, 1139 .len = 4, 1140 .veroffs = 4, 1141 .maxblocks = 4, 1142 .pattern = mirror_pattern, 1143}; 1144 1145#endif 1146 1147int board_nand_init(struct nand_chip *this) 1148{ 1149 struct mtd_info *mtd; 1150#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) 1151 uint32_t tmp; 1152#endif 1153 1154#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 1155 this->bbt_options |= NAND_BBT_USE_FLASH; 1156 this->bbt_td = &bbt_main_descr; 1157 this->bbt_md = &bbt_mirror_descr; 1158#endif 1159 1160 /* structures must be linked */ 1161 mtd = &this->mtd; 1162 host->nand = this; 1163 1164 /* 5 us command delay time */ 1165 this->chip_delay = 5; 1166 1167 nand_set_controller_data(this, host); 1168 this->dev_ready = mxc_nand_dev_ready; 1169 this->cmdfunc = mxc_nand_command; 1170 this->select_chip = mxc_nand_select_chip; 1171 this->read_byte = mxc_nand_read_byte; 1172 this->read_word = mxc_nand_read_word; 1173 this->write_buf = mxc_nand_write_buf; 1174 this->read_buf = mxc_nand_read_buf; 1175 1176 host->regs = (struct mxc_nand_regs __iomem *)CFG_MXC_NAND_REGS_BASE; 1177#ifdef MXC_NFC_V3_2 1178 host->ip_regs = 1179 (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE; 1180#endif 1181 host->clk_act = 1; 1182 1183#ifdef CONFIG_MXC_NAND_HWECC 1184 this->ecc.calculate = mxc_nand_calculate_ecc; 1185 this->ecc.hwctl = mxc_nand_enable_hwecc; 1186 this->ecc.correct = mxc_nand_correct_data; 1187 if (is_mxc_nfc_21() || is_mxc_nfc_32()) { 1188 this->ecc.mode = NAND_ECC_HW_SYNDROME; 1189 this->ecc.read_page = mxc_nand_read_page_syndrome; 1190 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome; 1191 this->ecc.read_oob = mxc_nand_read_oob_syndrome; 1192 this->ecc.write_page = mxc_nand_write_page_syndrome; 1193 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome; 1194 this->ecc.write_oob = mxc_nand_write_oob_syndrome; 1195 this->ecc.bytes = 9; 1196 this->ecc.prepad = 7; 1197 } else { 1198 this->ecc.mode = NAND_ECC_HW; 1199 } 1200 1201 if (is_mxc_nfc_1()) 1202 this->ecc.strength = 1; 1203 else 1204 this->ecc.strength = 4; 1205 1206 host->pagesize_2k = 0; 1207 1208 this->ecc.size = 512; 1209 _mxc_nand_enable_hwecc(mtd, 1); 1210#else 1211 this->ecc.layout = &nand_soft_eccoob; 1212 this->ecc.mode = NAND_ECC_SOFT; 1213 _mxc_nand_enable_hwecc(mtd, 0); 1214#endif 1215 /* Reset NAND */ 1216 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1217 1218 /* NAND bus width determines access functions used by upper layer */ 1219 if (is_16bit_nand()) 1220 this->options |= NAND_BUSWIDTH_16; 1221 1222#ifdef CFG_SYS_NAND_LARGEPAGE 1223 host->pagesize_2k = 1; 1224 this->ecc.layout = &nand_hw_eccoob2k; 1225#else 1226 host->pagesize_2k = 0; 1227 this->ecc.layout = &nand_hw_eccoob; 1228#endif 1229 1230#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 1231#ifdef MXC_NFC_V2_1 1232 tmp = readnfc(&host->regs->config1); 1233 tmp |= NFC_V2_CONFIG1_ONE_CYCLE; 1234 tmp |= NFC_V2_CONFIG1_ECC_MODE_4; 1235 writenfc(tmp, &host->regs->config1); 1236 if (host->pagesize_2k) 1237 writenfc(64/2, &host->regs->spare_area_size); 1238 else 1239 writenfc(16/2, &host->regs->spare_area_size); 1240#endif 1241 1242 /* 1243 * preset operation 1244 * Unlock the internal RAM Buffer 1245 */ 1246 writenfc(0x2, &host->regs->config); 1247 1248 /* Blocks to be unlocked */ 1249 writenfc(0x0, &host->regs->unlockstart_blkaddr); 1250 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the 1251 * unlockend_blkaddr, but the magic 0x4000 does not always work 1252 * when writing more than some 32 megabytes (on 2k page nands) 1253 * However 0xFFFF doesn't seem to have this kind 1254 * of limitation (tried it back and forth several times). 1255 * The linux kernel driver sets this to 0xFFFF for the v2 controller 1256 * only, but probably this was not tested there for v1. 1257 * The very same limitation seems to apply to this kernel driver. 1258 * This might be NAND chip specific and the i.MX31 datasheet is 1259 * extremely vague about the semantics of this register. 1260 */ 1261 writenfc(0xFFFF, &host->regs->unlockend_blkaddr); 1262 1263 /* Unlock Block Command for given address range */ 1264 writenfc(0x4, &host->regs->wrprot); 1265#elif defined(MXC_NFC_V3_2) 1266 writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1); 1267 writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc); 1268 1269 /* Unlock the internal RAM Buffer */ 1270 writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, 1271 &host->ip_regs->wrprot); 1272 1273 /* Blocks to be unlocked */ 1274 for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++) 1275 writenfc(0x0 | 0xFFFF << 16, 1276 &host->ip_regs->wrprot_unlock_blkaddr[tmp]); 1277 1278 writenfc(0, &host->ip_regs->ipc); 1279 1280 tmp = readnfc(&host->ip_regs->config2); 1281 tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK | 1282 NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK); 1283 tmp |= NFC_V3_CONFIG2_ONE_CYCLE; 1284 1285 if (host->pagesize_2k) { 1286 tmp |= NFC_V3_CONFIG2_SPAS(64/2); 1287 tmp |= NFC_V3_CONFIG2_PS_2048; 1288 } else { 1289 tmp |= NFC_V3_CONFIG2_SPAS(16/2); 1290 tmp |= NFC_V3_CONFIG2_PS_512; 1291 } 1292 1293 writenfc(tmp, &host->ip_regs->config2); 1294 1295 tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) | 1296 NFC_V3_CONFIG3_NO_SDMA | 1297 NFC_V3_CONFIG3_RBB_MODE | 1298 NFC_V3_CONFIG3_SBB(6) | /* Reset default */ 1299 NFC_V3_CONFIG3_ADD_OP(0); 1300 1301 if (!(this->options & NAND_BUSWIDTH_16)) 1302 tmp |= NFC_V3_CONFIG3_FW8; 1303 1304 writenfc(tmp, &host->ip_regs->config3); 1305 1306 writenfc(0, &host->ip_regs->delay_line); 1307#endif 1308 1309 return 0; 1310} 1311