1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * RZ/G2L I2C (RIIC) driver 4 * 5 * Copyright (C) 2021-2023 Renesas Electronics Corp. 6 */ 7 8#include <asm/io.h> 9#include <clk.h> 10#include <dm.h> 11#include <dm/device_compat.h> 12#include <errno.h> 13#include <i2c.h> 14#include <linux/bitops.h> 15#include <linux/delay.h> 16#include <reset.h> 17#include <wait_bit.h> 18 19#define RIIC_ICCR1 0x00 20#define RIIC_ICCR2 0x04 21#define RIIC_ICMR1 0x08 22#define RIIC_ICMR2 0x0c 23#define RIIC_ICMR3 0x10 24#define RIIC_ICFER 0x14 25#define RIIC_ICSER 0x18 26#define RIIC_ICIER 0x1c 27#define RIIC_ICSR1 0x20 28#define RIIC_ICSR2 0x24 29#define RIIC_ICSAR0 0x28 30#define RIIC_ICBRL 0x34 31#define RIIC_ICBRH 0x38 32#define RIIC_ICDRT 0x3c 33#define RIIC_ICDRR 0x40 34 35/* ICCR1 */ 36#define ICCR1_ICE BIT(7) 37#define ICCR1_IICRST BIT(6) 38#define ICCR1_CLO BIT(5) 39#define ICCR1_SOWP BIT(4) 40#define ICCR1_SCLO BIT(3) 41#define ICCR1_SDAO BIT(2) 42#define ICCR1_SCLI BIT(1) 43#define ICCR1_SDAI BIT(0) 44 45/* ICCR2 */ 46#define ICCR2_BBSY BIT(7) 47#define ICCR2_MST BIT(6) 48#define ICCR2_TRS BIT(5) 49#define ICCR2_SP BIT(3) 50#define ICCR2_RS BIT(2) 51#define ICCR2_ST BIT(1) 52 53/* ICMR1 */ 54#define ICMR1_MTWP BIT(7) 55#define ICMR1_CKS_MASK GENMASK(6, 4) 56#define ICMR1_BCWP BIT(3) 57#define ICMR1_BC_MASK GENMASK(2, 0) 58 59#define ICMR1_CKS(x) (((x) << 4) & ICMR1_CKS_MASK) 60#define ICMR1_BC(x) ((x) & ICMR1_BC_MASK) 61 62/* ICMR2 */ 63#define ICMR2_DLCS BIT(7) 64#define ICMR2_SDDL_MASK GENMASK(6, 4) 65#define ICMR2_TMOH BIT(2) 66#define ICMR2_TMOL BIT(1) 67#define ICMR2_TMOS BIT(0) 68 69/* ICMR3 */ 70#define ICMR3_SMBS BIT(7) 71#define ICMR3_WAIT BIT(6) 72#define ICMR3_RDRFS BIT(5) 73#define ICMR3_ACKWP BIT(4) 74#define ICMR3_ACKBT BIT(3) 75#define ICMR3_ACKBR BIT(2) 76#define ICMR3_NF_MASK GENMASK(1, 0) 77 78/* ICFER */ 79#define ICFER_FMPE BIT(7) 80#define ICFER_SCLE BIT(6) 81#define ICFER_NFE BIT(5) 82#define ICFER_NACKE BIT(4) 83#define ICFER_SALE BIT(3) 84#define ICFER_NALE BIT(2) 85#define ICFER_MALE BIT(1) 86#define ICFER_TMOE BIT(0) 87 88/* ICSER */ 89#define ICSER_HOAE BIT(7) 90#define ICSER_DIDE BIT(5) 91#define ICSER_GCAE BIT(3) 92#define ICSER_SAR2E BIT(2) 93#define ICSER_SAR1E BIT(1) 94#define ICSER_SAR0E BIT(0) 95 96/* ICIER */ 97#define ICIER_TIE BIT(7) 98#define ICIER_TEIE BIT(6) 99#define ICIER_RIE BIT(5) 100#define ICIER_NAKIE BIT(4) 101#define ICIER_SPIE BIT(3) 102#define ICIER_STIE BIT(2) 103#define ICIER_ALIE BIT(1) 104#define ICIER_TMOIE BIT(0) 105 106/* ICSR1 */ 107#define ICSR1_HOA BIT(7) 108#define ICSR1_DID BIT(5) 109#define ICSR1_GCA BIT(3) 110#define ICSR1_AAS2 BIT(2) 111#define ICSR1_AAS1 BIT(1) 112#define ICSR1_AAS0 BIT(0) 113 114/* ICSR2 */ 115#define ICSR2_TDRE BIT(7) 116#define ICSR2_TEND BIT(6) 117#define ICSR2_RDRF BIT(5) 118#define ICSR2_NACKF BIT(4) 119#define ICSR2_STOP BIT(3) 120#define ICSR2_START BIT(2) 121#define ICSR2_AL BIT(1) 122#define ICSR2_TMOF BIT(0) 123 124/* ICBRH */ 125#define ICBRH_RESERVED GENMASK(7, 5) /* The write value should always be 1 */ 126#define ICBRH_BRH_MASK GENMASK(4, 0) 127 128/* ICBRL */ 129#define ICBRL_RESERVED GENMASK(7, 5) /* The write value should always be 1 */ 130#define ICBRL_BRL_MASK GENMASK(4, 0) 131 132#define RIIC_TIMEOUT_MSEC 100 133 134#define RIIC_FLAG_DEFAULT_SCL_RISE_TIME BIT(0) 135#define RIIC_FLAG_DEFAULT_SCL_FALL_TIME BIT(1) 136 137/* 138 * If SDA is stuck in a low state, the I2C spec says up to 9 clock cycles on SCL 139 * may be needed to unblock whichever other device on the bus is holding SDA low. 140 */ 141#define I2C_DEBLOCK_MAX_CYCLES 9 142 143struct riic_priv { 144 void __iomem *base; 145 struct clk clk; 146 uint bus_speed; 147 u32 scl_rise_ns; 148 u32 scl_fall_ns; 149 u32 flags; 150}; 151 152static int riic_check_busy(struct udevice *dev) 153{ 154 struct riic_priv *priv = dev_get_priv(dev); 155 int ret; 156 157 ret = wait_for_bit_8(priv->base + RIIC_ICCR2, ICCR2_BBSY, 0, 158 RIIC_TIMEOUT_MSEC, 0); 159 if (ret == -ETIMEDOUT) { 160 dev_dbg(dev, "bus is busy!\n"); 161 return -EBUSY; 162 } 163 164 return ret; 165} 166 167static int riic_wait_for_icsr2(struct udevice *dev, u8 bit) 168{ 169 struct riic_priv *priv = dev_get_priv(dev); 170 ulong start = get_timer(0); 171 u8 icsr2; 172 173 /* We can't use wait_for_bit_8() here as we need to check for NACK. */ 174 while (!((icsr2 = readb(priv->base + RIIC_ICSR2)) & bit)) { 175 if (icsr2 & ICSR2_NACKF) 176 return -EIO; 177 if (get_timer(start) > RIIC_TIMEOUT_MSEC) { 178 dev_dbg(dev, "timeout! (bit=%x, icsr2=%x, iccr2=%x)\n", 179 bit, icsr2, readb(priv->base + RIIC_ICCR2)); 180 return -ETIMEDOUT; 181 } 182 udelay(1); 183 schedule(); 184 } 185 186 return 0; 187} 188 189static int riic_check_nack_receive(struct udevice *dev) 190{ 191 struct riic_priv *priv = dev_get_priv(dev); 192 193 if (readb(priv->base + RIIC_ICSR2) & ICSR2_NACKF) { 194 dev_dbg(dev, "received nack!\n"); 195 /* received NACK */ 196 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_NACKF); 197 setbits_8(priv->base + RIIC_ICCR2, ICCR2_SP); 198 readb(priv->base + RIIC_ICDRR); /* dummy read */ 199 return -EIO; 200 } 201 return 0; 202} 203 204static int riic_i2c_raw_write(struct udevice *dev, u8 *buf, size_t len) 205{ 206 struct riic_priv *priv = dev_get_priv(dev); 207 size_t i; 208 int ret; 209 210 for (i = 0; i < len; i++) { 211 ret = riic_check_nack_receive(dev); 212 if (ret < 0) 213 return ret; 214 215 ret = riic_wait_for_icsr2(dev, ICSR2_TDRE); 216 if (ret < 0) 217 return ret; 218 219 writeb(buf[i], priv->base + RIIC_ICDRT); 220 } 221 222 return riic_check_nack_receive(dev); 223} 224 225static int riic_send_start_cond(struct udevice *dev, int restart) 226{ 227 struct riic_priv *priv = dev_get_priv(dev); 228 int ret; 229 230 if (restart) 231 setbits_8(priv->base + RIIC_ICCR2, ICCR2_RS); 232 else 233 setbits_8(priv->base + RIIC_ICCR2, ICCR2_ST); 234 235 ret = riic_wait_for_icsr2(dev, ICSR2_START); 236 if (ret < 0) 237 return ret; 238 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_START); 239 240 return ret; 241} 242 243static int riic_receive_data(struct udevice *dev, struct i2c_msg *msg) 244{ 245 struct riic_priv *priv = dev_get_priv(dev); 246 int ret, stop_ret, i; 247 248 ret = riic_wait_for_icsr2(dev, ICSR2_RDRF); 249 if (ret < 0) 250 goto send_stop; 251 252 ret = riic_check_nack_receive(dev); 253 if (ret < 0) 254 goto send_stop; 255 256 setbits_8(priv->base + RIIC_ICMR3, ICMR3_WAIT | ICMR3_ACKWP | ICMR3_RDRFS); 257 258 /* A dummy read must be performed to trigger data reception */ 259 readb(priv->base + RIIC_ICDRR); 260 261 for (i = 0; i < msg->len; i++) { 262 ret = riic_wait_for_icsr2(dev, ICSR2_RDRF); 263 if (ret < 0) 264 goto send_stop; 265 266 if (i == (msg->len - 1)) { 267 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_STOP); 268 setbits_8(priv->base + RIIC_ICCR2, ICCR2_SP); 269 setbits_8(priv->base + RIIC_ICMR3, ICMR3_ACKBT); 270 } else { 271 clrbits_8(priv->base + RIIC_ICMR3, ICMR3_ACKBT); 272 } 273 274 msg->buf[i] = readb(priv->base + RIIC_ICDRR); 275 }; 276 277send_stop: 278 if (ret) { 279 /* 280 * We got here due to an error condition, so we need to perform 281 * a dummy read to issue the stop bit. 282 */ 283 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_STOP); 284 setbits_8(priv->base + RIIC_ICCR2, ICCR2_SP); 285 readb(priv->base + RIIC_ICDRR); 286 } 287 stop_ret = riic_wait_for_icsr2(dev, ICSR2_STOP); 288 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_STOP | ICSR2_NACKF); 289 clrbits_8(priv->base + RIIC_ICMR3, ICMR3_WAIT | ICMR3_ACKWP | ICMR3_RDRFS); 290 return ret ? ret : stop_ret; 291} 292 293static int riic_transmit_stop(struct udevice *dev) 294{ 295 struct riic_priv *priv = dev_get_priv(dev); 296 int ret; 297 298 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_STOP); 299 setbits_8(priv->base + RIIC_ICCR2, ICCR2_SP); 300 301 ret = riic_wait_for_icsr2(dev, ICSR2_STOP); 302 clrbits_8(priv->base + RIIC_ICSR2, ICSR2_STOP | ICSR2_NACKF); 303 return ret; 304} 305 306static int riic_transmit_data(struct udevice *dev, struct i2c_msg *msg) 307{ 308 int ret, stop_ret; 309 310 ret = riic_i2c_raw_write(dev, msg->buf, msg->len); 311 if (ret < 0) 312 goto send_stop; 313 314 ret = riic_wait_for_icsr2(dev, ICSR2_TEND); 315 if (ret < 0) 316 goto send_stop; 317 318 if (!ret && !(msg->flags & I2C_M_STOP)) 319 return 0; 320 321send_stop: 322 stop_ret = riic_transmit_stop(dev); 323 return ret ? ret : stop_ret; 324} 325 326static int riic_xfer_one(struct udevice *dev, struct i2c_msg *msg, int first_msg) 327{ 328 u8 addr_byte = ((msg->addr << 1) | (msg->flags & I2C_M_RD)); 329 int ret; 330 331 if (!(msg->flags & I2C_M_NOSTART)) { 332 /* 333 * Send a start for the first message and a restart for 334 * subsequent messages. 335 */ 336 ret = riic_send_start_cond(dev, !first_msg); 337 if (ret < 0) 338 return ret; 339 } 340 341 ret = riic_i2c_raw_write(dev, &addr_byte, 1); 342 if (ret < 0) { 343 /* 344 * We're aborting the transfer while still in master transmit 345 * mode. 346 */ 347 riic_transmit_stop(dev); 348 return ret; 349 } 350 351 if (msg->flags & I2C_M_RD) 352 return riic_receive_data(dev, msg); 353 354 return riic_transmit_data(dev, msg); 355} 356 357static int riic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) 358{ 359 int ret, i; 360 361 ret = riic_check_busy(dev); 362 if (ret < 0) 363 return ret; 364 365 /* Ensure that the last message is terminated with a stop bit. */ 366 msg[nmsgs - 1].flags |= I2C_M_STOP; 367 368 for (i = 0; i < nmsgs; i++) { 369 ret = riic_xfer_one(dev, &msg[i], !i); 370 if (ret) 371 return ret; 372 } 373 374 return 0; 375} 376 377static int riic_deblock(struct udevice *dev) 378{ 379 struct riic_priv *priv = dev_get_priv(dev); 380 int i = 0; 381 382 /* 383 * Issue clock cycles on SCL to hopefully unblock whatever is holding 384 * SDA low. These clock cycles may trigger error conditions such as 385 * Arbitration Lost, so we clear the status bits in ICSR2 after each 386 * cycle. 387 */ 388 while (!(readb(priv->base + RIIC_ICCR1) & ICCR1_SDAI)) { 389 if (i++ == I2C_DEBLOCK_MAX_CYCLES) 390 return -EIO; 391 392 setbits_8(priv->base + RIIC_ICCR1, ICCR1_CLO); 393 if (wait_for_bit_8(priv->base + RIIC_ICCR1, ICCR1_CLO, 0, 394 RIIC_TIMEOUT_MSEC, false)) 395 return -ETIMEDOUT; 396 writeb(0, priv->base + RIIC_ICSR2); 397 } 398 399 /* 400 * We have released SDA, but the I2C module is now out of sync 401 * with the bus state, so we need to reset its state machine. 402 */ 403 setbits_8(priv->base + RIIC_ICCR1, ICCR1_IICRST); 404 clrbits_8(priv->base + RIIC_ICCR1, ICCR1_IICRST); 405 406 return 0; 407} 408 409static int riic_set_bus_speed(struct udevice *dev, uint bus_speed) 410{ 411 struct riic_priv *priv = dev_get_priv(dev); 412 ulong refclk; 413 uint total_ticks, cks, brl, brh; 414 415 if (bus_speed > I2C_SPEED_FAST_PLUS_RATE) { 416 dev_err(dev, "unsupported bus speed (%dHz). %d max\n", bus_speed, 417 I2C_SPEED_FAST_PLUS_RATE); 418 return -EINVAL; 419 } 420 421 /* 422 * Assume the default register settings: 423 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles) 424 * FER.NFE = 1 (noise circuit enabled) 425 * MR3.NF = 0 (1 cycle of noise filtered out) 426 * 427 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1) 428 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1) 429 */ 430 431 /* 432 * Determine reference clock rate. We must be able to get the desired 433 * frequency with only 62 clock ticks max (31 high, 31 low). 434 * Aim for a duty of 60% LOW, 40% HIGH. 435 */ 436 refclk = clk_get_rate(&priv->clk); 437 total_ticks = DIV_ROUND_UP(refclk, bus_speed ?: 1); 438 439 for (cks = 0; cks < 7; cks++) { 440 /* 441 * 60% low time must be less than BRL + 2 + 1 442 * BRL max register value is 0x1F. 443 */ 444 brl = ((total_ticks * 6) / 10); 445 if (brl <= (0x1f + 3)) 446 break; 447 448 total_ticks /= 2; 449 refclk /= 2; 450 } 451 452 if (brl > (0x1f + 3)) { 453 dev_err(dev, "invalid speed (%u). Too slow.\n", bus_speed); 454 return -EINVAL; 455 } 456 457 brh = total_ticks - brl; 458 459 /* Remove automatic clock ticks for sync circuit and NF */ 460 if (cks == 0) { 461 brl -= 4; 462 brh -= 4; 463 } else { 464 brl -= 3; 465 brh -= 3; 466 } 467 468 /* 469 * If SCL rise and fall times weren't set in the device tree, set them 470 * based on the desired bus speed and the maximum timings given in the 471 * I2C specification. 472 */ 473 if (priv->flags & RIIC_FLAG_DEFAULT_SCL_RISE_TIME) 474 priv->scl_rise_ns = bus_speed <= I2C_SPEED_STANDARD_RATE ? 1000 : 475 bus_speed <= I2C_SPEED_FAST_RATE ? 300 : 120; 476 if (priv->flags & RIIC_FLAG_DEFAULT_SCL_FALL_TIME) 477 priv->scl_fall_ns = bus_speed <= I2C_SPEED_FAST_RATE ? 300 : 120; 478 479 /* 480 * Remove clock ticks for rise and fall times. Convert ns to clock 481 * ticks. 482 */ 483 brl -= priv->scl_fall_ns / (1000000000 / refclk); 484 brh -= priv->scl_rise_ns / (1000000000 / refclk); 485 486 /* Adjust for min register values for when SCLE=1 and NFE=1 */ 487 if (brl < 1) 488 brl = 1; 489 if (brh < 1) 490 brh = 1; 491 492 priv->bus_speed = refclk / total_ticks; 493 dev_dbg(dev, "freq=%u, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n", 494 priv->bus_speed, ((brl + 3) * 100) / (brl + brh + 6), 495 priv->scl_fall_ns / (1000000000 / refclk), 496 priv->scl_rise_ns / (1000000000 / refclk), cks, brl, brh); 497 498 setbits_8(priv->base + RIIC_ICCR1, ICCR1_IICRST); 499 writeb(ICMR1_CKS(cks), priv->base + RIIC_ICMR1); 500 writeb(brh | ICBRH_RESERVED, priv->base + RIIC_ICBRH); 501 writeb(brl | ICBRL_RESERVED, priv->base + RIIC_ICBRL); 502 clrbits_8(priv->base + RIIC_ICCR1, ICCR1_IICRST); 503 504 return 0; 505} 506 507static int riic_get_bus_speed(struct udevice *dev) 508{ 509 struct riic_priv *priv = dev_get_priv(dev); 510 511 return priv->bus_speed; 512} 513 514static const struct dm_i2c_ops riic_ops = { 515 .xfer = riic_xfer, 516 .deblock = riic_deblock, 517 .set_bus_speed = riic_set_bus_speed, 518 .get_bus_speed = riic_get_bus_speed, 519}; 520 521static int riic_init_setting(struct udevice *dev) 522{ 523 struct riic_priv *priv = dev_get_priv(dev); 524 int ret; 525 526 clrbits_8(priv->base + RIIC_ICCR1, ICCR1_ICE); 527 setbits_8(priv->base + RIIC_ICCR1, ICCR1_IICRST); 528 setbits_8(priv->base + RIIC_ICCR1, ICCR1_ICE); 529 530 /* 531 * Set a default bitrate. The rate may be overridden based on the device 532 * tree as part of i2c_post_probe(). 533 */ 534 ret = riic_set_bus_speed(dev, I2C_SPEED_STANDARD_RATE); 535 if (ret < 0) 536 goto err; 537 538 clrbits_8(priv->base + RIIC_ICCR1, ICCR1_IICRST); 539 540 /* Make sure the bus is not stuck. */ 541 if (!(readb(priv->base + RIIC_ICCR1) & ICCR1_SDAI)) { 542 dev_dbg(dev, "clearing SDA low state\n"); 543 ret = riic_deblock(dev); 544 if (ret) { 545 dev_err(dev, "failed to clear SDA low state!\n"); 546 goto err; 547 } 548 } 549 return 0; 550 551err: 552 clrbits_8(priv->base + RIIC_ICCR1, ICCR1_ICE | ICCR1_IICRST); 553 return ret; 554} 555 556static int riic_probe(struct udevice *dev) 557{ 558 struct riic_priv *priv = dev_get_priv(dev); 559 struct reset_ctl rst; 560 int ret; 561 562 priv->base = dev_read_addr_ptr(dev); 563 564 ret = dev_read_u32(dev, "i2c-scl-rising-time-ns", &priv->scl_rise_ns); 565 if (ret) 566 priv->flags |= RIIC_FLAG_DEFAULT_SCL_RISE_TIME; 567 ret = dev_read_u32(dev, "i2c-scl-falling-time-ns", &priv->scl_fall_ns); 568 if (ret) 569 priv->flags |= RIIC_FLAG_DEFAULT_SCL_FALL_TIME; 570 571 ret = clk_get_by_index(dev, 0, &priv->clk); 572 if (ret) { 573 dev_err(dev, "failed to get clock\n"); 574 return ret; 575 } 576 577 ret = clk_enable(&priv->clk); 578 if (ret) { 579 dev_err(dev, "failed to enable clock\n"); 580 return ret; 581 } 582 583 ret = reset_get_by_index(dev, 0, &rst); 584 if (ret < 0) { 585 dev_err(dev, "failed to get reset line\n"); 586 goto err_get_reset; 587 } 588 589 ret = reset_deassert(&rst); 590 if (ret < 0) { 591 dev_err(dev, "failed to de-assert reset line\n"); 592 goto err_reset; 593 } 594 595 ret = riic_init_setting(dev); 596 if (ret < 0) { 597 dev_err(dev, "failed to init i2c bus interface\n"); 598 goto err_init; 599 } 600 601 return 0; 602 603err_init: 604 reset_assert(&rst); 605err_reset: 606 reset_free(&rst); 607err_get_reset: 608 clk_disable(&priv->clk); 609 return ret; 610} 611 612static const struct udevice_id riic_ids[] = { 613 { .compatible = "renesas,riic-rz", }, 614 { /* sentinel */ } 615}; 616 617U_BOOT_DRIVER(riic_i2c) = { 618 .name = "riic-i2c", 619 .id = UCLASS_I2C, 620 .of_match = riic_ids, 621 .probe = riic_probe, 622 .priv_auto = sizeof(struct riic_priv), 623 .ops = &riic_ops, 624}; 625