1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6#include <common.h>
7#include <altera.h>
8#include <log.h>
9#include <spi.h>
10#include <asm/io.h>
11#include <linux/delay.h>
12#include <linux/errno.h>
13
14/* Write the RBF data to FPGA via SPI */
15static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
16			 unsigned long rbf_size)
17{
18	struct spi_slave *slave;
19	int ret;
20
21	debug("%s (%d): data=%p size=%ld\n",
22	      __func__, __LINE__, rbf_data, rbf_size);
23
24	/* FIXME: How to get the max. SPI clock and SPI mode? */
25	slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
26	if (!slave)
27		return -1;
28
29	if (spi_claim_bus(slave))
30		return -1;
31
32	ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
33		       SPI_XFER_BEGIN | SPI_XFER_END);
34
35	spi_release_bus(slave);
36
37	return ret;
38}
39
40/*
41 * This is the interface used by FPGA driver.
42 * Return 0 for sucess, non-zero for error.
43 */
44int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
45{
46	altera_board_specific_func *pfns = desc->iface_fns;
47	int cookie = desc->cookie;
48	int spi_bus;
49	int spi_dev;
50	int ret = 0;
51
52	if ((u32)rbf_data & 0x3) {
53		puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
54		return -EINVAL;
55	}
56
57	/* Run the pre configuration function if there is one */
58	if (pfns->pre)
59		(pfns->pre)(cookie);
60
61	/* Establish the initial state */
62	if (pfns->config) {
63		/* De-assert nCONFIG */
64		(pfns->config)(false, true, cookie);
65
66		/* nConfig minimum low pulse width is 2us */
67		udelay(200);
68
69		/* Assert nCONFIG */
70		(pfns->config)(true, true, cookie);
71
72		/* nCONFIG high to first rising clock on DCLK min 1506 us */
73		udelay(1600);
74	}
75
76	/* Write the RBF data to FPGA */
77	if (pfns->write) {
78		/*
79		 * Use board specific data function to write bitstream
80		 * into the FPGA
81		 */
82		ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
83	} else {
84		/*
85		 * Use common SPI functions to write bitstream into the
86		 * FPGA
87		 */
88		spi_bus = COOKIE2SPI_BUS(cookie);
89		spi_dev = COOKIE2SPI_DEV(cookie);
90		ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
91	}
92	if (ret)
93		return ret;
94
95	/* Check done pin */
96	if (pfns->done) {
97		ret = (pfns->done)(cookie);
98
99		if (ret)
100			printf("Error: DONE not set (ret=%d)!\n", ret);
101	}
102
103	return ret;
104}
105