1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6#ifndef __AXP_TRAINING_STATIC_H
7#define __AXP_TRAINING_STATIC_H
8
9/*
10 * STATIC_TRAINING - Set only if static parameters for training are set and
11 * required
12 */
13
14MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = {
15	/* Read Leveling */
16	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
17	/*0     */
18	{0x000016A0, 0xC002011A},
19	/*1 */
20	{0x000016A0, 0xC0420100},
21	/*2 */
22	{0x000016A0, 0xC082020A},
23	/*3 */
24	{0x000016A0, 0xC0C20017},
25	/*4 */
26	{0x000016A0, 0xC1020113},
27	/*5 */
28	{0x000016A0, 0xC1420107},
29	/*6 */
30	{0x000016A0, 0xC182011F},
31	/*7 */
32	{0x000016A0, 0xC1C2001C},
33	/*8 */
34	{0x000016A0, 0xC202010D},
35
36	/* Write Leveling */
37	/*0 */
38	{0x000016A0, 0xC0004A06},
39	/*1 */
40	{0x000016A0, 0xC040690D},
41	/*2 */
42	{0x000016A0, 0xC0806A0D},
43	/*3 */
44	{0x000016A0, 0xC0C0A01B},
45	/*4 */
46	{0x000016A0, 0xC1003A01},
47	/*5 */
48	{0x000016A0, 0xC1408113},
49	/*6 */
50	{0x000016A0, 0xC1805609},
51	/*7 */
52	{0x000016A0, 0xC1C04504},
53	/*8 */
54	{0x000016A0, 0xC2009518},
55
56	/*center DQS on read cycle */
57	{0x000016A0, 0xC803000F},
58
59	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
60	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
61
62	/*init DRAM */
63	{0x00001480, 0x00000001},
64	{0x0, 0x0}
65};
66
67MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = {
68	/* Read Leveling */
69	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
70	/*0     */
71	{0x000016A0, 0xC0020301},
72	/*1 */
73	{0x000016A0, 0xC0420202},
74	/*2 */
75	{0x000016A0, 0xC0820314},
76	/*3 */
77	{0x000016A0, 0xC0C20117},
78	/*4 */
79	{0x000016A0, 0xC1020219},
80	/*5 */
81	{0x000016A0, 0xC142020B},
82	/*6 */
83	{0x000016A0, 0xC182030A},
84	/*7 */
85	{0x000016A0, 0xC1C2011D},
86	/*8 */
87	{0x000016A0, 0xC2020212},
88
89	/* Write Leveling */
90	/*0 */
91	{0x000016A0, 0xC0007A12},
92	/*1 */
93	{0x000016A0, 0xC0408D16},
94	/*2 */
95	{0x000016A0, 0xC0809E1B},
96	/*3 */
97	{0x000016A0, 0xC0C0AC1F},
98	/*4 */
99	{0x000016A0, 0xC1005E0A},
100	/*5 */
101	{0x000016A0, 0xC140A91D},
102	/*6 */
103	{0x000016A0, 0xC1808E17},
104	/*7 */
105	{0x000016A0, 0xC1C05509},
106	/*8 */
107	{0x000016A0, 0xC2003A01},
108
109	/* PBS Leveling */
110	/*0 */
111	{0x000016A0, 0xC0007A12},
112	/*1 */
113	{0x000016A0, 0xC0408D16},
114	/*2 */
115	{0x000016A0, 0xC0809E1B},
116	/*3 */
117	{0x000016A0, 0xC0C0AC1F},
118	/*4 */
119	{0x000016A0, 0xC1005E0A},
120	/*5 */
121	{0x000016A0, 0xC140A91D},
122	/*6 */
123	{0x000016A0, 0xC1808E17},
124	/*7 */
125	{0x000016A0, 0xC1C05509},
126	/*8 */
127	{0x000016A0, 0xC2003A01},
128
129	/*center DQS on read cycle */
130	{0x000016A0, 0xC803000B},
131
132	{0x00001538, 0x0000000D},	/*Read Data Sample Delays Register */
133	{0x0000153C, 0x00000011},	/*Read Data Ready Delay Register */
134
135	/*init DRAM */
136	{0x00001480, 0x00000001},
137	{0x0, 0x0}
138};
139
140MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
141	/* Read Leveling */
142	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
143	/*0             2               4               15 */
144	{0x000016A0, 0xC002010C},
145	/*1             2               4               2 */
146	{0x000016A0, 0xC042001C},
147	/*2             2               4               27 */
148	{0x000016A0, 0xC0820115},
149	/*3             2               4               0 */
150	{0x000016A0, 0xC0C20019},
151	/*4             2               4               13 */
152	{0x000016A0, 0xC1020108},
153	/*5             2               4               5 */
154	{0x000016A0, 0xC1420100},
155	/*6             2               4               19 */
156	{0x000016A0, 0xC1820111},
157	/*7             2               4               0 */
158	{0x000016A0, 0xC1C2001B},
159	/*8             2               4               10 */
160	/*{0x000016A0, 0xC2020117}, */
161	{0x000016A0, 0xC202010C},
162
163	/* Write Leveling */
164	/*0 */
165	{0x000016A0, 0xC0005508},
166	/*1 */
167	{0x000016A0, 0xC0409819},
168	/*2 */
169	{0x000016A0, 0xC080650C},
170	/*3 */
171	{0x000016A0, 0xC0C0700F},
172	/*4 */
173	{0x000016A0, 0xC1004103},
174	/*5 */
175	{0x000016A0, 0xC140A81D},
176	/*6 */
177	{0x000016A0, 0xC180650C},
178	/*7 */
179	{0x000016A0, 0xC1C08013},
180	/*8 */
181	{0x000016A0, 0xC2005508},
182
183	/*center DQS on read cycle */
184	{0x000016A0, 0xC803000F},
185
186	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
187	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
188
189	/*init DRAM */
190	{0x00001480, 0x00000001},
191	{0x0, 0x0}
192};
193
194MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = {
195	/* Read Leveling */
196	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
197	/*0             2               4               15 */
198	{0x000016A0, 0xC002040C},
199	/*1             2               4               2 */
200	{0x000016A0, 0xC0420117},
201	/*2             2               4               27 */
202	{0x000016A0, 0xC082041B},
203	/*3             2               4               0 */
204	{0x000016A0, 0xC0C20117},
205	/*4             2               4               13 */
206	{0x000016A0, 0xC102040A},
207	/*5             2               4               5 */
208	{0x000016A0, 0xC1420117},
209	/*6             2               4               19 */
210	{0x000016A0, 0xC1820419},
211	/*7             2               4               0 */
212	{0x000016A0, 0xC1C20117},
213	/*8             2               4               10 */
214	{0x000016A0, 0xC2020117},
215
216	/* Write Leveling */
217	/*0 */
218	{0x000016A0, 0xC0008113},
219	/*1 */
220	{0x000016A0, 0xC0404504},
221	/*2 */
222	{0x000016A0, 0xC0808514},
223	/*3 */
224	{0x000016A0, 0xC0C09418},
225	/*4 */
226	{0x000016A0, 0xC1006D0E},
227	/*5 */
228	{0x000016A0, 0xC1405508},
229	/*6 */
230	{0x000016A0, 0xC1807D12},
231	/*7 */
232	{0x000016A0, 0xC1C0b01F},
233	/*8 */
234	{0x000016A0, 0xC2005D0A},
235
236	/*center DQS on read cycle */
237	{0x000016A0, 0xC803000F},
238
239	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
240	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
241
242	/*init DRAM */
243	{0x00001480, 0x00000001},
244	{0x0, 0x0}
245};
246
247MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
248	/* Read Leveling */
249	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
250	/*0             2               3               1 */
251	{0x000016A0, 0xC0020104},
252	/*1             2               2               6 */
253	{0x000016A0, 0xC0420010},
254	/*2             2               3               16 */
255	{0x000016A0, 0xC0820112},
256	/*3             2               1               26 */
257	{0x000016A0, 0xC0C20009},
258	/*4             2               2               29 */
259	{0x000016A0, 0xC102001F},
260	/*5             2               2               13 */
261	{0x000016A0, 0xC1420014},
262	/*6             2               3               6 */
263	{0x000016A0, 0xC1820109},
264	/*7             2               1               31 */
265	{0x000016A0, 0xC1C2000C},
266	/*8             2               2               22 */
267	{0x000016A0, 0xC2020112},
268
269	/* Write Leveling */
270	/*0 */
271	{0x000016A0, 0xC0009919},
272	/*1 */
273	{0x000016A0, 0xC0405508},
274	/*2 */
275	{0x000016A0, 0xC0809919},
276	/*3 */
277	{0x000016A0, 0xC0C09C1A},
278	/*4 */
279	{0x000016A0, 0xC1008113},
280	/*5 */
281	{0x000016A0, 0xC140650C},
282	/*6 */
283	{0x000016A0, 0xC1809518},
284	/*7 */
285	{0x000016A0, 0xC1C04103},
286	/*8 */
287	{0x000016A0, 0xC2006D0E},
288
289	/*center DQS on read cycle */
290	{0x000016A0, 0xC803000F},
291
292	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
293	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
294	/*init DRAM */
295	{0x00001480, 0x00000001},
296	{0x0, 0x0}
297};
298
299MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
300
301	/* Read Leveling */
302	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
303	/*0             2               3               1 */
304	{0x000016A0, 0xC0020103},
305	/*1            2               2               6 */
306	{0x000016A0, 0xC0420012},
307	/*2            2               3               16 */
308	{0x000016A0, 0xC0820113},
309	/*3            2               1               26 */
310	{0x000016A0, 0xC0C20012},
311	/*4            2               2               29 */
312	{0x000016A0, 0xC1020100},
313	/*5            2               2               13 */
314	{0x000016A0, 0xC1420016},
315	/*6            2               3               6 */
316	{0x000016A0, 0xC1820109},
317	/*7            2               1               31 */
318	{0x000016A0, 0xC1C20010},
319	/*8            2               2               22 */
320	{0x000016A0, 0xC2020112},
321
322	/* Write Leveling */
323	/*0 */
324	{0x000016A0, 0xC000b11F},
325	/*1 */
326	{0x000016A0, 0xC040690D},
327	/*2 */
328	{0x000016A0, 0xC0803600},
329	/*3 */
330	{0x000016A0, 0xC0C0a81D},
331	/*4 */
332	{0x000016A0, 0xC1009919},
333	/*5 */
334	{0x000016A0, 0xC1407911},
335	/*6 */
336	{0x000016A0, 0xC180ad1e},
337	/*7 */
338	{0x000016A0, 0xC1C04d06},
339	/*8 */
340	{0x000016A0, 0xC2008514},
341
342	/*center DQS on read cycle */
343	{0x000016A0, 0xC803000F},
344
345	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
346	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
347
348	/*init DRAM */
349	{0x00001480, 0x00000001},
350	{0x0, 0x0}
351};
352
353MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = {
354
355	/* Read Leveling */
356	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
357	/*0             2               3               1 */
358	{0x000016A0, 0xC0020213},
359	/*1            2               2               6 */
360	{0x000016A0, 0xC0420108},
361	/*2            2               3               16 */
362	{0x000016A0, 0xC0820210},
363	/*3            2               1               26 */
364	{0x000016A0, 0xC0C20108},
365	/*4            2               2               29 */
366	{0x000016A0, 0xC102011A},
367	/*5            2               2               13 */
368	{0x000016A0, 0xC1420300},
369	/*6            2               3               6 */
370	{0x000016A0, 0xC1820204},
371	/*7            2               1               31 */
372	{0x000016A0, 0xC1C20106},
373	/*8            2               2               22 */
374	{0x000016A0, 0xC2020112},
375
376	/* Write Leveling */
377	/*0 */
378	{0x000016A0, 0xC000620B},
379	/*1 */
380	{0x000016A0, 0xC0408D16},
381	/*2 */
382	{0x000016A0, 0xC0806A0D},
383	/*3 */
384	{0x000016A0, 0xC0C03D02},
385	/*4 */
386	{0x000016A0, 0xC1004a05},
387	/*5 */
388	{0x000016A0, 0xC140A11B},
389	/*6 */
390	{0x000016A0, 0xC1805E0A},
391	/*7 */
392	{0x000016A0, 0xC1C06D0E},
393	/*8 */
394	{0x000016A0, 0xC200AD1E},
395
396	/*center DQS on read cycle */
397	{0x000016A0, 0xC803000F},
398
399	{0x00001538, 0x0000000C},	/*Read Data Sample Delays Register */
400	{0x0000153C, 0x0000000E},	/*Read Data Ready Delay Register */
401
402	/*init DRAM */
403	{0x00001480, 0x00000001},
404	{0x0, 0x0}
405};
406
407MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = {
408	/* Read Leveling */
409	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
410	/*0 */
411	{0x000016A0, 0xC002010E},
412	/*1 */
413	{0x000016A0, 0xC042001E},
414	/*2 */
415	{0x000016A0, 0xC0820118},
416	/*3 */
417	{0x000016A0, 0xC0C2001E},
418	/*4 */
419	{0x000016A0, 0xC102010C},
420	/*5 */
421	{0x000016A0, 0xC1420102},
422	/*6 */
423	{0x000016A0, 0xC1820111},
424	/*7 */
425	{0x000016A0, 0xC1C2001C},
426	/*8 */
427	{0x000016A0, 0xC2020109},
428
429	/* Write Leveling */
430	/*0 */
431	{0x000016A0, 0xC0003600},
432	/*1 */
433	{0x000016A0, 0xC040690D},
434	/*2 */
435	{0x000016A0, 0xC0805207},
436	/*3 */
437	{0x000016A0, 0xC0C0A81D},
438	/*4 */
439	{0x000016A0, 0xC1009919},
440	/*5 */
441	{0x000016A0, 0xC1407911},
442	/*6 */
443	{0x000016A0, 0xC1803E02},
444	/*7 */
445	{0x000016A0, 0xC1C05107},
446	/*8 */
447	{0x000016A0, 0xC2008113},
448
449	/*center DQS on read cycle */
450	{0x000016A0, 0xC803000F},
451
452	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
453	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
454
455	/*init DRAM */
456	{0x00001480, 0x00000001},
457	{0x0, 0x0}
458};
459
460MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = {
461	/* Read Leveling */
462	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
463	/*0 */
464	{0x000016A0, 0xC0020106},
465	/*1 */
466	{0x000016A0, 0xC0420016},
467	/*2 */
468	{0x000016A0, 0xC0820117},
469	/*3 */
470	{0x000016A0, 0xC0C2000F},
471	/*4 */
472	{0x000016A0, 0xC1020105},
473	/*5 */
474	{0x000016A0, 0xC142001B},
475	/*6 */
476	{0x000016A0, 0xC182010C},
477	/*7 */
478	{0x000016A0, 0xC1C20011},
479	/*8 */
480	{0x000016A0, 0xC2020101},
481
482	/* Write Leveling */
483	/*0 */
484	{0x000016A0, 0xC0003600},
485	/*1 */
486	{0x000016A0, 0xC0406D0E},
487	/*2 */
488	{0x000016A0, 0xC0803600},
489	/*3 */
490	{0x000016A0, 0xC0C04504},
491	/*4 */
492	{0x000016A0, 0xC1009919},
493	/*5 */
494	{0x000016A0, 0xC1407911},
495	/*6 */
496	{0x000016A0, 0xC1803600},
497	/*7 */
498	{0x000016A0, 0xC1C0610B},
499	/*8 */
500	{0x000016A0, 0xC2008113},
501
502	/*center DQS on read cycle */
503	{0x000016A0, 0xC803000F},
504
505	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
506	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
507
508	/*init DRAM */
509	{0x00001480, 0x00000001},
510	{0x0, 0x0}
511};
512
513MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = {
514	/* Read Leveling */
515	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
516	/*0 */
517	{0x000016A0, 0xC002010C},
518	/*1 */
519	{0x000016A0, 0xC042001B},
520	/*2 */
521	{0x000016A0, 0xC082011D},
522	/*3 */
523	{0x000016A0, 0xC0C20015},
524	/*4 */
525	{0x000016A0, 0xC102010B},
526	/*5 */
527	{0x000016A0, 0xC1420101},
528	/*6 */
529	{0x000016A0, 0xC1820113},
530	/*7 */
531	{0x000016A0, 0xC1C20017},
532	/*8 */
533	{0x000016A0, 0xC2020107},
534
535	/* Write Leveling */
536	/*0 */
537	{0x000016A0, 0xC0003600},
538	/*1 */
539	{0x000016A0, 0xC0406D0E},
540	/*2 */
541	{0x000016A0, 0xC0803600},
542	/*3 */
543	{0x000016A0, 0xC0C04504},
544	/*4 */
545	{0x000016A0, 0xC1009919},
546	/*5 */
547	{0x000016A0, 0xC1407911},
548	/*6 */
549	{0x000016A0, 0xC180B11F},
550	/*7 */
551	{0x000016A0, 0xC1C0610B},
552	/*8 */
553	{0x000016A0, 0xC2008113},
554
555	/*center DQS on read cycle */
556	{0x000016A0, 0xC803000F},
557
558	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
559	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
560
561	/*init DRAM */
562	{0x00001480, 0x00000001},
563	{0x0, 0x0}
564};
565
566MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = {
567	/* Read Leveling */
568	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
569	/* CS 0 */
570	/*0             2               3               1 */
571	{0x000016A0, 0xC0020103},
572	/*1            2               2               6 */
573	{0x000016A0, 0xC0420012},
574	/*2            2               3               16 */
575	{0x000016A0, 0xC0820113},
576	/*3            2               1               26 */
577	{0x000016A0, 0xC0C20012},
578	/*4            2               2               29 */
579	{0x000016A0, 0xC1020100},
580	/*5            2               2               13 */
581	{0x000016A0, 0xC1420016},
582	/*6            2               3               6 */
583	{0x000016A0, 0xC1820109},
584	/*7            2               1               31 */
585	{0x000016A0, 0xC1C20010},
586	/*8            2               2               22 */
587	{0x000016A0, 0xC2020112},
588
589	/* Write Leveling */
590	/*0 */
591	{0x000016A0, 0xC000b11F},
592	/*1 */
593	{0x000016A0, 0xC040690D},
594	/*2 */
595	{0x000016A0, 0xC0803600},
596	/*3 */
597	{0x000016A0, 0xC0C0a81D},
598	/*4 */
599	{0x000016A0, 0xC1009919},
600	/*5 */
601	{0x000016A0, 0xC1407911},
602	/*6 */
603	{0x000016A0, 0xC180ad1e},
604	/*7 */
605	{0x000016A0, 0xC1C04d06},
606	/*8 */
607	{0x000016A0, 0xC2008514},
608
609	/*center DQS on read cycle */
610	{0x000016A0, 0xC803000F},
611
612	/* CS 1 */
613
614	{0x000016A0, 0xC0060103},
615	/*1            2               2               6 */
616	{0x000016A0, 0xC0460012},
617	/*2            2               3               16 */
618	{0x000016A0, 0xC0860113},
619	/*3            2               1               26 */
620	{0x000016A0, 0xC0C60012},
621	/*4            2               2               29 */
622	{0x000016A0, 0xC1060100},
623	/*5            2               2               13 */
624	{0x000016A0, 0xC1460016},
625	/*6            2               3               6 */
626	{0x000016A0, 0xC1860109},
627	/*7            2               1               31 */
628	{0x000016A0, 0xC1C60010},
629	/*8            2               2               22 */
630	{0x000016A0, 0xC2060112},
631
632	/* Write Leveling */
633	/*0 */
634	{0x000016A0, 0xC004b11F},
635	/*1 */
636	{0x000016A0, 0xC044690D},
637	/*2 */
638	{0x000016A0, 0xC0843600},
639	/*3 */
640	{0x000016A0, 0xC0C4a81D},
641	/*4 */
642	{0x000016A0, 0xC1049919},
643	/*5 */
644	{0x000016A0, 0xC1447911},
645	/*6 */
646	{0x000016A0, 0xC184ad1e},
647	/*7 */
648	{0x000016A0, 0xC1C44d06},
649	/*8 */
650	{0x000016A0, 0xC2048514},
651
652	/*center DQS on read cycle */
653	{0x000016A0, 0xC807000F},
654
655	/* Both CS */
656
657	{0x00001538, 0x00000B0B},	/*Read Data Sample Delays Register */
658	{0x0000153C, 0x00000F0F},	/*Read Data Ready Delay Register */
659
660	/*init DRAM */
661	{0x00001480, 0x00000001},
662	{0x0, 0x0}
663};
664
665MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = {
666	/* Read Leveling */
667	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
668	/*0 */
669	{0x000016A0, 0xC0020118},
670	/*1 */
671	{0x000016A0, 0xC0420108},
672	/*2 */
673	{0x000016A0, 0xC0820202},
674	/*3 */
675	{0x000016A0, 0xC0C20108},
676	/*4 */
677	{0x000016A0, 0xC1020117},
678	/*5 */
679	{0x000016A0, 0xC142010C},
680	/*6 */
681	{0x000016A0, 0xC182011B},
682	/*7 */
683	{0x000016A0, 0xC1C20107},
684	/*8 */
685	{0x000016A0, 0xC2020113},
686
687	/* Write Leveling */
688	/*0 */
689	{0x000016A0, 0xC0003600},
690	/*1 */
691	{0x000016A0, 0xC0406D0E},
692	/*2 */
693	{0x000016A0, 0xC0805207},
694	/*3 */
695	{0x000016A0, 0xC0C0A81D},
696	/*4 */
697	{0x000016A0, 0xC1009919},
698	/*5 */
699	{0x000016A0, 0xC1407911},
700	/*6 */
701	{0x000016A0, 0xC1803E02},
702	/*7 */
703	{0x000016A0, 0xC1C04D06},
704	/*8 */
705	{0x000016A0, 0xC2008113},
706
707	/*center DQS on read cycle */
708	{0x000016A0, 0xC803000F},
709
710	{0x00001538, 0x0000000B},	/*Read Data Sample Delays Register */
711	{0x0000153C, 0x0000000F},	/*Read Data Ready Delay Register */
712
713	/*init DRAM */
714	{0x00001480, 0x00000001},
715	{0x0, 0x0}
716};
717
718MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = {
719	/* Read Leveling */
720	/*PUP   RdSampleDly (+CL)       Phase   RL ADLL value */
721	/*0 */
722	{0x000016A0, 0xC0020404},
723	/* 1           2               2               6 */
724	{0x000016A0, 0xC042031E},
725	/* 2           2               3               16 */
726	{0x000016A0, 0xC0820411},
727	/* 3           2               1               26 */
728	{0x000016A0, 0xC0C20400},
729	/* 4           2               2               29 */
730	{0x000016A0, 0xC1020404},
731	/* 5           2               2               13 */
732	{0x000016A0, 0xC142031D},
733	/* 6           2               3               6 */
734	{0x000016A0, 0xC182040C},
735	/* 7           2               1               31 */
736	{0x000016A0, 0xC1C2031B},
737	/* 8           2               2               22 */
738	{0x000016A0, 0xC2020112},
739
740	/*  Write Leveling */
741	/* 0 */
742	{0x000016A0, 0xC0004905},
743	/* 1 */
744	{0x000016A0, 0xC040A81D},
745	/* 2 */
746	{0x000016A0, 0xC0804504},
747	/* 3 */
748	{0x000016A0, 0xC0C08013},
749	/* 4 */
750	{0x000016A0, 0xC1004504},
751	/* 5 */
752	{0x000016A0, 0xC140A81D},
753	/* 6 */
754	{0x000016A0, 0xC1805909},
755	/* 7 */
756	{0x000016A0, 0xC1C09418},
757	/* 8 */
758	{0x000016A0, 0xC2006D0E},
759
760	/*center DQS on read cycle */
761	{0x000016A0, 0xC803000F},
762	{0x00001538, 0x00000009},	/*Read Data Sample Delays Register */
763	{0x0000153C, 0x0000000D},	/*Read Data Ready Delay Register */
764	/* init DRAM */
765	{0x00001480, 0x00000001},
766	{0x0, 0x0}
767};
768
769#endif /* __AXP_TRAINING_STATIC_H */
770