1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6#ifndef _MV_DDR_SYS_ENV_LIB_H
7#define _MV_DDR_SYS_ENV_LIB_H
8
9#include "ddr_ml_wrapper.h"
10
11/* device revision */
12#define DEV_ID_REG			0x18238
13#define DEV_VERSION_ID_REG		0x1823c
14#define REVISON_ID_OFFS			8
15#define REVISON_ID_MASK			0xf00
16
17#define MPP_CONTROL_REG(id)		(0x18000 + (id * 4))
18#define GPP_DATA_OUT_REG(grp)		(MV_GPP_REGS_BASE(grp) + 0x00)
19#define GPP_DATA_OUT_EN_REG(grp)	(MV_GPP_REGS_BASE(grp) + 0x04)
20#define GPP_DATA_IN_REG(grp)		(MV_GPP_REGS_BASE(grp) + 0x10)
21#define MV_GPP_REGS_BASE(unit)		(0x18100 + ((unit) * 0x40))
22
23#define MPP_REG_NUM(GPIO_NUM)		(GPIO_NUM / 8)
24#define MPP_MASK(GPIO_NUM)		(0xf << 4 * (GPIO_NUM - \
25					(MPP_REG_NUM(GPIO_NUM) * 8)));
26#define GPP_REG_NUM(GPIO_NUM)		(GPIO_NUM / 32)
27#define GPP_MASK(GPIO_NUM)		(1 << GPIO_NUM % 32)
28
29/* device ID */
30/* Board ID numbers */
31#define MARVELL_BOARD_ID_MASK		0x10
32
33/* Customer boards for A38x */
34#define A38X_CUSTOMER_BOARD_ID_BASE	0x0
35#define A38X_CUSTOMER_BOARD_ID0		(A38X_CUSTOMER_BOARD_ID_BASE + 0)
36#define A38X_CUSTOMER_BOARD_ID1		(A38X_CUSTOMER_BOARD_ID_BASE + 1)
37#define A38X_MV_MAX_CUSTOMER_BOARD_ID	(A38X_CUSTOMER_BOARD_ID_BASE + 2)
38#define A38X_MV_CUSTOMER_BOARD_NUM	(A38X_MV_MAX_CUSTOMER_BOARD_ID - \
39					 A38X_CUSTOMER_BOARD_ID_BASE)
40
41/* Marvell boards for A38x */
42#define A38X_MARVELL_BOARD_ID_BASE	0x10
43#define RD_NAS_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 0)
44#define DB_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 1)
45#define RD_AP_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 2)
46#define DB_AP_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 3)
47#define DB_GP_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 4)
48#define DB_BP_6821_ID			(A38X_MARVELL_BOARD_ID_BASE + 5)
49#define DB_AMC_6820_ID			(A38X_MARVELL_BOARD_ID_BASE + 6)
50#define A38X_MV_MAX_MARVELL_BOARD_ID	(A38X_MARVELL_BOARD_ID_BASE + 7)
51#define A38X_MV_MARVELL_BOARD_NUM	(A38X_MV_MAX_MARVELL_BOARD_ID - \
52					 A38X_MARVELL_BOARD_ID_BASE)
53
54/* Marvell boards for A39x */
55#define A39X_MARVELL_BOARD_ID_BASE	0x30
56#define A39X_DB_69XX_ID			(A39X_MARVELL_BOARD_ID_BASE + 0)
57#define A39X_RD_69XX_ID			(A39X_MARVELL_BOARD_ID_BASE + 1)
58#define A39X_MV_MAX_MARVELL_BOARD_ID	(A39X_MARVELL_BOARD_ID_BASE + 2)
59#define A39X_MV_MARVELL_BOARD_NUM	(A39X_MV_MAX_MARVELL_BOARD_ID - \
60					 A39X_MARVELL_BOARD_ID_BASE)
61
62struct board_wakeup_gpio {
63	u32 board_id;
64	int gpio_num;
65};
66
67enum suspend_wakeup_status {
68	SUSPEND_WAKEUP_DISABLED,
69	SUSPEND_WAKEUP_ENABLED,
70	SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
71};
72
73/*
74 * GPIO status indication for Suspend Wakeup:
75 * If suspend to RAM is supported and GPIO inidcation is implemented,
76 * set the gpio number
77 * If suspend to RAM is supported but GPIO indication is not implemented
78 * set '-2'
79 * If suspend to RAM is not supported set '-1'
80 */
81
82#define MV_BOARD_WAKEUP_GPIO_INFO {	\
83	{RD_NAS_68XX_ID, -2 },		\
84	{DB_68XX_ID,	 -1 },		\
85	{RD_AP_68XX_ID,	 -2 },		\
86	{DB_AP_68XX_ID,	 -2 },		\
87	{DB_GP_68XX_ID,	 -2 },		\
88	{DB_BP_6821_ID,	 -2 },		\
89	{DB_AMC_6820_ID, -2 },		\
90};
91
92enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void);
93u32 mv_ddr_sys_env_get_cs_ena_from_reg(void);
94
95#endif /* _MV_DDR_SYS_ENV_LIB_H */
96