10Sdukemenu "i.MX9 DDR controllers" 22362Sohair depends on ARCH_IMX9 30Sduke 40Sdukeconfig IMX9_DRAM 50Sduke bool "imx9 dram" 60Sduke select IMX_SNPS_DDR_PHY 70Sduke 80Sdukeconfig IMX9_LPDDR4X 90Sduke bool "imx9 lpddr4 and lpddr4x" 100Sduke select IMX9_DRAM 110Sduke help 120Sduke Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC. 130Sduke 140Sdukeconfig IMX9_DRAM_PM_COUNTER 150Sduke bool "imx9 DDRC performance monitor counter" 160Sduke default y 170Sduke help 180Sduke Enable DDR controller performance monitor counter for reference events. 192362Sohair 202362Sohairconfig SAVED_DRAM_TIMING_BASE 212362Sohair hex "Define the base address for saved dram timing" 220Sduke help 230Sduke after DRAM is trained, need to save the dram related timming 240Sduke info into memory for low power use. 250Sduke default 0x2051C000 260Sduke 270Sdukeendmenu 280Sduke