1menu "i.MX8ULP DDR controllers"
2	depends on ARCH_IMX8ULP
3
4config IMX8ULP_DRAM
5	bool "imx8m dram"
6
7config IMX8ULP_DRAM_PHY_PLL_BYPASS
8	bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK"
9	depends on IMX8ULP_DRAM
10
11config SAVED_DRAM_TIMING_BASE
12	hex "Define the base address for saved dram timing"
13	help
14	  The DRAM config timing data need to be saved into sram
15	  for low power use.
16	default 0x20055000
17
18endmenu
19